KR101478508B1 - Wafer level fan out package and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor package, and more particularly, to a wafer-level fan-out package using a compression mold wafer and a through-mold via, and a method of manufacturing the same.
That is, according to the present invention, a mold interposer having a through-mold via formed in the periphery of each chip formed in a wafer state is disposed, and then a mold interposer including a chip is molded to form a chip, The present invention provides a wafer-level fan-out package having a novel structure that can greatly shorten the process of forming the existing through-mold via, and a manufacturing method thereof.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer-level fan-

The present invention relates to a semiconductor package, and more particularly, to a wafer-level fan-out package using a compression mold wafer and a through-mold via, and a method of manufacturing the same.

A basic structure of a semiconductor package includes a substrate such as a lead frame, a substrate, a circuit film, etc., a semiconductor chip attached to the substrate, conductive connecting means for electrically connecting the substrate and the semiconductor chip in a conductive manner, A molding compound resin that encloses the semiconductor chip to protect it from the outside, and input / output means that is fused to the substrate to finally output a signal of the semiconductor chip.

In recent years, the chip scale packaging technology, which packages each chip at a wafer level and manufactures chips at a size close to that of a chip, is applied as a result of demanding high integration and seeking miniaturization and light weight shortening have.

As an example of the chip scale package, a wafer level fan-in package in which input and output terminals such as a solder ball for electrical signal transmission are electrically connected in the area of each chip, and a chip- And a wafer-level fan-out package that extends the conductive line to the outside of the area of the insulating layer and fuses the input / output terminals to the extended portion.

Here, a conventional fan-out type wafer level package, which is one of the chip scale packages, and a manufacturing process thereof will be described with reference to FIGS. 2A to 2H.

First, the bottom surface of each chip 10 separated from the wafer state is attached to a bonding surface such as a tape or a carrier at a predetermined interval, and a surface having a bonding pad serving as an input / output pad of an electrical signal is attached to the bonding surface Reference).

Next, all of the individual chips 10 are molded together with the molding compound resin 30 so as to be sealed with the molding compound resin 30 having a constant thickness over the upper and side surfaces of each chip 10 (see FIG. 2B) ).

Subsequently, when the molding compound resin 30 including the individual chips 10 is removed from the bonding surface, the individual chip bottoms (the side having the bonding pads) are exposed to the outside, and the molding compound resin 30 ) Is performed so that the bottom surface, including the top surface, becomes an even surface, and the cleaning process for the chip bottom surface proceeds.

Next, a process of forming a lower wiring line (RDL, redistribution layer) 32, which is a kind of metal wiring line, is performed from the bonding pad 12 of each chip 10 to a desired position of the bottom surface of the molding compound resin 30 (See FIG. 2C).

When the input / output terminals such as the solder balls are attached to the bonding pads of the respective chips forming fine pitches of the rewiring lines, the input / output terminals are contacted with each other, Refers to a metal wiring line extending outwardly from a bonding pad so that it can be attached at intervals.

At this time, a passivation film is usually formed on the surface of the chip except the bonding pad, and a rewiring line is formed thereon by a plating process. Water, various foreign substances and the like are prevented from permeating through the rewiring line, An insulating passivation for preventing a short circuit phenomenon between lines is formed, and the detailed forming process will be omitted.

Next, a process of forming the through-mold via 22 in the molding compound resin 30 by laser machining proceeds (see FIGS. 2D and 2E).

The through vias 22 are formed at regular intervals on the chip 10 at the same positions with respect to the chip 10. The through vias 22 extend from the upper surface of the molding compound resin 30 to the bottom surface where the lower re- (See FIG. 2D) of forming via holes 26 by machining, dehumidifying the inner diameter of the via holes and foreign matters around the via holes 26, Plating or filling a conductive metal material 28 (e.g., a metal paste) (see FIG. 2E), and the like.

The process of forming the upper rewiring line 34 in the same manner as the method of forming the lower rewiring line 32 from the upper end face of the through-mold via 22 to a desired position of the upper surface of the molding compound resin 30 (See FIG. 2F).

Next, a process of fusing the input / output terminal 36 such as a solder ball to the end portion of the upper redistribution line 34 extending from the upper surface of the molding compound resin 30 to a desired position, that is, the ball pad portion 2g).

Finally, the process of sowing along the sawing line (each package boundary line of the molding compound resin) proceeds to form the individual chip 10 and the through-mold via 22 formed in the periphery thereof, as shown in FIG. And a solder ball 36, and the like.

However, there is a problem in that a lot of laser drilling is performed to form through-mold vias in the molding compound resin around each chip, a process of cleaning foreign materials generated in laser drilling, a plating process or a metal paste Filling process, and the like, and thus the number of processes increases and the manufacturing cost increases.

In particular, if the laser drilling is performed accurately from the upper surface of the molding compound resin to the rewiring position of the bottom surface, the rewiring serves as a stopper for the laser. On the other hand, if the laser drilling is not performed correctly, A defect may occur that a hole is formed in the passivation layer.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a mold interposer in which a mold interposer having through- A wafer-level fan-out package of a new structure capable of greatly shortening a process of forming a conventional through-hole via via a process such as forming a conductive line to the top and bottom of a molding compound resin, And a manufacturing method thereof.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a chip; A mold interposer previously formed in a structure in which a plurality of through mold vias are formed at regular intervals and disposed adjacent to both sides or all sides of the chip; A molding compound resin which is molded by molding and sealing the chip and the mold interposer and exposing the bottom surface of the chip and the upper and lower surfaces of the mold interposer; A lower growing line formed by a plating process from a bonding pad formed on a bottom surface of the chip to a lower end of a through-mold via of the mold interposer past the molding compound resin; An upper growth line formed by a plating process from an upper end of the through-mold via of the mold interposer to a desired upper surface position of the molding compound resin; An input / output terminal electrically conductively fused to the ball pad of the upper rewiring line; The present invention provides a wafer-level fan-out package.

Preferably, the mold interposer is formed to have a height higher than the height of the chip and a height equal to the height of the molding compound resin.

More preferably, the mold interposer has through-mold vias arranged in a two-row arrangement along the length direction, and a sowing line is formed at the center between the two rows.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: fabricating a mold interposer having a plurality of through vias formed at regular intervals; Placing a mold interposed with a desired size on both sides or at four sides of the chip sown in the wafer state; Molding and sealing the chip and the mold interposer with a molding compound resin while exposing and molding the bottom surface of the chip and the upper and lower surfaces of the mold interposer; Forming a lower rewiring line from a bonding pad formed on a bottom surface of the chip through a molding compound resin to a lower end of a through-mold via of a mold interposer using a plating process; Forming an upper rewiring line using a plating process from an upper end of the through-mold via of the mold interposer to a desired upper surface position of the molding compound resin; Fusing an input / output terminal to a ball pad of the upper rewiring line; The present invention also provides a method of manufacturing a wafer-level fan-out package.

According to a preferred embodiment of the present invention, the step of fabricating the mold interposer comprises the steps of: molding the molding resin at a wafer level; Forming a plurality of via holes passing through the molding resin body at regular intervals; Plating or filling a conductive metal material in the via hole to complete the through-mold via; Sawing the molding resin along the transverse and longitudinal directions to include a desired number of through mold vias; .

The forming of the via hole may include: forming a metal film on a bottom surface of the molding resin body using a plating process; Performing laser drilling on the upper surface of the molding resin body until the metal film is exposed; A process of back-grinding and removing the metal film; .

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

According to the present invention, a mold interposer having a through-mold via is formed in advance and disposed in the vicinity of each chip in a wafer state, and then a wafer-level fan-out package can be manufactured. The manufacturing cost and the manufacturing cost can be greatly reduced as compared with a method in which a through-mold via is formed in the periphery thereof.

In addition, since the mold interposer having the number of through vias required can be sowed to a desired size, it is advantageous that it can be used in compatibility with a fan out package having a different structure.

Further, when a mold interposer is manufactured, a metal film serving as a stopper for the laser is formed on the entire bottom surface thereof, so that laser drilling can be carried out without limitation, and thus laser drilling is not accurately performed on a molding compound resin The damage to the passivation layer can be completely eliminated.

That is, since the through-mold vias are formed in the mold interposer in advance, when the through-mold vias are formed in the molding compound resin after the rewiring is formed, the laser drilling becomes inaccurate and the passivation layer around the rewiring line is damaged .

FIGS. 1A to 1H are cross-sectional views illustrating a wafer-level fan-out package and a method of manufacturing the same according to the present invention,
FIGS. 2A through 2H are cross-sectional views illustrating a conventional wafer-level fan-out package and a method of manufacturing the same.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1A to 1H.

The present invention is focused on manufacturing a fan-out package after pre-fabricating a mold interposer in which a through-mold via is formed and arranging it around each chip sowed in a wafer state.

To this end, the step of fabricating the mold interposer 20 in which a plurality of through-mold vias 22 are formed is preceded.

First, in order to manufacture the mold interposer 20, a molding resin body 25 is formed by injecting a molding compound resin into a mold mold at a wafer level and curing it.

Next, a process of forming a plurality of via holes 26 passing through the molding resin body 25 at equal intervals in order to form the through-mold via 22 in the molding resin body 25 at the wafer level (See FIG. 1A).

In order to form the via hole 26, a metal film 29 serving as a stopper during laser drilling is formed on the bottom surface of the molding resin body 25 using a plating process or a separate metal plate is attached.

Laser drilling is performed on the upper surface of the molding resin body 25 and laser drilling is performed until the metal film 29 is exposed to form a plurality of via holes 26 in the molding resin body 25 .

At this time, when the via hole 26 is formed from the top surface to the bottom surface of the molding resin body 25 by the laser drilling, the metal film 29 present on the bottom surface of the molding resin 25 is pressed against the stopper .

Next, the mold interposer 20 in which the through-mold via 22 is formed in the molding resin 25 is completed by plating or filling the conductive metal material 28 in each via hole 26 (see FIG. 1B) .

After the via hole 26 is formed by the laser drilling, the metal film 29 of the molding resin 25 is filled with the conductive metal material 28 so that the top and bottom of the completed through- A back grinding process is performed (FIG. 1C).

Hereinafter, a process of manufacturing the fan-out package of the present invention using the pre-fabricated mold interposer will be described.

In order to manufacture the wafer level fan-out package using the mold interposer 20, the mold interposer 20 is sowed to a desired size.

That is, the molding resin body 25 is sown to a desired size along the lateral and longitudinal directions so that the desired number of through-mold vias 22 are included.

Next, the mold interposer 20 sown at both sides or at four positions of the chip 10 sown in the wafer state is disposed adjacent to the chip interposer 20 (see Fig. 1D).

The chip 10 and the mold interposer 20 are placed in a predetermined mold and then molded and sealed with a molding compound resin 30 so that the bottom surface of the chip 10 and the mold interposer 20 The molding step is performed while exposing the upper and lower surfaces (see Fig. 1E).

The mold interposer 20 is higher than the height of the chip 10 and has the same height as the molding compound resin 30 so that the mold interposer 20 including the through- Is exposed to the outside.

In another embodiment, the entire surface of the chip 10 and the mold interposer 20 is molded so as to be sealed with the molding compound resin 30, and then the mold interposer 20 including the through- So that the upper and lower surfaces of the base 20 can be exposed to the outside.

Next, the bonding pad 12 formed on the bottom surface of the chip 10 passes through the molding compound resin 30 to the lower end of the through-mold via 22 of the mold interposer 20, (See Fig. 1F).

Subsequently, a step of forming the upper rewiring line 34 is performed from the upper end of the through-mold via 22 of the mold interposer 20 to a desired upper surface of the molding compound resin 30 using a plating process 1g).

Of course, during the process of forming the lower rewiring line 32 and the upper rewiring line 34, a passivation film is usually formed on the chip except for the bonding pad, and a rewiring line is formed thereon using a plating process , And a process of forming an insulating passivation for preventing a short-circuit phenomenon of a re-wiring line is formed thereon.

As the through-mold via 22 is formed first in the mold interposer 20 and then the upper and lower re-wiring lines are formed, the conductive connection state between the through-mold via 22 and the re-wiring line can be reliably ensured.

That is, as described above, a re-wiring line is first formed from the bonding pad of the chip to the desired position of the bottom of the molding compound resin, and then a via hole of the through-mold via via laser drilling is formed in the upper portion of the molding compound resin However, according to the present invention, since the through-mold via 22 is first formed in the mold interposer 20 and then the upper and lower portions of the molding compound resin are formed on the upper and lower portions of the molding compound resin, The conductive connection state between the through-mold via 22 and the re-wiring line can surely be ensured by forming the through-via holes 22 and the conductive upper and lower re-wiring lines.

Then, a step of fusing an input / output terminal 36 such as a solder ball to the ball pad of the upper redistribution line 34 is performed (refer to FIG. 1H) so as to be connected to a mother board of the electronic device and input / output an electric signal.

In the meantime, as a preferred embodiment of the present invention, the mold interposer 20 has through-mold vias 22 formed in a two-row arrangement along the longitudinal direction, and a sowing line 24 is formed at the center between the two rows.

Thus, singing is performed along the sawing lines 24 of the through-mold vias 22, which in turn make up the two-row array, to singulate into individual fan-out packages (see FIG.

As described above, according to the present invention, since the mold interposer having the through-mold vias formed thereon is manufactured in advance and disposed in the vicinity of each chip in the wafer state, manufacturing costs and cost can be greatly reduced without defects compared with the conventional fan- It is possible to provide a wafer-level fan-out package of a new structure.

10: Chip
12: bonding pad
20: Mold interposer
22: Through Mold Via
24: Sowing line
25: Molding resin body
26:
28: conductive metal material
30: Molding compound resin
32: Lower growth line
34: Upper rebar
36: I / O terminal

Claims (6)

A chip 10 sown in a wafer state;
A plurality of through vias 22 are formed in a two-row array along the longitudinal direction, and a sowing line 24 is formed at the center between the two rows, and are disposed adjacent to or on both sides of the chip 10 A mold interposer 20;
A molding compound resin 30 which molds and encapsulates the chip 10 and the mold interposer 20 so as to expose the bottom surface of the chip 10 and the top and bottom surfaces of the mold interposer 20;
The lower wiring line 32 formed by the plating process from the bonding pad 12 formed on the bottom surface of the chip 10 to the lower end of the through-mold via 22 of the mold interposer 20 through the molding compound resin 30 )and;
An upper rewiring line 34 formed by a plating process from an upper end of the through-mold via 22 of the mold interposer 20 to a desired upper surface of the molding compound resin 30;
An input / output terminal (36) which is conductively fused to the ball pad of the upper redistribution line (34);
Wherein the wafer-level fan-out package comprises:
The method according to claim 1,
Wherein the mold interposer (20) is formed to be higher than the height of the chip (10) and at the same height as the height of the molding compound resin (30).
delete A process of molding the molding resin body 25 at a wafer level and a process of forming a plurality of via holes 26 passing through the molding resin body 25 upward and downward at regular intervals; Filling or filling the material 28 to complete the through-mold via 22 and sintering the molding resin 25 along the transverse and longitudinal directions to include the desired number of through-mold vias 22 Fabricating a mold interposer (20) having a structure in which a plurality of through mold vias (22) are formed at regular intervals;
Sawing the mold interposer (20) to a desired size and arranging the mold interposer (20) adjacent to the sown chip (10) at both sides or at four locations in the wafer state;
Molding and sealing the chip 10 and the mold interposer 20 with a molding compound resin 30 so as to expose and mold the bottom surface of the chip 10 and the upper and lower surfaces of the mold interposer 20;
The lower rewiring line 32 is formed by plating from the bonding pad 12 formed on the bottom surface of the chip 10 to the lower end of the through-mold via 22 of the mold interposer 20 through the molding compound resin 30, ; ≪ / RTI >
Forming an upper redistribution line 34 from a top of the through-mold via 22 of the mold interposer 20 to a desired top surface of the molding compound 30 using a plating process;
Fusing the input / output terminal (36) to the ball pad of the upper redistribution line (34);
≪ / RTI > The method of claim 1, further comprising:
delete The method of claim 4,
The process of forming the via hole 26 includes:
Forming a metal film (29) on the bottom surface of the molding resin body (25) by a plating process;
Performing laser drilling on the upper surface of the molding resin body (25) until the metal film (29) is exposed;
A process of back-grinding and removing the metal film 29;
≪ RTI ID = 0.0 > 1, < / RTI >

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