KR101376654B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having various screen shapes, and more particularly, to a liquid crystal display device having an improved screen quality by compensating for line loads of gate lines and data lines. The present invention provides a semiconductor device comprising: a substrate; A plurality of gate lines and data lines intersecting longitudinally and horizontally on the substrate, the plurality of gate lines being different from each other in length; A pixel electrode and a common electrode provided for each pixel; A common voltage line supplying a common voltage to the common electrode; A plurality of first compensation capacitors provided with the plurality of gate lines and the common voltage line overlapping each other, and having a capacitance inversely proportional to the length of the gate line, and compensating for the same capacitance of the parasitic capacitor of each gate line; A plurality of second compensation capacitors provided to overlap each of the plurality of data lines and the common voltage line, and having a capacitance inversely proportional to the length of the data line to compensate for the same parasitic capacitor of each data line; Lt; / RTI >

LCD, line load

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a screen having various shapes, and more particularly, to a liquid crystal display device having an improved screen quality by compensating line loads of gate lines and data lines.

Generally, the liquid crystal display device has a tendency of widening its application range due to features such as light weight, thinness, and low power consumption driving. Accordingly, liquid crystal display devices are widely used as portable computers such as notebook PCs, office automation devices, and audio / video devices.

In general, a liquid crystal display device displays a desired image on a screen by controlling a light transmission amount according to an image signal applied to a plurality of switching elements for control arranged in a matrix form.

The liquid crystal display includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled therebetween; And a driver for supplying scan signals and image information to the liquid crystal panel to operate the liquid crystal panel.

In the liquid crystal display having the above configuration, the user's demand for a model having a screen having various functions or various shapes is increasing. Accordingly, researches on liquid crystal displays having screens of various shapes including semicircles, circles, etc., which are not universal rectangles, have been made.

A conventional liquid crystal display having such a screen having various shapes will be described with reference to FIG. 2 as shown in FIG. 1.

FIG. 1 is a block diagram of a general liquid crystal display, and FIG. 2 is a plan view of a liquid crystal display having a curved shape at both corners of an upper portion of the screen of FIG. 1.

As shown in Figs. 1 and 2, a conventional general liquid crystal display device includes a substrate 1; A plurality of gate lines (GL) and data lines (DL) which cross each other on the substrate (1) vertically and horizontally to define pixels (2), each of which has a length different from each other; A timing controller 13 generating a plurality of control signals using signals input from the outside and rearranging and outputting pixel data from the outside; A power supply unit 14 for outputting a plurality of supply voltages by converting a voltage input from the outside; A pixel electrode 3 and a common electrode 4 provided for each pixel 2; A common voltage line 5 for supplying a common voltage Vcom from the power supply unit 14 to the common electrode 4; A gate driver 11 driving the gate line GL by using a control signal from the timing controller 13 and a supply voltage from the power supply unit 14; A data driver 12 for driving the data line DL by using the control signal from the timing controller 13, the pixel data and the supply voltage from the power supply unit 14; .

As shown in FIG. 2, a liquid crystal display device having a curved shape at both edges of the screen is different from a liquid crystal display device having a general rectangular screen, and the lengths of the plurality of gate lines GL are not the same, and the data line ( The length of DL) is also not the same.

Therefore, the line loads formed for each gate line GL or data line DL, that is, line resistance and parasitic capacitor, are different for each line. In this case, the magnitude of the line resistance and the capacitance of the parasitic capacitor rise in proportion to the length of the corresponding gate line GL or data line DL.

That is, since the line resistances and parasitic capacitors of the gate lines GL are different because the lengths of the gate lines GL are not the same, the degree of delay of a signal transmitted to each pixel 2 through the gate line GL is delayed. Is different for each gate line GL, and a defect occurs in the displayed screen. In addition, since the line resistance and parasitic capacitor of each data line DL are different because the length of each data line DL is not the same, a data signal transmitted to each pixel 2 through the data line DL is delayed. As the degree is different for each data line DL, a defect occurs in the displayed screen.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to provide a compensation resistor and a compensation capacitor in a gate line or a data line having different lengths, thereby providing line resistance and parasitics of each gate line or data line. By setting the capacitors to be the same, it is to provide a liquid crystal display device having improved quality of the displayed screen.

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A liquid crystal display device according to an embodiment of the present invention, a substrate; A plurality of gate lines and data lines intersecting longitudinally and horizontally on the substrate, the plurality of gate lines being different from each other in length; A timing controller generating a plurality of control signals using signals input from the outside and rearranging and outputting pixel data from the outside; A power supply unit converting a voltage input from the outside to output first and second power voltages; A gate driver for driving a gate line using the control signal from the timing controller and the first and second power voltages from the power supply unit; A data driver for driving a data line using a control signal from the timing controller, pixel data, and first and second power voltages from a power supply; A plurality of gate lines overlapping the line to which the second power supply voltage is supplied and a plurality of gate lines, and formed to have a capacity inversely proportional to the length of the gate line, thereby compensating for the same capacitance of the parasitic capacitor of each gate line; 1 'compensation capacitor; A plurality of data lines overlap with a line to which the first or second power supply voltage is supplied, and are formed to have a capacitance inversely proportional to the length of the data line, thereby compensating for the same capacitance of each parasitic capacitor. A plurality of second 'compensation capacitors; .

In the liquid crystal display according to the present invention having the above-described configuration, the liquid crystal display having improved display quality by compensating for line loads formed differently according to gate lines or data lines having different lengths in liquid crystal displays having various screen shapes. There is an advantage to provide a display device.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

First, a first embodiment of the present invention will be described with reference to FIG. 3.

As shown in FIG. 3, the liquid crystal display according to the first embodiment of the present invention includes a substrate 101; A plurality of gate lines (GL) and data lines (DL), which are vertically intersected on the substrate (101) to define pixels (102), some of which have different lengths; A pixel electrode 103 and a common electrode 104 provided for each pixel 102; A common voltage line 105 for supplying a common voltage Vcom to the common electrode 104; The plurality of gate lines GL and the common voltage line 105 overlap each other, and are formed to have a size inversely proportional to the length of the gate line GL. A plurality of first compensation capacitors 106 that compensate for equality; The plurality of data lines DL and the common voltage line 105 overlap each other, and are formed to have a size inversely proportional to the length of the data line DL. A plurality of second compensation capacitors 107 compensating for equality; . In addition, the liquid crystal display according to the first exemplary embodiment of the present invention is formed on the plurality of gate lines GL to have a size inversely proportional to the length of the gate line GL, so that each gate line GL is formed. A plurality of first compensation resistors 108 are additionally provided to compensate for the same line resistance, and are formed to have a size inversely proportional to the length of the data lines DL on the data lines DL. Thus, a plurality of second compensation resistors 109 are provided to compensate for the same line resistance of each data line DL.

3 illustrates only a thin film transistor array substrate, which is a lower substrate, among upper and lower substrates constituting a liquid crystal panel of a liquid crystal display for convenience of description.

The substrate 101 shown in FIG. 3 has a curved shape at both corners of the top, but the present invention is not limited thereto, and the shape of the substrate 101 according to the present invention does not depart from the gist of the present invention. It can be a variety of shapes, such as a semi-circle or a circle.

In the substrate 101, a gate line GL and a data line DL intersect vertically and horizontally to define a pixel 102, and each of the pixels 102 includes a thin film transistor 115 as a switching element.

The substrate 101 includes a gate driver 111 for driving a gate line GL and a data driver 112 for driving a data line DL.

In FIG. 3, the gate driver 111 includes one gate drive integrated circuit 111a and the data driver 112 includes two data drive integrated circuits 112a and 112b. However, the present invention is limited thereto. The number of gate drive integrated circuits constituting the gate driver 111 and the number of data drive integrated circuits constituting the data driver 112 may be changed depending on the model of the liquid crystal display.

As illustrated in FIG. 3, the pixel electrode 103 connected to the drain terminal of the thin film transistor is formed in each pixel 102. The pixel electrode 103 is connected to the drain terminal of the thin film transistor 115 of the pixel, and a plurality of pixel electrodes 103 are formed in a direction parallel to the data line DL.

Each pixel 102 is provided with a common electrode 104 together with the pixel electrode 103, and the common electrode 104 is formed to cross and cross the pixel electrode 103.

The common electrode 104 is supplied with a common voltage Vcom from the common line 105a branched from the common voltage line 105. Referring to FIG. 3, the common voltage line 105 has an edge of the substrate 101. It is formed along the, so as to overlap the end of the gate line (GL) or the data line (DL). Here, the common voltage line 105 is supplied with a common voltage Vcom from the common voltage terminal 110 as shown in FIG. 3, and the common voltage terminal 110 receives a common voltage from a power supply unit (not shown). To be supplied. Here, the power supply unit will refer to FIG. 1, which shows a liquid crystal display according to the related art.

3 illustrates the liquid crystal display according to the first embodiment of the present invention, the common voltage line 105 is provided in the shape of a closed curve along the edge of the substrate 101. However, the common voltage according to the present invention is illustrated in FIG. The line 105 is not limited to this and various examples are possible without departing from the gist of the present invention. That is, the common voltage line 105 may be provided in various forms such as two straight lines instead of closed curves along the edge of the substrate 101.

Referring to FIG. 3, a plurality of first compensation capacitors 106 having a capacitance inversely proportional to the length of the gate lines GL are provided in the plurality of gate lines GL formed on the substrate 101.

The first compensation capacitor 106 is formed by overlapping a portion of the gate line GL with a portion of the line branched from the common voltage line 105. That is, as shown in FIG. 3, the first compensation capacitor 106 has a large area of a portion of the gate line GL and a large area of a portion of the line branched from the common voltage line 105. It may be prepared by overlapping each other.

4A, the first compensation capacitor 106 is formed by overlapping the gate line GL and the common voltage line 105 with the gate insulating layer 120 and the protective layer 121 interposed therebetween. do. Here, the gate insulating film 120 is a film formed on the entire substrate 101 on which the gate line GL is formed after the gate line GL is formed on the substrate 101 at the time of manufacturing the liquid crystal display device. . The protective layer 121 forms a thin film transistor 115 including a gate line GL and a data line DL on the substrate 101, and then forms a gate line GL and a data line DL. And a film formed over the substrate 101 on which the thin film transistor 115 is formed, and a pixel connected to the drain terminal of the thin film transistor 115 through a contact hole (not shown) on the upper portion of the protective layer 121. The common voltage line 105 is formed including the electrode 103.

The plurality of first compensation capacitors 106 are parasitic capacitors having the same capacitance in all the gate lines GL based on the capacitance of the parasitic capacitor of the gate line GL having the longest length among the plurality of gate lines GL. And the capacitance of the plurality of first compensation capacitors 106 formed between each gate line GL and the common voltage line 105 may be equal to each gate line GL. It is inversely proportional to the length of.

That is, based on the case where the first compensation capacitor 106 is not formed in the gate line GL, the first compensation capacitor 106 is formed in the gate line GL having the parasitic capacitor having the largest capacitance. The gate having the parasitic capacitor having the largest capacitance when the first compensation capacitor 106 having the least capacity or the smallest capacitance is formed and the first compensation capacitor 106 is not formed in the gate line GL. A first compensation capacitor 106 having a capacitance inversely proportional to the length of the gate line GL is formed in the gate line GL having a parasitic capacitor having a smaller capacitance than the line GL.

The capacitance of the first compensation capacitor 106 formed in each gate line GL will be described in more detail with reference to the drawings as follows.

Referring to FIG. 3, the gate line GL has the same length from the first gate line GL1 to the (n-4) th gate line GL (n-4). 3) The length gradually decreases from the gate line GL (n-3) to the nth gate line GLn. Here, the gate line GL has the same length from the first gate line GL1 to the (n-4) th gate line GL (n-4), and has the same length as the (n-3) th gate line. It is for the purpose of explanation of the present invention that the length is gradually decreased from (GL (n-3)) to the n-th gate line GLn, but the present invention is not limited thereto. Depending on the shape, the length of the gate line GL may be different from that shown in FIG. 3.

Therefore, referring to FIG. 3, a first compensation capacitor 106 is not formed in the first gate line GL1 through the (n-4) th gate line G1 (n-4) or the first having the smallest capacitance. A compensation capacitor 106 is formed, and the (n-3) th gate line GL (n-3) is formed from the (n-3) th gate line GL (n-3) to the nth gate line GLn. The first compensation capacitor 106 having a larger capacitance is formed from the to the nth gate line GLn.

As a result, parasitic capacitors formed from the first gate line GL1 to the nth gate line GLn are equally set.

That is, as described above, by forming the first compensation capacitor 106 having a capacitance inversely proportional to the length of each gate line GL, the capacitance of the parasitic capacitor formed in each gate line GL can be set to be the same. .

In the above description and drawings, the first compensation capacitor 106 is formed at one end of the gate line GL and is formed adjacent to the gate driver 111. However, the present invention is not limited thereto. One example of the compensation capacitor 106 may be formed at one end of the gate line GL that is not adjacent to the gate driver 111, or two may be formed at both ends of the gate line GL.

Referring to FIG. 3, the plurality of gate lines GL formed on the substrate 101 are provided with a plurality of first compensation resistors 108 having a size inversely proportional to the length of the gate line GL.

The size of the first compensation resistor 108 provided in each gate line GL is determined based on the size of the line resistance of the gate line GL having the longest length among the plurality of gate lines GL. GL) is designed to have the same size line resistance, which will be described in more detail as follows.

As mentioned above, the gate line GL has the same length from the first gate line GL1 to the (n-4) th gate line GL (n-4), and is equal to (n). -3) The length gradually decreases from the gate line GL (n-3) to the nth gate line GLn.

Accordingly, when the first compensation resistor 108 is not formed in the gate line GL, the first compensation resistor 108 is formed in the gate line GL having the largest line resistance. Or a gate having the largest line resistance when the first compensation resistor 108 having the smallest magnitude is formed and the first compensation resistor 108 is not formed in the gate line GL. A first compensation resistor 108 having a size inversely proportional to the length of the gate line GL is formed in the gate line GL having a line resistance smaller than the line GL.

That is, referring to FIG. 3, a first compensation resistor 108 is not formed in the first gate line GL to the (n-4) th gate line GL (n-4), or the smallest sized resistor. A first compensation resistor 108 is formed, and the (n-3) th gate line GL (n-3) is formed from the (n-3) th gate line GL (n-3) to the nth gate line GLn. ), A larger first compensation resistor 108 is formed toward the n-th gate line GLn.

Accordingly, the line resistances formed from the first gate line GL1 to the nth gate line GLn are equally set.

That is, as described above, by forming the first compensation resistor 108 having a size inversely proportional to the length of each gate line GL, the size of the line resistance formed in each gate line GL may be set to be the same. .

In the above description and drawings, the first compensation resistor 108 is formed at one end of the gate line GL and is formed adjacent to the gate driver 111, but the present invention is not limited thereto. One example of the compensation resistor 108 may be formed at one end of the gate line GL that is not adjacent to the gate driver 111, or two may be formed at both ends of the gate line GL.

Referring to FIG. 3, the plurality of data lines DL formed on the substrate 101 are provided with a plurality of second compensation capacitors 107 having capacitances inversely proportional to the lengths of the data lines DL.

The second compensation capacitor 107 is formed by overlapping a portion of the data line DL with a portion of the line branched from the common voltage line 105. That is, as shown in FIG. 3, the second compensation capacitor 107 has a large area of a portion of the data line DL and a large area of a portion of the line branched from the common voltage line 105. It may be prepared by overlapping each other.

Referring to FIG. 4B, the second compensation capacitor 107 is formed by overlapping the data line DL and the common voltage line 105 with the protective layer 121 interposed therebetween. The passivation layer 121 forms the thin film transistor 115 including the gate line GL and the data line DL on the substrate 101, and then the gate line GL, the data line DL, and the thin film. A pixel formed on the entire substrate 101 on which the transistor 115 is formed, and a pixel electrode connected to the drain terminal of the thin film transistor 115 through a contact hole (not shown) on the protective layer 121. In addition to 103, a common voltage line 105 is formed.

The second compensation capacitor 107 may have parasitic capacitors of the same capacitance based on the capacitance of the parasitic capacitor of the data line DL having the longest length among the plurality of data lines DL. As such, the capacitance of the second compensation capacitor 107 formed between each data line DL and the common voltage line 105 is inversely proportional to the length of each data line DL. do.

That is, when the second compensation capacitor 107 is not formed on the data line DL, the second compensation capacitor 107 is formed on the data line DL having the parasitic capacitor having the largest capacitance. The data having the parasitic capacitor having the largest capacitance when the second compensation capacitor 107 is not formed or the smallest capacitance is formed and the second compensation capacitor 107 is not formed in the data line DL. A second compensation capacitor 107 having a capacitance inversely proportional to the length of the data line DL is formed in the data line DL having a parasitic capacitor having a smaller capacitance than the line DL.

For example, the capacitance of the second compensation capacitor 108 formed in each data line DL will be described in more detail with reference to the accompanying drawings.

Referring to FIG. 3, the length of the data line DL gradually increases from the first data line DL1 to the fourth data line DL4, and starts from the fifth data line DL5. n-4) The length up to the data line DL (n-4) is the same and the length starting from the (n-3) th data line DL (n-3) to the nth data line DLn. Gradually decreases. Herein, the length of the data line DL gradually increases from the first data line DL1 to the fourth data line DL4, and starts from the fifth data line DL5 (n-4). The length up to the data line DL (n-4) is the same, and the length gradually decreases from the (n-3) th data line DL (n-3) to the nth data line DLn. As an example, the present invention is not limited thereto, and the length of the data line may be different from that shown in FIG. 3 according to the shape of the substrate 101.

Therefore, referring to FIG. 3, a second compensation capacitor 107 is not formed in the fifth data line DL5 to the (n-4) th data line DL (n-4) or the second having the smallest capacitance. The compensation capacitor 107 is formed, and the second data having a smaller capacitance from the first data line DL1 to the fourth data line DL4 starting from the first data line DL1 to the fourth data line DL4. A compensation capacitor 107 is formed, and the (n-3) th data line DL (n-3) is formed from the (n-3) th data line DL (n-3) to the nth data line DLn. A second compensation capacitor 107 of larger capacitance is formed starting from and going to the n-th data line DLn.

Accordingly, parasitic capacitors formed from the first data line DL1 to the nth data line DLn are set in the same manner.

That is, by forming the second compensation capacitor 107 having a capacitance inversely proportional to the length of each data line DL, as described above, the capacitance of the parasitic capacitor formed in each data line DL can be set to be equal. .

In the above description and drawings, the second compensation capacitor 107 is formed at one end of the data line DL but is formed adjacent to the data driver 112. However, the present invention is not limited thereto. The two compensation capacitors 107 may be formed at one end of the data line DL that is not adjacent to the data driver 112 or two may be formed at both ends of the data line DL.

Referring to FIG. 3, a plurality of second compensation resistors 109 having a size inversely proportional to the length of the data line DL are provided in the plurality of data lines DL formed on the substrate 101.

The size of the second compensation resistor 109 provided in each data line DL is determined based on the size of the line resistance of the data line DL having the longest length among the plurality of data lines DL. DL) is designed to have the same line resistance, which will be described in more detail as follows.

As mentioned above, the length of the data line DL gradually increases from the first data line DL1 to the fourth data line DL4 and starts at the fifth data line DL5. (n-4) The data lines DL (n-4) have the same length, starting from the (n-3) th data line DL (n-3) to the nth data line DLn. The length gradually decreases.

Accordingly, when the second compensation resistor 109 is not formed on the data line DL, a second compensation resistor 109 is formed on the data line DL having the largest line resistance. Data having the largest line resistance when the second compensation resistor 109 is not formed or the smallest size is formed and the second compensation resistor 109 is not formed on the data line DL. A second compensation resistor 109 having a size inversely proportional to the length of the data line DL is formed in the data line DL having a line resistance smaller than the line DL.

That is, referring to FIG. 3, a second compensation resistor 109 is not formed in the fifth data line DL5 to the (n-4) th data line DL (n-4), or the smallest sized resistor. The second compensation resistor 109 is formed, and the first data line DL1 to the fourth data line DL4 have a smaller first size starting from the first data line DL1 to the fourth data line DL4. The second compensation resistor 109 is formed, and the (n-3) th data line DL (n-3) is formed from the (n-3) th data line DL (n-3) to the nth data line DLn. ), The second compensation resistor 109 having a larger size is formed as the n th data line DLn increases.

Accordingly, the line resistances formed from the first data line DL1 to the nth data line DLn are equally set.

That is, as described above, by forming the second compensation resistor 109 having a size inversely proportional to the length of each data line DL, the size of the line resistance formed in each data line DL may be set to be the same. .

In the above description and drawings, the second compensation resistor 109 is formed at one end of the data line DL but is formed adjacent to the data driver 112. However, the present invention is not limited thereto. The two compensation resistors 109 may be formed at one end of the data line DL that is not adjacent to the data driver 112 or two may be formed at both ends of the data line DL.

≪ Embodiment 2 >

Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 5 to 7. In the description of the liquid crystal display device according to the second embodiment of the present invention, components not shown in FIGS. 5 to 7 will be referred to FIG. 3, which shows the liquid crystal display device according to the first embodiment of the present invention.

5 to 7, a liquid crystal display according to a second embodiment of the present invention includes a substrate (see 101 in FIG. 3); A plurality of gate lines (GL) and data lines (DL) different in length from each other to define pixels (see 102 in FIG. 3) crossing vertically and horizontally on the substrate; A timing controller 213 for generating a plurality of control signals using signals input from the outside and rearranging and outputting pixel data from the outside; A power supply unit 214 for converting a voltage input from the outside to output first and second power voltages VDD and VSS; A gate driver 211 driving the gate line GL by using the control signal from the timing controller 213 and the first and second power voltages VDD and VSS from the power supply unit 214; A data driver 212 for driving the data line DL by using the control signal from the timing controller 213, the pixel data and the first and second power voltages VDD and VSS from the power supply unit 214; A line to which the second power supply voltage VSS is supplied and a plurality of gate lines GL overlap each other and are formed to have a capacity inversely proportional to the length of the gate line GL. A first 'compensation capacitor C1 for compensating for the same capacitance of the parasitic capacitor; The line to which the first or second power supply voltages VDD and VSS are supplied and the plurality of data lines DL overlap each other and are formed to have a capacity inversely proportional to the length of the data line DL. A plurality of second 'compensation capacitors C2 for compensating for the same capacitance of the parasitic capacitor of the DL; .

The gate driver 211 of the liquid crystal display according to the second exemplary embodiment of the present invention uses the control signal input from the timing controller 213 to control the first control signal Q1 and the second control signal. A gate control unit 211c for outputting Q2; A first transistor T1 for supplying a first power voltage VDD or a clock signal CLK to a gate line GL in response to a first control signal Q1 from the gate controller 211c, and the gate And a second transistor T2 for supplying a second power supply voltage VSS to the gate line GL in response to the second control signal Q2 from the controller 211c. A buffer unit 211d for buffering the output signal; . Here, the ratio W / L of the channel width W to the channel length L of the first and second transistors T1 and T2 is formed to be proportional to the length of the corresponding gate line GL. The line resistance of the line GL is compensated to have the same magnitude.

In addition, the data driver 212 included in the liquid crystal display according to the second exemplary embodiment of the present invention outputs the third control signal Q3 by using the control signal input from the timing controller 213. A data controller 212c for converting and outputting pixel data from the timing controller 213; A third transistor T3 configured to output the pixel data converted to the data line DL in response to the third control signal Q3 from the data control unit 212c, and output from the data control unit 212c. A buffer unit 212d for buffering a signal to be used; . Here, the ratio W / L of the channel width W to the channel length L of the third transistor T3 is formed in proportion to the length of the corresponding data line DL, so that each data line DL is Branches are compensated for equal line resistance.

The liquid crystal display according to the second exemplary embodiment of the present invention having such a configuration will now be described in detail.

5 illustrates a gate driver 211, a power supply unit 214, and a timing controller 213 among elements constituting the liquid crystal panel of the liquid crystal display for convenience of description.

Referring to FIG. 3, the substrate is a thin film transistor array substrate which is a lower substrate among upper substrates and lower substrates constituting the liquid crystal panel of the liquid crystal display, and has both curved upper edges. As described above, the substrate according to the second embodiment of the present invention also has a curved shape in which both edges of the substrate are curved like the substrate according to the first embodiment, but the present invention is not limited thereto. Various shapes such as a semi-circle or a circle may be used without departing from the gist of the present invention.

The substrate is defined by crossing the gate line GL and the data line DL vertically and horizontally on the substrate, and each pixel is formed with a thin film transistor (see 115 in FIG. 3) as a switching element.

In the lengths of the gate line GL and the data line DL according to the second embodiment of the present invention, FIG. 3 is a view illustrating a liquid crystal display device according to the first embodiment of the present invention for convenience of description. See you.

That is, the gate line GL according to the second embodiment of the present invention has the same length from the first gate line GL1 to the (n-4) gate line GL (n-4). (n-3) The length gradually decreases from the gate line GL (n-3) to the nth gate line Gln. Here, the gate line GL has the same length from the first gate line GL1 to the (n-4) th gate line GL (n-4), and has the same length as the (n-3) th gate line. It is for the purpose of explanation of the present invention that the length is gradually reduced from (GL (n-3)) to the n-th gate line GLn, but the present invention is not limited thereto. The length of the gate line GL may be sufficiently changed.

In addition, the length of the data line DL according to the second embodiment of the present invention increases from the first data line DL1 to the fourth data line DL4, and the fifth data line DL5. The lengths are the same from the (n-4) th data line DL (n-4) to the nth data line starting at the (n-3) th data line DL (n-3). Up to DLn), its length gradually decreases. Herein, the length of the data line DL gradually increases from the first data line DL1 to the fourth data line DL4, and starts from the fifth data line DL5 (n-4). The length up to the data line DL (n-4) is the same, and the length gradually decreases from the (n-3) th data line DL (n-3) to the nth data line DLn. For the purpose of explanation, the present invention is not limited thereto, and the length of the data line DL may be sufficiently changed according to the shape of the substrate.

Referring to FIG. 4, the liquid crystal display according to the second exemplary embodiment of the present invention generates a plurality of control signals using signals input from the outside and rearranges and outputs the pixel data input from the outside. It is provided. The plurality of control signals output from the timing controller 213 are transmitted to the gate driver 211 and the data driver 212, and the gate driver 211 and the data driver 212 use the plurality of control signals to gate. The line GL and the data line DL are driven.

In addition, the liquid crystal display according to the second exemplary embodiment of the present invention converts a voltage input from an external device to convert a first voltage VDD, a second voltage VSS, etc. required to drive each component of the liquid crystal display. An output power supply unit 214 is provided. As described above, the first voltage VDD and the second voltage VSS are supplied to the gate driver 211 and the data driver 212 among the plurality of supply powers output from the power supply unit 214. The data driver 212 drives the gate line GL and the data line DL using the first voltage VDD and the second voltage VSS.

The gate driver 211 uses the control signal input from the timing controller 213 and the first power voltage VDD and the second power voltage VSS input from the power supply unit 214 to form the gate line GL. Drive sequentially one by one. The gate driver 211 includes a gate controller 211c and a buffer unit 211d. The gate driver 211 will be described in detail as follows.

The gate controller 211c outputs the first control signal Q1 and the second control signal Q2 using the control signal input from the timing controller 213. The first control signal Q1 is a signal for driving the gate line GL by supplying a first power supply voltage VDD to the gate line GL, and the second control signal G2 is a gate line (G2). This is a signal for not driving the gate line GL by supplying the second power supply voltage VSS to the GL.

The first control signal Q1 and the second control signal Q2 are supplied to the buffer unit, that is, the first transistor T1 and the second transistor T2.

The buffer unit 211d includes the first transistor T1 and the second transistor T2 and includes a plurality of buffers 211e connected to each gate line GL.

The gate terminal of the first transistor T1 is connected to the line to which the first control signal Q1 is supplied from the gate controller 211c, and the source terminal is connected to the first power voltage VDD or the clock signal from the gate controller 211c. CLK is connected to the supply line, and the drain terminal is connected to the corresponding gate line GL. The gate terminal of the second transistor T2 is connected to the line to which the second control signal Q2 is supplied, the source terminal is connected to the line to which the second power supply voltage VSS is supplied, and the drain terminal is connected to the corresponding gate line. Connected to GL.

Accordingly, the first transistor T1 applies the first power voltage VDD or the clock signal CLK to the corresponding gate line GL in response to the first control signal Q1 from the gate controller 211c. The gate line GL is driven, and the second transistor T2 supplies the second power voltage VSS to the corresponding gate line GL in response to the second control signal Q2 from the gate controller 211c. As a result, the gate line GL will not be driven.

FIG. 6 is a plan view illustrating the first transistor T1. Referring to this, the channel width W of the first transistor T1 is the length of the side where the source electrode and the drain electrode face each other, and the channel length L is The source electrode and the drain electrode are spaced apart from each other, and the same applies to the second transistor T2.

Although not shown in detail in the drawings, the ratio W / L of the channel width W to the channel length L of the first transistor T1 and the second transistor T2 is determined by the first transistor T1 and the second transistor. It is proportional to the length of the gate line GL to which the transistor T2 itself is connected.

That is, the ratio W / L of the channel width W to the channel length L of the first transistor T1 and the second transistor T2 connected to each gate line GL is determined by the number of gate lines GL. ) Is the largest when the first gate line GL1 having the longest length is connected to the (n-4) th gate line GL (n-4), and the (n-3) th gate line GL (n -3)) to be connected to the n-th gate line GLn, it is formed to become smaller as it goes from the (n-3) th gate line GL (n-3) to the n-th gate line GLn.

Accordingly, the output resistance of the buffer 111e connected to each gate line GL is set in inverse proportion to the length of the gate line GL.

That is, as described above, the ratio W / L of the channel width W to the channel length L of the plurality of first transistors T1 and the second transistor T2 is determined by the first transistor T1 and the first transistor T1. By forming the two transistors T2 to be proportional to the length of the connected gate line GL, the output resistance of each buffer 211e and the line resistance of the gate line GL are set to be equal. .

In FIG. 5, only the first ′ compensation capacitor C1 formed on the first gate line GL1 and the first ′ compensation capacitor C1 formed on the nth gate line Gln are shown in FIG. 5.

Referring to FIG. 5, a plurality of first 'compensation capacitors C1 formed by overlapping a line to which the second power supply voltage VSS is supplied and each gate line GL are provided in the plurality of gate lines GL. The first ′ compensation capacitor C1 has a capacitance inversely proportional to the length of the gate line GL to which the first compensation capacitor C1 is connected.

That is, the capacitance of the first 'compensation capacitor C1 formed between the line to which the second power supply voltage VSS is supplied and each gate line GL is the first having the longest length among the plurality of gate lines GL. When the gate line GL1 is connected to the (n-4) th gate line GL (n-4), the gate line GL1 is not the smallest or formed, and the gate line GL1 from the (n-3) th gate line GL (n-3) When connected to the n-th gate line GLn, the n-th gate line GLn is formed to gradually increase from the (n-3) th gate line GL (n-3) to the nth gate line GLn.

Accordingly, parasitic capacitors formed from the first gate line GL1 to the nth gate line GL are set to be the same.

That is, as described above, by forming a plurality of first 'compensation capacitors C1 having capacitances inversely proportional to the lengths of the gate lines GL, the capacitances of the parasitic capacitors formed in each gate line GL may be equal. Can be set to

Referring to FIG. 6, the data driver 212 receives a control signal and pixel data from the timing controller 213, and receives a first power voltage VDD and a second power voltage VSS from the power supply 214. The data driver 212 is a line based on the gate line GL after appropriately converting pixel data using the control signal, the first power supply voltage VDD and the second power supply voltage VSS. Output to data line DL at the same time by minute.

The data driver 212 includes a data controller 212c and a buffer unit 212d. The data driver 212 will be described in detail as follows.

The data controller 212c outputs a third control signal Q3 using the control signal input from the timing controller 213. The data controller 212c converts the pixel data input from the timing controller 213 as appropriate and outputs the converted data. The third control signal Q3 is a signal for buffering and supplying pixel data to the data line DL.

The third control signal Q3 is supplied to the buffer unit 212d, that is, the third transistor T3.

The buffer unit 212d includes a third transistor T3 and includes a plurality of buffers 212e connected to each data line DL.

That is, the gate terminal of the third transistor T3 is connected to the line from which the third control signal Q3 is supplied from the data controller 212c and the source terminal is connected to the line from which the pixel data is output from the data controller 212c. The drain terminal is connected to the corresponding data line DL.

Therefore, the third transistor T3 supplies pixel data to the corresponding data line DL in response to the third control signal Q3 from the data controller 212c. Here, the third control signal Q3 is simultaneously supplied to all of the third transistors T3 connected to each data line DL, thereby simultaneously supplying pixel data to all data lines DL.

Although not shown in detail in the drawing, the channel width W of the third transistor T3 is the length of the side where the source electrode and the drain electrode face each other, and the channel length L is the distance between the source electrode and the drain electrode.

The ratio W / L of the channel width W to the channel length L of the third transistor T3 is proportional to the length of the data line DL to which the third transistor T3 itself is connected.

That is, the ratio (W / L) of the channel width (W) to the channel length (L) of the third transistor (T3) connected to the data line (DL) is from the first data line (DL1) to the fourth data line ( When connected to the DL4, the first data line DL1 to the fourth data line DL4 becomes larger and larger, and the fifth to fifth data lines DL5 having the longest length among the plurality of data lines DL. n-4) is largest when connected to the data line DL (n-4), and is connected to the nth data line DLn starting from the (n-3) th data line DL (n-3). In this case, starting from the (n-3) th data line DL (n-3), the number decreases gradually toward the nth data line DLn.

Accordingly, the output resistance of the buffer 212e connected to each data line DL is set in inverse proportion to the length of the data line DL.

That is, as described above, the ratio W / L of the channel width W to the channel length L of the plurality of third transistors T3 is proportional to the length of the data line DL to which the third transistor T3 is connected. The sum of the output resistance of each buffer 212e and the magnitude of the line resistance of the data line DL is set to be equal.

In FIG. 7, only the second ′ compensation capacitor C2 formed on the first data line DL1 and the second ′ compensation capacitor C2 formed on the nth data line DLn are illustrated in FIG. 7.

Referring to FIG. 7, a plurality of data lines DL are formed by overlapping a line supplied with a first power supply voltage VDD or a line supplied with a second power supply voltage VSS and each data line DL. The second 'compensation capacitor C2 is provided, and the second' compensation capacitor C2 has a capacity inversely proportional to the length of the data line DL to which it is connected.

That is, the capacitance of the second 'compensation capacitor C2 formed between the line to which the first power supply voltage VDD is supplied or the line to which the second power supply voltage VSS is supplied and each data line DL is the first data. When connected from the line DL1 to the fourth data line DL4, the first data line DL1 is gradually smaller from the fourth data line DL4, and has the longest length among the plurality of data lines DL. When the fifth data line DL5 is connected to the (n-4) th data line DL (n-4), it is the smallest or not formed, and the (n-3) th data line DL (n− 3)) from the (n-3) th data line DL (n-3) to the nth data line DLn.

Accordingly, parasitic capacitors formed from the first data line DL1 to the nth data line DLn are set in the same manner.

That is, as described above, by forming a plurality of second 'compensation capacitors C2 having capacitances inversely proportional to the lengths of the data lines DL, the capacitances of the parasitic capacitors formed in each data line DL are the same. Can be set to

1 is a block diagram showing a general liquid crystal display device.

FIG. 2 is a plan view illustrating the liquid crystal display of FIG. 1. FIG.

3 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention;

4A is a cross-sectional view illustrating a plane taken along line II ′ of FIG. 3, and FIG. 4B is a cross-sectional view illustrating a plane taken along line II-II ′ of FIG. 3.

FIG. 5 is a diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention, and illustrates a plan view of a gate driver and a first ′ compensation capacitor. FIG.

FIG. 6 is a plan view illustrating the first transistor of FIG. 4. FIG.

FIG. 7 is a view showing a liquid crystal display according to a second embodiment of the present invention, showing a data driver and a second 'compensation capacitor. FIG.

DESCRIPTION OF REFERENCE NUMERALS

GL (GL1 ~ GLn): Gate Line DL (DL1 ~ DLn): Data Line

105: common voltage line

106: first compensation capacitor 107: second compensation capacitor

108: first compensation resistor 109: second compensation resistor

111, 211: gate driver 211, 212: data driver

211c: gate controller 211d: buffer portion 211e: buffer

212c: Data control unit 212d: Buffer unit 212e: Buffer

T1, T2, T3: first, second, third transistor

C1: first 'compensation capacitor C2: second' compensation capacitor

Claims (10)

delete delete delete delete Board; A plurality of gate lines and data lines intersecting longitudinally and horizontally on the substrate, the plurality of gate lines being different from each other in length; A timing controller generating a plurality of control signals using signals input from the outside and rearranging and outputting pixel data from the outside; A power supply unit converting a voltage input from the outside to output first and second power voltages; A gate driver for driving the plurality of gate lines using a control signal from the timing controller and first and second power voltages from the power supply unit; A data driver for driving the plurality of data lines using control signals from the timing controller, pixel data, and first and second power voltages from the power supply unit; The lines to which the second power supply voltage is supplied and the plurality of gate lines overlap each other, and are formed to have a capacity inversely proportional to the length of each of the plurality of gate lines, so that the capacitances of the parasitic capacitors of the gate lines are the same. A plurality of first 'compensation capacitors to compensate; A line of the first or second power supply voltage and the plurality of data lines overlap each other, and are formed to have a capacity inversely proportional to the length of each of the plurality of data lines. Includes a plurality of second 'compensation capacitors to compensate for the same, The gate driver includes: A gate controller configured to output a first control signal and a second control signal using the control signal input from the timing controller; A first transistor supplying a first power supply voltage or a clock signal to each of the plurality of gate lines in response to a first control signal from the gate controller, and the plurality of gates in response to a second control signal from the gate controller And a buffer unit configured to include a second transistor configured to supply a second power supply voltage to each of the lines, and to buffer a signal output from the gate controller. delete The method of claim 5, wherein the ratio of the channel width (W) to the channel length (L) of the first transistor (W / L) is formed in proportion to the length of the corresponding gate line, the size of the line resistance of each gate line And are compensated to be equal. The method of claim 5, wherein the ratio of the channel width (W) to the channel length (L) of the second transistor (W / L) is formed in proportion to the length of the corresponding gate line, the size of the line resistance of each gate line And are compensated to be equal. The method of claim 5, wherein the data driver, A data control unit outputting a third control signal using the control signal input from the timing control unit, and converting and outputting pixel data from the timing control unit; A buffer unit including a third transistor configured to output converted pixel data to each of the data lines in response to a third control signal from the data control unit to buffer a signal output from the data control unit; And the liquid crystal display device. 10. The method of claim 9, wherein the ratio (W / L) of the channel width (W) to the channel length (L) of the third transistor is formed to be proportional to the length of the corresponding data line, so that the magnitude of the line resistance of each data line has. And are compensated to be equal.

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