KR101277990B1 - Optical sensor and solid-state imaging device - Google Patents

Abstract

The solid-state imaging device includes a plurality of pixels stored in a one-dimensional or two-dimensional array, each of which is connected to a photodiode which receives light and generates photocharges, and during the storage operation, the photodiode An overflow gate for transferring photocharges that overflow the diode, and a storage capacitor element for storing the photocharges transferred by the overflow gate during the storage operation.

Solid-state imaging device, photodiode

Description

Optical sensor and solid-state imaging device {OPTICAL SENSOR AND SOLID-STATE IMAGING DEVICE}

1 is an equivalent circuit diagram corresponding to Patent Document 1. FIG.

2 is an equivalent circuit diagram corresponding to Patent Document 2. FIG.

3 is an equivalent circuit diagram corresponding to Patent Document 3. FIG.

4 is an equivalent circuit diagram corresponding to Patent Document 4. FIG.

5 is an equivalent circuit diagram corresponding to Non-Patent Document 3. FIG.

6 is an equivalent circuit diagram of pixels of a solid-state imaging device according to the first embodiment of the present invention.

7 is a schematic plan view of a pixel of a solid-state imaging device according to the first embodiment of the present invention.

8A is a schematic cross-sectional view showing regions of a photodiode PD1, an overflow gate LO4, and a storage capacitor CS5 in a pixel of the solid-state imaging device according to the first embodiment of the present invention.

8B shows regions of the photodiode PD1, the transfer transistor T2, the floating region FD3, the storage transistor S7, and the storage capacitor CS5 in the pixel of the solid-state imaging device according to the first embodiment of the present invention. Schematic cross section showing.

9 is a drive timing diagram of the solid-state imaging device according to the first embodiment of the present invention.

10 is a block diagram of a solid-state imaging device according to the first embodiment of the present invention.

11 is an equivalent circuit diagram of pixels of a solid-state imaging device according to a second embodiment of the present invention.

12 is a schematic plan view of a pixel of a solid-state imaging device according to a second embodiment of the present invention.

13 is a drive timing diagram of the solid-state imaging device according to the second embodiment of the present invention.

Fig. 14 is an equivalent circuit diagram of a pixel of the solid-state imaging device according to the third embodiment of the present invention, which corresponds to the equivalent circuit diagram of the first embodiment.

15 is a schematic plan view of a pixel of a solid-state imaging device according to a third embodiment of the present invention, corresponding to the plan view of the first embodiment.

Fig. 16 is an equivalent circuit diagram of a pixel of the solid-state imaging device according to the third embodiment of the present invention, which corresponds to the equivalent circuit diagram of the second embodiment.

Fig. 17 is a schematic plan view of the pixel of the solid-state imaging device according to the third embodiment of the present invention, which corresponds to the plan view of the second embodiment.

18 is a cross-sectional view of a pixel of a solid-state imaging device according to a third embodiment of the present invention.

19 is a cross-sectional view of a pixel of a solid-state imaging device according to a fourth embodiment of the present invention.

20 is a cross-sectional view of a pixel of a solid-state imaging device according to a fourth embodiment of the present invention.

21 is a sectional view of a pixel of a solid-state imaging device according to a fourth embodiment of the present invention.

Fig. 22 is an equivalent circuit diagram of two pixels of the solid-state imaging device according to the fifth embodiment of the present invention.

23 is a schematic plan view of two pixels of a solid-state imaging device according to a fifth embodiment of the present invention.

24 is a drive timing diagram of the solid-state imaging device according to the fifth embodiment of the present invention.

Fig. 25 is an equivalent circuit diagram of four pixels of the solid-state imaging device according to the sixth embodiment of the present invention.

Fig. 26 is a schematic plan view of four pixels of a solid-state imaging device according to the sixth embodiment of the present invention.

27 is a drive timing diagram of the solid-state imaging device according to the sixth embodiment of the present invention.

Fig. 28 is a sectional view of a pixel of a solid-state imaging device according to the seventh embodiment of the present invention.

29 is a sectional view of a pixel of a solid-state imaging device according to a seventh embodiment of the present invention.

30 is a sectional view of a pixel of a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 31 is a sectional view of a pixel of a solid-state imaging device according to the seventh embodiment of the present invention.

32 is a cross-sectional view of a pixel of a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 33 is a sectional view of a pixel of a solid-state imaging device according to the seventh embodiment of the present invention.

34 is a cross-sectional view of a pixel of a solid-state imaging device according to the seventh embodiment of the present invention.

35 is a sectional view of a pixel of the solid-state imaging device according to the seventh embodiment of the present invention.

36 is a cross-sectional view of a pixel of a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 37 is a sectional view of a pixel of the solid-state imaging device according to the seventh embodiment of the present invention.

38 is a sectional view of a pixel of the solid-state imaging device according to the seventh embodiment of the present invention.

Fig. 39 is a sectional view of a pixel of the solid-state imaging device according to the seventh embodiment of the present invention.

40 is a cross-sectional view of a pixel of a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 41 is a sectional view of a pixel of the solid-state imaging device according to the seventh embodiment of the present invention.

The present invention relates to an optical sensor and a solid-state imaging device, and more particularly, to a one-dimensional or two-dimensional solid-state imaging device of a CMOS or CCD sensor, and a driving method for the above-mentioned solid-state imaging device.

Image sensors such as CMOS (complementary metal-oxide semiconductor) image sensors and CCD (charge coupled device) image sensors have been enhanced in their properties and find wide application in digital cameras, cellular phones with cameras, scanners, and the like. .

However, further improvement of the characteristics of the image sensor is required. One of them is to extend the operating range. The operating range of a conventionally used image sensor is, for example, staying in units of 3 to 4 digits (60 to 80 dB), so that the expected is at least 5 to 6 digits, comparable to the visual or silver-halide film. It is an implementation of a good quality image sensor with an operating range of (100 to 120 dB).

As a technique for improving the image quality of the image sensor described above, for example, S. Inoue et al., "IEEE Workshop on CCDs and Advanced Image Sensor 2001, pp. 16-19" (hereinafter referred to as "non-patent document 1") The noise signal generated in the floating region adjacent to the photodiode of each pixel and the noise signal added to the optical signal, and taking the difference therebetween, for the purpose of achieving high sensitivity and high S / N ratio It describes a technique for reducing the However, even by this method, the range of operation that can be achieved is in the state of up to 80 dB. The realization of a wider operating range is required.

For example, as shown in Fig. 1, Japanese Patent Application Laid-Open No. 2003-134396 (hereinafter referred to as "Patent Document 1") is a small capacitor located on the high sensitivity and low luminance side. Connect not only the floating region with (C1) but also the floating region with the large capacitor (C2) located on the low sensitivity and high luminance side to the photodiode (PD), the low-luminance side output (OUT1) and the high-low side A technique for extending the operating range by outputting to each of the outputs OUT2 is disclosed.

In addition, as shown in Fig. 2, Japanese Patent Application Laid-Open No. 2000-165754 (hereinafter referred to as "Patent Document 2") makes the capacitor CS variable in the floating diffusion (FD) region. A technique for extending the operating range is disclosed. Furthermore, by dividing the image into images having at least two different exposure time periods, including an image having a short exposure time period corresponding to the high luminance side and an image having a long exposure time period corresponding to the low luminance side, the operating range There is another disclosed technique to extend it.

In addition, as shown in Fig. 3, Japanese Patent Application Laid-Open No. 2002-77737 (hereinafter referred to as "Patent Document 3"), and IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, pp. 16-19 (hereinafter referred to as “non-patent document 2”) includes a transistor switch T between the photodiode PD and the capacitor C, and an optical signal on both the photodiode PD and the capacitor C. FIG. Turn on switch T in the first exposure period to store charge, and switch T in the second exposure period to store optical charge in photodiode PD in addition to the charge stored in the first exposure period. By turning off, a technique for extending the operating range is disclosed. Here, these documents disclose therein that, when providing light irradiation beyond the saturation value, excessive charge is discharged through the reset transistor (R).

In addition, as shown in Fig. 4, Japanese Patent Application Laid-Open No. 5-90556 (hereinafter referred to as "Patent Document 4") uses a larger capacitor than that of the prior art as a photodiode PD. A technique is disclosed that makes it possible to address imaging with high-brightness.

In addition, as shown in FIG. 5, the Journal of the Institute of Image Information and Television Engineers, Vol. 57, 2003 (hereinafter referred to as “non-patent document 3”) stores and outputs an optical current signal from the photodiode PD during algebraically converting the signal by a logarithmic conversion circuit constituted by a combination of MOS transistors. A technique for extending the operating range is disclosed.

In the method described in Patent Documents 1, 2, 3 and Non-Patent Document 2, or in the method of imaging with two or more different exposure time periods, the imaging on the low luminance side and the imaging on the high luminance side are performed at different times. This causes a problem because a time lag occurs between at least two imaging times, which impairs the quality of a moving image.

Further, in the above-described methods described in Patent Documents 4 and 3, although a wide operating range can be achieved by imaging corresponding to the high-luminance side, low sensitivity and low S / N are also involved in the image on the low-luminance side. The ratio results in undesirable consequences, thus impairing image quality.

As described above, in an image sensor such as a CMOS image sensor, it is difficult to achieve a wide operating range while maintaining high sensitivity and high S / N ratio. The foregoing applies not only to an image sensor in which pixels are arranged in a two-dimensional array, but also to a linear sensor in which pixels are arranged in a one-dimensional array and an optical sensor without a plurality of pixels.

(summary)

Accordingly, it is an object of the present invention to provide a solid-state imaging device capable of extending the operating range while maintaining high sensitivity and high S / N ratio.

According to the solid-state imaging device of the present invention, a high-sensitivity and high S / N ratio is maintained in low-luminance imaging by a photodiode that receives light and generates and stores photocharges, and the photodiode through an overflow gate By performing a high-brightness image by storing photocharges overflowing the storage capacitor in a storage capacitor, a wide operating range can be achieved.

According to a first aspect of the invention, an optical sensor is provided. The optical sensor is connected to a photodiode that receives light and generates photocharges, an overflow gate that transmits a photocharge that overflows the photodiode during the storage operation, and an overflow gate during the storage operation. Storage capacitor elements for storing photocharges.

The optical sensor further includes a photodiode and a transfer transistor coupled to the floating region, wherein the transfer transistor transfers photocharge from the photodiode to the floating region.

The overflow gate is composed of a junction transistor. In this case, the semiconductor region forming the gate of the junction transistor is connected to the semiconductor region forming the surface region of the photodiode and the well region in which the overflow gate is formed with the photodiode.

The overflow gate is formed at a predetermined depth of the substrate on which the overflow gate is formed. In this case, the overflow gate has a semiconductor layer of the same conductivity type as the channel of the overflow gate, and the semiconductor layer reduces the barrier and punches through the overflow gate.

The storage capacitor element includes a semiconductor region which functions as a lower electrode formed on the surface layer portion of the semiconductor substrate on which the optical sensor is formed, a capacitor insulating film formed on the semiconductor region, and an upper electrode formed on the capacitor insulating film.

The storage capacitor device includes a lower electrode formed on a substrate on which an optical sensor is formed, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film.

The storage capacitor element is formed on the semiconductor region, which functions as a lower electrode formed on the inner wall of the trench formed in the semiconductor substrate on which the optical sensor is formed, the capacitor insulating film formed on the inner wall of the trench, and the capacitor insulating film, and the trench It includes an upper electrode for embedding.

Further, there is provided a solid-state imaging device including a plurality of pixels arranged in a one-dimensional or two-dimensional array, each pixel having the above-described optical sensor.

The overflow gate may be composed of a MOS transistor or a junction transistor.

In addition, another solid-state imaging device including a plurality of pixel blocks is provided. In this apparatus, each of the plurality of pixel blocks includes a plurality of pixels and a single floating region. Each of the plurality of pixels includes a photodiode that receives light and generates photocharges, an overflow gate that is connected to the photodiode and transmits a photocharge that overflows the photodiode during the storage operation, and an overflow gate during the storage operation. A storage capacitor element for storing the transferred photocharges, and a transfer transistor coupled between the photodiode and the single floating region.

The transfer transistor is an ambush channel transistor having a semiconductor layer of the same conductivity type as the channel of the transfer transistor formed from the surface or the vicinity of the surface of the substrate on which the transfer transistor is formed to a predetermined depth.

A solid-state imaging device comprising a plurality of pixels, each pixel having the above-described optical sensor, is connected between a floating region and between a storage transistor element and a reset transistor for discharging signal charges of the floating region, between the floating region and the storage capacitor element. The transistor further includes a transistor provided, an amplifying transistor reading a signal charge as a voltage in the floating region or both the floating region and the storage capacitor element, and a selection transistor connected to the amplifying transistor and selecting a pixel.

The solid-state imaging device is connected to a storage capacitor element and reset transistor for discharging signal charge in the storage capacitor element and the floating region, a transistor provided between the floating region and the storage capacitor element, in the floating region or in both the floating region and the storage capacitor element. An amplifying transistor for reading the signal charge into a voltage, and a selection transistor connected to the amplifying transistor and selecting a pixel.

A solid-state imaging device comprising a plurality of pixels, each pixel having the above-described optical sensor, includes a voltage signal and a floating region or floating region obtained from photocharges transmitted to the floating region or to both the floating region and the storage capacitor element. And noise removing means for taking the difference between the voltage signals at the reset levels on both sides of the storage capacitor elements.

The solid-state imaging device further includes storage means for storing the voltage signal at the reset level of the floating region and the storage capacitor element.

According to another aspect of the invention, a method is provided for outputting a signal from an optical sensor comprising a photodiode and a storage capacitor element. The method includes storing the first photocharge generated by the photodiode before the saturation of the photodiode with the photodiode, storing the second photocharge generated by the photodiode with the storage capacitor element after saturation, and Outputting a signal based on the first and second photocharges.
The overflow gate consists of a MOS transistor coupled between the photodiode and the storage capacitor, the gate electrode of the MOS transistor receiving a signal that determines the storage operation.

(Preferred embodiment)

EMBODIMENT OF THE INVENTION Hereinafter, it demonstrates with reference to the drawing which attaches the solid-state imaging device which concerns on embodiment of this invention. In all of these figures, like reference numerals designate like or equivalent parts.

First Embodiment

6 is an equivalent circuit diagram of a pixel of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 7 is a schematic plan view thereof.

Each pixel includes a photodiode PD1 that receives light, generates and stores photocharges, and is adjacent to the photodiode PD1, and includes a transfer transistor T2 and a transfer transistor T2 that transmit photoelectric charges. Floating region (floating region) FD3 connected to the photodiode PD1 via, an overflow gate which is provided adjacent to the photodiode PD1 and transmits a photocharge which overflows the photodiode PD1 during a storage operation ( LO4), connected to storage capacitor CS5, floating region FD3, which stores photocharges that overflow photodiode PD1 through overflow gate LO4, during storage operation, and to storage capacitor CS5 and floating Storage with reset transistor R6, floating region FD3 and storage capacitor CS5, floating region FD3 or floating region FD3, which are provided between reset transistor R6, floating region FD3 and storage capacitor CS5, which discharge the signal charge of region FD3 Capacitor CS5 includes an amplifying transistor SF8 for reading both signal charges as a voltage, and a selection transistor X9 connected to the amplifying transistor SF8 and selecting a pixel or a pixel block.

In the solid-state imaging device according to the present embodiment, the plurality of pixels each having the above-described arrangement is stored in a two-dimensional or one-dimensional array. In each pixel, the driving lines Φ _LO 10, Φ _T 11, Φ _S 12, and Φ _R 13 each represent an overflow gate LO4, a transfer transistor T2, a storage transistor S7, and a reset transistor ( Is connected to the gate electrodes of R6). Further, the pixel select line Φ _X 14 driven by the low shift register is connected to the gate electrode of the select transistor X9. The output line OUT 15 is also connected to the output side source of the selection transistor X9 and controlled by the column shift register to generate an output.

The configuration of the solid-state imaging device according to the present embodiment is not limited as long as the voltage of the floating region FD3 can be fixed to an appropriate value for allowing the pixel selection operation or the non-selection operation to be performed. Therefore, the selection transistor X9 and the drive line Φ _X ; 14 may be omitted.

FIG. 8A is a schematic cross-sectional view showing regions of the photodiode PD1, the overflow gate LO4, and the storage capacitor CS5 of the pixel of the solid-state imaging device according to the present embodiment, and FIG. 8B is a photodiode PD1 of the pixel. ), A schematic cross-sectional view showing regions of the transfer transistor T2, the floating region FD3, the storage transistor S7, and the storage capacitor CS5.

For example, on the n-type silicon semiconductor substrate (n-sub; 20), a p-type well (p-well) 21 is formed, and an element isolation insulating film separating the individual pixels and the storage capacitor (CS) region. (22, 23, 24, and 25) are formed by the LOCOS method or the like. In addition, p + type isolation regions 26, 27, 28, and 29 are formed in the p type well 21 under the element isolation insulating film separating the pixels. The n type semiconductor region 30 is formed in the p type well 21, and the p + type semiconductor region 31 is formed in the surface layer thereof. By the pn junction, a charge transfer built-in photodiode (PD) is constructed. When light LT enters the depletion layer made by applying a suitable bias to the pn junction, photoelectric charge is generated by the photoelectric effect.

At the end of the n-type semiconductor region 30, a region for blocking the p + -type semiconductor region 31 is formed, and in a region separated by a predetermined distance from the region, the n + -type semiconductor region 32 is a p-type well 21. Is formed on the surface layer.

Further, at the end of the n-type semiconductor region 30, there is another region formed to block the p + -type semiconductor region 31, and functions as a floating region FD in a region separated by a predetermined distance from the other region. The n + type semiconductor region 33 is formed in the surface layer of the p type well 21. In addition, the n + type semiconductor region 34 is formed in a region separated by a predetermined distance from the other regions described above.

Here, in the region associated with the n-type semiconductor region 30 and the n + -type semiconductor region 32, the gate electrode 36 made of polysilicon or the like is formed through the gate insulating film 35 made of silicon oxide or the like. An overflow gate formed over the surface of the 21 and having, as a source / drain, an n-type semiconductor region 30 and an n + -type semiconductor region 32, and having a channel forming a region in the surface layer of the p-type well ( LO) is provided.

Further, in the region associated with the n-type semiconductor region 30 and the n + -type semiconductor region 33, the gate electrode 38 made of polysilicon or the like is formed through the gate insulation film 37 made of silicon oxide or the like. A transfer transistor formed over the surface of the 21 and having, as a source / drain, an n-type semiconductor region 30 and an n + -type semiconductor region 33 and a channel for forming a region in the surface layer of the p-type well ( T) is provided.

Further, in the region associated with the n + type semiconductor region 33 and the n + type semiconductor region 34, the gate electrode 40 made of polysilicon or the like is formed through the gate insulating film 39 made of silicon oxide or the like. A storage transistor S formed on the surface of the surface 21 and having, as a source / drain, an n + type semiconductor region 33 and an n + type semiconductor region 34 and a channel forming a region in the surface layer of the p type well. ) Is provided.

Further, in the region separated by the element isolation insulating films 22 and 23, a p + type semiconductor region 41 serving as a lower electrode is formed in the surface layer of the p type well, and on top of this layer is made of polysilicon or the like. The upper electrode 43 comprised is formed via the capacitor insulation film 42 comprised from silicon oxide etc. These constitute the storage capacitor CS.

An insulating film 44 made of silicon oxide or the like is formed to cover the overflow gate LO, the transfer transistor T, the storage transistor S, and the storage capacitor CS. An opening is provided which extends from the n + type semiconductor region 32 and the n + type semiconductor region 33 to the upper electrode 43 via the n + type semiconductor region 34. Moreover, the wiring 45 which connects the n + type semiconductor region 32 and the upper electrode 43, and the wiring 46 which connects to the n + type semiconductor region 33 are provided.

The drive line Φ _T is connected to the gate electrode 38 of the transfer transistor _T , and the drive line Φ _S is connected to the gate electrode 40 of the storage transistor S.

The drive line Φ _LO is connected to the gate electrode 36 of the overflow gate LO. The drive line Φ _LO may be applied with a drive pulse signal, and may instead be connected to a zero potential as in the case of the p-type well 21. The threshold voltage of the overflow gate LO is transferred to the transfer transistor T so that excess charges beyond the saturation value of the photodiode PD are allowed to flow efficiently through the overflow gate LO to the storage capacitor CS. It is set to a value lower than the threshold voltage of. When the threshold voltages of the overflow gate LO and the transfer transistor T become equal, setting the potential to a value higher than zero potential causes excess charges exceeding the saturation value of the photodiode PD to overflow gate. It is possible to efficiently flow through the LO to the storage capacitor CS.

With respect to other components, that is, the reset transistor R, the amplifying transistor SF, the selection transistor X, the driving lines Φ _R and Φ _X , and the output line OUT, the configuration is equivalent to that of FIG. 6. In order to have the configuration shown in the circuit diagram, they are configured in such a manner that the wiring 46 is connected to an amplifying transistor SF (not shown) in an unillustrated area on the semiconductor substrate 20 shown in FIGS. 8A and 8B. .

Floating region FD and storage capacitor CS constitute capacitors C _FD and C _CS , each having a relatively deep potential, while photodiode PD has a capacitor C _PD having a relatively shallow potential. Configure.

Here, the driving method of the solid-state imaging device according to the present embodiment shown in Figs. 6, 7, 8A, and 8B will be described. 9 is a drive timing diagram of the solid-state imaging device according to the present embodiment.

Before the start of storage, the storage transistor S is first set to on, and the transfer transistor T and the reset transistor R are set to off. At this point, the photodiode PD is completely depleted. Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CS (time: t1). Then, the reset noise of (FD + CS) captured immediately after the reset transistor R is switched off is read out as the noise signal N2 (time: t ₂ ). Here, the noise signal N2 is a fixed pattern noise component and includes a change in the threshold voltage of the amplifying transistor SF. During the storage period (time: t ₃ ), in the state where the storage transistor S, the transfer transistor T, the reset transistor R, and the select transistor X are switched off, the photoelectrodes before saturation are transferred to the photodiode. And the excess photocharge when saturation is exceeded is stored in the storage capacitor CS through the overflow gate LO. This operation allows the charge that overflows the photodiode PD to be used efficiently without wasting. In this method, in both the period before and after saturation, the storage operation is performed by receiving light by the same photodiode PD of each pixel in the same storage period.

After the storage is completed (time: T ₄ ), the select transistor X is switched on. Thereafter, the reset transistor is switched on to reset the floating region FD (time: T ₅ ), and the FD reset noise captured immediately after the reset is read as the noise signal N1 (time: T ₆ ). . Here, the noise signal N1 is a fixed pattern noise component and includes a change in the threshold voltage of the amplifying transistor SF.

Next, the transfer transistor T is switched on to completely transmit the optical signal stored in the photodiode PD to the floating region FD (time: T ₇ ), and the signal is read out as (S1 + N1). do. Thereafter, the storage transistor S is also switched on to completely transfer the photocharge stored in the photodiode PD to the floating region FD and the storage capacitor CS (time: T ₈ ). Charges stored in the photodiode PD, the floating region FD, and the storage capacitor CS are mixed, and the signal is read as (S1 + S2 + N1).

10 is a block diagram of a solid-state imaging device according to the present embodiment. On the periphery of the pixel arrays 100-103 arranged in two dimensions, a low shift register (VSR) 104, a column shift register (HSR) 105, a signal / noise holding unit 106, and an output circuit 107 are provided. It is provided. Here, an example of the pixel arrangement of (2 pixels x 2 pixels) will be described briefly, but the number of pixels is not limited.

The signals sequentially read out from each pixel include noise signal N1, and (an optical signal before saturation, used for charge / voltage conversion in FD) + (noise signal), that is, (S1 + N1); Noise signal N2, and (an additional optical signal before and after saturation, used for charge / voltage conversion in FD and CS) + (noise signal), ie, (S1 + S2 + N2). By the subtraction circuit, the noise removing operation [(S1 + N1)-N1] is performed on the signal before saturation. This removes both random noise components and fixed pattern noise components. That is, the noise N2 on the super saturation side is read immediately after the start of storage, and therefore, when both the random noise component and the fixed pattern noise component are removed, the noise N2 is stored once in the frame memory, and accordingly, The noise removing operation [(S1 + N1)-N1] is performed by the subtraction circuit. Thus, the signal S1 before saturation and the supersaturated side signal S1 + S2, each of which noise is removed, can be obtained. Each of the subtraction circuit and the frame memory may be formed on the image sensor chip or may be formed as a single chip.

If the capacitances of the floating region FD and the storage capacitor CS are C _FD and C _CS , respectively, the expansion ratio of the operating range can be expressed as (C _FD + C _CS ) / C _FD . In practice, however, compared with the case of resetting the floating region FD, in the case of resetting (FD + CS), the clock feed-through in the reset transistor R has a small effect and operates. The saturation voltage of the super saturation side signal S2 becomes higher than the signal S1 before saturation so that the range is increased with an expansion ratio larger than the above-described ratio. In order to efficiently widen the operating range without increasing the pixel size while maintaining the high numerical aperture of the photodiode, it is desirable that a large storage capacity having high area efficiency can be formed.

The design of the wide dynamic range signal can be achieved by selecting either the signal S1 before saturation and the signal S1 + S2 on the supersaturated side, each of which noise is removed. The selection between S1 and (S1 + S2) is accomplished by comparing the preset S1 / (S1 + S2) switching reference voltage and the signal output voltage of S1 and then selecting one of the signals S1 and (S1 + S2). Can be. In order to prevent the switching reference voltage from being affected by the change in the saturation voltage of the pre-saturation signal S1, the switching reference voltage is set lower than the saturation voltage of S1, and at the same time, at the switching point, the supersaturated side signal S1 Set to high voltage to maintain the high S / N ratio of + S2). Here, multiplying the gain of the supersaturated side signal S1 + S2 by the ratio (C _FD + C _CS ) / C _FD ensures that the gain of the signal S1 is matched before this gain is saturated. Thus, it is possible to obtain an image signal having an extended operating range by selective combining of signals linear from low luminance to high luminance.

In this solid-state imaging device, since the signal charge before saturation and the signal charge on the supersaturation side are mixed into the supersaturation side signal S1 + S2, the signal S1 + S2 is the signal charge near the PD saturation of the signal S1 before saturation. It is apparent from the above-described operation to include at least. This increases the tolerance of noise components such as low dark current and reset noise on the supersaturated side. By using the increase in noise tolerance for the supersaturated side (S1 + S2) signal, the potential immediately after the reset of the floating region FD and the storage capacitor CS in the subsequent field is read as N2 'and a fixed pattern noise component By taking the difference for (S1 + S2 + N2) in the preceding field (i.e. (S1 + S2 + N2)-N2 ') in order to eliminate, the periphery of the selective switching point between the signal before saturation and the supersaturated signal Even in a sufficient S / N ratio can be guaranteed.

The read operation of the signal S1 + N1 and the noise signal N1 before saturation includes the elimination of the floating region FD reset noise, and the correction of the change in the threshold voltage of the source follower amplifier is performed. Thus, in the low luminance region, the high S / N ratio (low noise) characteristic can be executed without the occurrence of afterimages. In the same storage period, after storing the charges overflowing the photodiode PD through the overflow gate LO in the storage capacitor CS, in the operation on the super saturation side, signal reading on the low luminance side is performed. After completion of reading, at time t ₈ , the signal charge before saturation remaining in the floating region FD is mixed with the supersaturated signal charge, and the mixed charge is read out. Further, at time t ₈ , upon switching on the storage transistor S, the floating region FD is connected to the storage capacitor CS having a large capacity, and the potential of (FD + CS) goes out in the positive direction. . Thus, the photocharge of the photodiode PD is transmitted completely to (FD + CS) with high efficiency even though the photodiode PD is in a saturation state, so that afterimages do not occur even around the PD saturation.

In addition, even when the storage capacitor CS is saturated, by adjusting the threshold voltages of the reset transistor R and the storage transistor S, the excess charge can be efficiently discharged to the power supply VDD, so that the p-type silicon Screening can be suppressed even when a semiconductor substrate is used. Here, the low side potentials of the reset transistor R and the storage transistor S are set to a value higher than the zero potential.

In this way, in a low luminance image in which the photodiode PD is not saturated, high sensitivity and high S / N ratio can be maintained by the charge signal S1 before saturation obtained by removing noise. In addition, in a high luminance image in which the photodiode PD is saturated, photoelectric charges overflowing the photodiode PD are captured by being stored in the storage capacitor CS, and a high S / N ratio can be maintained, thereby A wide operating range on the high luminance side can be realized by a signal obtained by removing noise, that is, a sum (S1 + S2) of a signal before saturation and a supersaturated charge signal.

As described above, the solid-state imaging device according to the present embodiment can increase the sensitivity on the high luminance side without reducing the sensitivity on the low luminance side, thereby achieving a wide range, and in addition, the range generally used Do not use power supply voltage exceeding. This enables the present solid-state imaging device to achieve miniaturization of future image sensors. In addition, since the addition of components is reduced to a minimum, there is no possibility of causing an increased pixel size.

Also, unlike conventional image sensors that implement a wide operating range, the storage cycle is not divided between the high luminance side and the low luminance side, i.e., without straddling the frame, the present embodiment provides the same storage. Store the photocharge in the cycle. This prevents the deterioration of image quality even in the imaging of moving images.

Regarding the leakage current from the floating region FD, in the image sensor according to the present embodiment, the minimum signal of (S1 + S2) becomes the saturated charge from the photodiode PD, and the image sensor is the floating region. The charge amount larger than the charge amount of the leakage current from (FD) is dealt with. This provides an advantage in fabricating an image sensor that is not damaged by FD leakage.

Second Embodiment

In the solid-state imaging device according to the present embodiment, the circuit configuration of the pixel in the solid-state imaging device according to the first embodiment is changed. FIG. 11 is an equivalent circuit diagram of one pixel of the present embodiment, and FIG. 12 is a schematic plan view thereof.

Each pixel includes a photodiode PD1 that receives light, generates and stores photocharges, and is adjacent to the photodiode PD1, and includes a transfer transistor T2 and a transfer transistor T2 that transmit photoelectric charges. Floating region FD3 connected to the photodiode PD1 through, adjacent to the photodiode PD1, an overflow gate LO4 for transmitting photocharges that overflow the photodiode PD1 during a storage operation, storage It is connected to a storage capacitor CS5, a storage capacitor CS5, which stores photocharges overflowing the photodiode PD1 through an overflow gate LO4 during operation, and is a storage capacitor CS5 and a floating region FD3. The storage transistor S7, the floating region FD3 or the floating region FD3 and the storage capacitor CS5 provided between the reset transistor R6, the floating region FD3 and the storage capacitor CS5, which discharges the signal charge of the ) Amount An amplifying transistor SF8 for reading the signal charge of the side as a voltage, and a selection transistor X9 connected to the amplifying transistor SF8 and selecting a pixel or a pixel block.

As in the case of the first embodiment described above, in the solid-state imaging device according to the present embodiment, a plurality of pixels each having the above-described arrangement are stored in a two-dimensional or one-dimensional array. At each pixel, the driving line (Φ _LO 10, Φ _T 11, Φ _S 12, and Φ _R 13 are connected to the gate electrodes of overflow gate LO4, transfer transistor T2, storage transistor S7, and reset transistor R6, respectively. . Further, the pixel select line Φ _X 14 driven by the low shift register is connected to the gate electrode of the select transistor X9. The output line OUT 15 is also connected to the output side source of the selection transistor X9 and controlled by the column shift register to generate an output.

As in the case of the first embodiment described above, as long as the voltage of the floating region FD3 can be fixed to an appropriate value to enable the selection operation or the non-selection operation of the pixel, the solid according to the present embodiment. The configuration of the imaging device is not limited. Therefore, the selection transistor X9 and the drive line Φ _X ; 14 may be omitted.

In the solid-state imaging device according to the present embodiment, schematic cross-sectional views showing regions of the photodiode PD1, the overflow gate LO4, and the storage capacitor CS5 of the pixel are the same as in FIG. 8A shown in the first embodiment and Therefore, description is omitted to avoid duplication. Moreover, the schematic sectional drawing of this solid-state imaging device which shows the area | region of the photodiode PD1, the transfer transistor T2, the floating region FD3, the storage transistor S7, and the storage capacitor CS5 of a pixel is the same as FIG. 8B. Therefore, description is similarly omitted.

Here, the driving method of the solid-state imaging device according to the present embodiment shown in FIGS. 11 and 12 will be described. 13 is a drive timing diagram of the solid-state imaging device according to the present embodiment.

Prior to storage, the storage transistor S is first set on, and the transfer transistor T and the reset transistor R are set off. At this point, the photodiode PD is in a completely depleted state.

Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CS (time: t ₁ '). Then, the reset noise of the capture region (floating region FD + storage capacitor CS) captured immediately after the reset transistor R is switched off is read out as the noise signal N2 (time: t ₂ ′). Here, the noise signal N2 is a fixed pattern noise component and includes a change in the threshold voltage of the amplifying transistor SF. During the storage period (time: t ₃ '), the photodiode before saturation is in the state where the storage transistor S, the transfer transistor T, the reset transistor R, and the select transistor X are switched off. Stored by PD and stored in storage capacitor CS via overflow gate LO when excess saturation is exceeded. This operation allows the charge that overflows the photodiode PD to be used efficiently without wasting. In this method, in both the period before and after saturation, the storage operation is performed by receiving light by the same photodiode PD of each pixel in the same storage period.

After the storage is completed (time: T ₄ ′), the selection transistor X is switched on, and then the noise signal stored in the photodiode PD is read out. Here, the noise signal N1 is a fixed pattern noise component and includes a change in the threshold voltage of the amplifying transistor SF. Next, the transfer transistor T is switched on to completely transmit the optical signal stored in the photodiode PD to the floating region FD (time: T ₅ '), and the signal is transferred to (S1 + N1). Is read. Thereafter, the storage transistor S is also switched on (time: T ₆ ′) so that the signal charge stored in the photodiode PD is completely transferred to the floating region FD and the storage capacitor CS. Here, the charges stored in the photodiode PD, the floating region FD, and the storage capacitor CS are mixed, and the signal is read as (S1 + S2 + N2).

In the first embodiment, part of the noise signal N2 stored in the floating region FD and the storage capacitor CS was discarded at time t ₆ during the reset operation of the floating region FD. The amount of discarded signal at this time is C _FD / (C _FD + C _CS ) times greater than the noise signal stored in the floating region FD and the storage capacitor CS. In contrast, in the solid-state imaging device according to the present embodiment, there is no possibility that a part of the noise signal is discarded.

The block diagram of the solid-state imaging device according to the present embodiment is the same as that of FIG. 10 shown in the first embodiment, and therefore, description is omitted to avoid duplication. In this embodiment, the signals read out sequentially from each pixel, the expansion ratio of the operating range, and the design of the wide operating range signal are the same as in the above-described first embodiment.

As in the case of the first embodiment, the solid-state imaging device according to the present embodiment can achieve a wide range by increasing the sensitivity on the high luminance side without reducing the sensitivity on the low luminance side, and in addition, in general Do not use a power supply voltage that exceeds the range used. This enables the present solid-state imaging device to achieve miniaturization of future image sensors. In addition, since the addition of the component is reduced to a minimum, there is no possibility of causing an increase in the pixel size.

Also, unlike conventional image sensors that realize a wide operating range, the storage cycle is not divided between the high luminance side and the low luminance side, that is, without straddling the frame, the present embodiment stores the same Store the photocharge in the cycle. This prevents the deterioration of image quality even in the imaging of moving images.

In addition, the leakage current from the floating area FD is read by the capacitance of the floating area FD and the storage capacitor CS, that is, (C _FD + C _CS ) in the image sensor according to the present embodiment. The minimum signal becomes (supersaturated charge) + (charge saturated from photodiode PD) so that the image sensor handles an amount of charge that is greater than the amount of leakage current from the floating region FD. This provides an advantage in fabricating an image sensor that is not damaged by FD leakage.

Third Embodiment

In the solid-state imaging device according to the present embodiment, the overflow gate of the pixel in the solid-state imaging devices according to the first and second embodiments of the present invention is changed. 14 and 15 are equivalent circuit diagrams and schematic cross-sectional views of the pixels of this embodiment, respectively, and these diagrams correspond to respective diagrams of the first embodiment. 16 and 17 are equivalent circuit diagrams and schematic cross-sectional views of the pixels of the present embodiment, and these correspond to the respective views of the second embodiment.

Each pixel includes a photodiode PD1 that receives light, generates and stores photocharges, and is adjacent to the photodiode PD1, and includes a transfer transistor T2 and a transfer transistor T2 that transmit photoelectric charges. Floating region FD3 connected to photodiode PD1 via, overflow gate LO4 'provided adjacent to photodiode PD1 and transmitting photocharges that overflow photodiode PD1 during a storage operation, Connected to a storage capacitor CS5, a storage capacitor CS5, which stores photocharges overflowing the photodiode PD1 through an overflow gate LO4 ', during the storage operation, and floating region FD3 (FIG. 14) or A reset transistor R6 for discharging the signal charge of the storage capacitor CS5 (FIG. 16), a storage transistor S7, a floating region FD3, or a floating region provided between the floating region FD3 and the storage capacitor CS5 ( FD3) and save An amplifying transistor SF8 for reading the signal charges on both sides of the capacitor CS5 as a voltage, and a selection transistor X9 connected to the amplifying transistor SF8 and selecting a pixel or a pixel block.

As in the case of the first and second embodiments described above, in the solid-state imaging device according to the present embodiment, a plurality of pixels each having the above-described arrangement are stored in a two-dimensional or one-dimensional array. In each pixel, the driving lines Φ _T 11, Φ _S 12, and Φ _R 13 are connected to the gate electrodes of the transfer transistor T2, the storage transistor S7, and the reset transistor R6, respectively. Further, the pixel select line Φ _X 14 driven by the low shift register is connected to the gate electrode of the select transistor X9. The output line OUT 15 is also connected to the output side source of the selection transistor X9 and controlled by the column shift register to generate an output.

As in the case of the first embodiment described above, as long as the voltage of the floating region FD3 can be fixed to an appropriate value to enable the selection operation or the non-selection operation of the pixel, the solid according to the present embodiment. The configuration of the imaging device is not limited. Therefore, the selection transistor X9 and the drive line Φ _X ; 14 may be omitted.

18 is a schematic cross-sectional view of a photodiode PD1, an overflow gate LO4, and a storage capacitor CS5 of a pixel in the solid-state imaging device according to the third embodiment. Here, in the region associated with the n-type semiconductor region 30 and the n + -type semiconductor region 32, the p + semiconductor region 50 is formed on the surface of the p-type well 21, and the n-type semiconductor region as a source / drain A junction transistor type overflow gate LO having an 30 and an n + type semiconductor region 32 and having a p + semiconductor region 50 as a gate is formed. The other configurations are the same as in the above-described first embodiment. Here, the p + semiconductor region 50 is electrically connected to the p + semiconductor region 31 and the p-type well 21.

The driving method of the solid-state imaging device according to the present embodiment is the same as in the first and second embodiments. The block diagram of the solid-state imaging device according to the present embodiment is the same as that in FIG. 10 shown in the first embodiment, and therefore, description is omitted to avoid duplication. In this embodiment, the signals read out sequentially from each pixel, the expansion ratio of the operating range, and the design of the wide operating range signal are the same as in the above-described first embodiment.

The solid-state imaging device according to the present embodiment exhibits an effect similar to that in the first and second embodiments, and the p + semiconductor region 50 is electrically connected to the p + semiconductor region 31 and the p-type well 21. Since the solid-state imaging device according to the present embodiment is connected to the first and second embodiments, the wiring number of the drive signals is reduced, and a high density pixel is achieved.

Fourth Embodiment

The solid-state imaging device according to the present embodiment is configured to more smoothly move the charges overflowing the photodiode during charge storage than in the above-described third embodiment.

19 is a solid-state imaging device in which the overflow gate LO is an ambush channel transistor having a semiconductor layer of the same conductivity as the channel of the transfer transistor formed from a surface or periphery of the substrate surface constituting the transfer transistor to a predetermined depth. Exemplary cross-sectional view. 19 shows the region of the photodiode PD, the overflow gate LO, and the storage capacitor CS.

Here, the n-type semiconductor region 51 has a predetermined depth between the n-type semiconductor region 30 and the n + -type semiconductor region 32 from the surface of the substrate surface or the surface circumferential number under the p + semiconductor region of the overflow gate LO. It is formed to overlap. The n-type semiconductor region 51 is an n-type region, which has a lower effective concentration of impurities than the n-type semiconductor region 30 and the n + -type semiconductor region 32.

The above configuration contributes to lowering the potential barrier between the photodiode PD and the storage capacitor CS. This allows the charge that overflows the photodiode PD to smoothly move to the storage capacitor CS during charge storage.

The solid-state imaging device shown in FIGS. 20 and 21 is configured to have a semiconductor layer formed in parallel with a portion below the gate of the overflow gate LO at a predetermined depth of the substrate, and reduce the barrier to store with the photodiode PD. Allow it to penetrate between the capacitors (CS).

20 is an exemplary sectional view of the solid-state imaging device according to the present embodiment, and shows regions of the photodiode PD, the overflow gate LO, and the storage capacitor CS. Here, in the region of the predetermined depth under the gate electrode 50 of the overflow gate LO, the n-type semiconductor region 52 is formed to be connected to the n-type semiconductor region 30.

The above configuration contributes to lowering the barrier so that it can penetrate through the overflow gate LO. A through route in an oblique direction from the n-type semiconductor region 52 to the n + -type semiconductor region 32 constitutes an overflow path from the photodiode PD to the storage capacitor CS, whereby the photodiode PD The charge that overflows through is penetrated so that it can smoothly move to the storage capacitor CS during charge storage.

21 is an exemplary cross-sectional view of the solid-state imaging device according to the present embodiment. As in the case of the solid-state imaging device shown in FIG. 20, in the region of a predetermined depth under the gate electrode 50 of the overflow gate LO, an n-type semiconductor region 53 is formed to form an n-type semiconductor region 30. Connected with. In addition, in this embodiment, the n-type semiconductor region 53 extends below the n + type semiconductor region 32.

The above configuration lowers the barrier and contributes to penetration in the overflow gate LO. The substantially perpendicular through route from the n-type semiconductor region 53 to the n + -type semiconductor region 32 constitutes an overflow path from the photodiode PD to the storage capacitor CS, whereby the photodiode ( The charge that overflows PD) is penetrated so that it can smoothly move to the storage capacitor CS during charge storage.

Fifth Embodiment

In the solid-state imaging device according to the present embodiment, the circuit configuration of the solid-state imaging device according to the first embodiment is modified. 22 is an equivalent circuit diagram of two pixels in the solid-state imaging device according to the present embodiment, and FIG. 23 is a schematic plan view thereof.

The solid-state imaging device according to the present embodiment has a pixel block composed of two pixels, "a" and "b" as a basic unit, each pixel block including two diodes and two storage capacitors. Each pixel block includes photodiodes PDa1 and PDa1 'that receive light and generate and store photocharges; Transmission transistors Ta2 and Tb2 'which are provided adjacent to the photodiodes PDa1 and PDb1', respectively, and transfer photocharges; One floating region FD3, each of which is connected to the photodiodes PDa1 and PDb1 'through the transfer transistors Ta2 and Tb2'; Overflow gates LOa4 and LOb4 ', each provided adjacent to the photodiodes PDa1 and PDb1' and transmitting photocharges that overflow the individual photodiodes PDa1 and PDb1 'during a storage operation; Storage capacitors CSa5 and CSb5 'that store photocharges that overflow photodiodes PDa1 and PDb1', respectively, through respective overflow gates LOa4 and LOb4 'during a storage operation; A reset transistor R6 each connected to the storage capacitors CSa5 and CSb5 'and discharging the signal charges of the storage capacitors CSa5 and CSb5' and the floating region FD3; Storage transistors Sa7 and Sb7 'provided between floating region FD3 and storage capacitors CSa5 and CSb5'; An amplifying transistor SF8 for reading the signal charge of the floating region FD3 or the signal charge of each of the floating region FD3 and the storage capacitors CSa5 and CSb5 'as a voltage; And a selection transistor X9 connected to the amplifying transistor SF8 for selecting the pixel or pixel block. In this manner, the pixel block as the base unit is configured to include two photodiodes, two storage capacitors, a floating region FD, an amplifying transistor SF, a reset transistor R, and a selection transistor X.

In the solid-state imaging device according to the present embodiment, a plurality of pixels having the above-described arrangement are stored in a two-dimensional or one-dimensional array. In each pixel block, the driving lines Ф _LOa , Ф _LOb , Ф _Ta , Ф _Tb , Ф _Sa , Ф _Sb , and Ф _R are respectively overflow gates LOa4 and LOb4 ', transfer transistors Ta2 and Tb2'. ), The storage transistors Sa7 and Sb7 ', and the gate electrode of the reset transistor R6. Further, the pixel select line Ф _X driven by the low shift register is connected to the gate electrode of the select transistor X9. The output line OUT15 is also connected to the output side source of the selection transistor X9 and controlled by the column shift register to generate an output.

As in the case of the first embodiment described above, the configuration of the solid-state imaging device according to the present embodiment can be fixed to an appropriate value such that the voltage of the floating region FD3 can perform the selection operation or the non-selection operation of the pixel. As much as possible, it is not limited. Therefore, the selection transistor X9 and the driving line Ф _X may be omitted.

In the solid-state imaging device according to the present embodiment, the pixels of the pixel block, photodiodes PDa1 and PDb1 'of "a" and "b", overflow gates LOa4 and LOb4', and storage capacitors CSa5 and CSb5 '. The schematic cross sectional view showing the area | region of () is similar to FIG. 8A shown by 1st Embodiment, and abbreviate | omits description in order to avoid duplication. Further, the regions of the photodiodes PDa1 and PDb1 ', the transfer transistors Ta2 and Tb2', the floating regions FD3, the storage transistors Sa7 and Sb7 ', and the storage capacitors CSa5 and CSb5' of the pixel are shown. The schematic sectional drawing of this solid-state imaging device is similar to FIG. 8B shown by 1st Embodiment, Therefore this description is abbreviate | omitted.

Here, an operation method for the solid-state imaging device according to the present embodiment shown in FIGS. 22 and 23 will be described. 24 is a drive timing diagram for the solid-state imaging device according to the present embodiment. In each pixel block, when pixels " a " and " b " are read, reading is performed using the same floating region FD, amplifying transistor SF, reset transistor R, and selection transistor X. do.

First, before the start of storage, the storage transistor Sa of the pixel "a" is set on, and the transfer transistor Ta and reset transistor R are set off. At this time, the photodiode PDa of the pixel "a" is completely depleted. Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CSa of the pixel "a" (time: t ₁ ). Thereafter, the reset noise of (FD + CSa) captured immediately after the reset transistor R is switched off is read into the noise signal N2. Here, the noise signal N2 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component. During the storage period (time: t ₃ ), the photocharges before saturation are stored by the photodiode PDa, and the excess photocharges when the saturation is exceeded are stored in the storage capacitor CSa via the overflow gate LOa. . This operation allows the charge overflowing the photodiode PD to be used efficiently without being discarded. In this way, in all periods before and after saturation, the storage operation is performed by receiving light by the same photodiode PD for each pixel in the same storage period.

After the storage is completed (time: t ₄ ), the selection transistor X is switched on. Thereafter, the reset transistor R is switched on to reset the floating region FD (t: t ₅ ), and the FD reset noise captured immediately after the reset is read out as the noise signal N1. Here, the noise signal N1 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component. Next, the transfer transistor Ta is switched on to completely transmit the optical signal stored in the photodiode PDa to the floating region FD (time: t ₇ ), and the signal is read as (S1 + N1). do. Thereafter, the storage transistor Sa is also switched on (time: t ₈ ) and completely transfers the photocharge stored in the photodiode PDa to the floating region PD and the storage capacitor CSa; Charges of the photodiode PDa, the floating region FD, and the storage capacitor CSa are mixed; The signal is read as (S1 + S2 + N1). Also in the pixel "b", before the start of storage, the storage transistor Sb is set to on, and the transfer transistor Tb and reset transistor R are set to off. Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CSb, and the reset noise of (FD + CSb) captured immediately after the reset transistor R is switched off. Is read into the noise signal N2. Here, the noise signal N2 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component.

During the storage period (time; t ₉ ), the photocharges before saturation are stored by the photodiode PDb, and the excess photocharges when the saturation is exceeded are stored in the storage capacitor CSb via the overflow gate LOb. .

After the storage is completed (time; t ₁₀ ), the select transistor X is switched on. Thereafter, the reset transistor R is switched on to reset the floating region FD (t: t ₁₁ ), and the FD reset noise captured immediately after the reset is read out as the noise signal N1 (time: t ₁₂ ).

Next, the transfer transistor Tb is switched on to transmit the optical signal stored in the photodiode PDb to the floating region FD (time: t ₁₃ ), and the signal is read out as (S1 + N1). . Thereafter, the storage transistor Sb is turned on (time: t ₁₄ ) and completely transfers the photocharge stored in the photodiode PDb to the floating region FD and the storage capacitor CSb. Charges stored in the photodiode PDb, the floating region FD, and the storage capacitor CSb are mixed, and the signal is read as (S1 + S2 + N2).

In the solid-state imaging device according to the present embodiment, since the floating region FD, the amplifying transistor SF, the reset transistor R, and the selection transistor X are provided at a ratio of one group per two pixels, pixels per pixel The area can be reduced.

The block diagram of the solid-state imaging device according to the present embodiment is the same as that of Fig. 10 shown in the first embodiment except for the output line provided at one ratio per two pixels. The design of the signal read out sequentially from each pixel in the present embodiment, the expansion ratio of the operating range, and the wide operating range signal are the same as those described in the first embodiment.

In the above operation, the case where the pixels provided to the pixel blocks are sequentially driven and signals obtained from all the pixels are used will be described. However, as a thinning-out operation, a signal obtained from a pixel selected by selecting an arbitrary pixel from the pixel block may be used. Alternatively, as an average operation, pixel signals of the pixel block may be mixed and added to use the signal.

As in the case of the first embodiment, the solid-state imaging device according to the present embodiment increases the sensitivity at high brightness without reducing the sensitivity at low brightness to achieve a wide area, and also exceeds the area usually used. The supply voltage will not be used. This enables the present solid-state imaging device to be miniaturized in the future image sensor. In addition, since the addition of the component is reduced to a minimum, there is no possibility of causing an increase in the pixel size.

Also, unlike conventional image sensors that realize a wide operating range, the storage cycle is not divided between the high luminance side and the low luminance side, that is, without straddling the frame, the present embodiment stores the same Store the photocharge in the cycle. This prevents the deterioration of image quality even in the imaging of moving images.

In addition, in the image sensor according to the present embodiment, in consideration of the leakage current from the floating region FD, the minimum signal of (S1 + S2) becomes the electric charge saturated from the photodiode PD, and the image sensor is the floating region. The charge amount larger than the charge amount of the leakage current from (FD) can be handled. This provides the advantage of manufacturing image sensors that are insensitive to FD leakage.

Sixth Embodiment

The solid-state imaging device according to the present embodiment is a modification of the circuit configuration of the solid-state imaging device according to the first embodiment. 25 is an equivalent circuit diagram of four pixels in the solid-state imaging device according to the present embodiment, and FIG. 26 is a schematic plan view thereof.

The solid-state imaging device according to this embodiment has a pixel block composed of four pixels "a", "b", "c", and "d" as a basic unit. Each pixel block includes photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'" that receive light and generate and store photocharges; Transfer transistors Ta2, Tb2 ', Tc2 ", and Td2'", which are provided adjacent to the photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'", respectively, and transfer photocharges; One floating region FD3 connected to the photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'" through transfer transistors Ta2, Tb2 ', Tc2 ", and Td2'", respectively; Transmit photocharges that overflow individual photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'" during the storage operation, and are adjacent to the photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'". Provided overflow gates (LOa4, LOb4 ', LOc4 ", and LOd4'"); To store photocharges that overflow the photodiodes PDa1, Pdb1 ', PDc1 ", and PDd1'" through respective overflow gates LOa4, LOb4 ', LOc4 ", and LOd4'" during the storage operation. Storage capacitors CSa5, CSb5 ', CSc5 ", and CSd5'"; It is connected to the respective storage capacitors CSa5, CSb5 ', CSc5 ", and CSd5'", and discharges the signal charges of the storage capacitors CSa5, CSb5 ', CSc5 ", and CSd5'" and the floating region FD3. Reset transistor R6; Storage transistors Sa7, Sb7 ', Sc7 ", and Sd7" provided between floating region FD3 and storage capacitors CSa5, CSb5', CSc5 ", and CSd5 '"; An amplifying transistor for reading the signal charge of the floating region FD3 or each of the signal charges of the floating region FD3 and the storage capacitors CSa5, CSb5 ', CSc5 ", and CSd5'" as a voltage; And a selection transistor X9 connected to the amplifying transistor SF8 and selecting a pixel or a pixel block. In this manner, the pixel block as the base unit is configured to include four photodiodes, four storage capacitors, floating region FD, amplifying transistor SF, reset transistor R, and selection transistor X.

In the solid-state imaging device according to the present embodiment, a plurality of pixels having the above-described arrangement are stored in a two-dimensional or one-dimensional array. In each pixel block, the driving lines Ф _LOa , Ф _LOb , Ф _LOc , Ф _LOd , Ф _Ta , Ф _Tb , Ф _Tc , Ф _Td , Ф _Sa , Ф _Sb , Ф _Sc , Ф _Sd , and Ф _R ) Overflow gates (LOa4, LOb4 ', LOc4 ", and LOd4'"), transfer transistors Ta2, Tb2 ', Tc2 ", and Td2'", storage transistors Sa7, Sb7 ', Sc7 ", and Sd7', respectively. ") And the gate electrode of reset transistor R6. Further, the pixel select line Ф _X driven by the low shift register is connected to the gate electrode of the select transistor X9. The output line OUT15 is also connected to the output side source of the selection transistor X9 and controlled by the column shift register to generate an output.

As in the case of the first embodiment described above, the configuration of the solid-state imaging device according to the present embodiment can be fixed to an appropriate value such that the voltage of the floating region FD3 can perform the selection operation or the non-selection operation of the pixel. As much as possible, it is not limited. Therefore, the selection transistor X9 and the driving line Ф _X may be omitted.

In the solid-state imaging device according to the present embodiment, the photodiodes PDa1, Pdb1 ', PDc1, and PDd1' "in the pixels" a "and" b "of the pixel block, overflow gates LOa4, LOb4 ', and LOc4. &Quot; and LOd4 '", and storage capacitors CSa5, CSb5', CSc5 ", and CSd5 '" are similar to FIG. 8A shown in the first embodiment, and therefore, description thereof is omitted to avoid duplication. Further, the photodiodes PDa1, PDb1 ', PDc1', and PDd1 '"of the pixel, the transfer transistors Ta2, Tb2', Tc2", Td2 '", the floating region FD3, and the storage transistors Sa7, Sb7' , Sc7 ", and Sd7 '") and the schematic sectional drawing of this solid-state imaging device corresponding to the area | region of the storage capacitors CSa5, CSb5', CSc5 ", and CSd5 '" are shown with FIG. 8B shown by 1st Embodiment. Similar, and therefore, the description is omitted.

Here, an operation method for the solid-state imaging device according to the present embodiment shown in FIGS. 25 and 26 will be described. 27 is a drive timing diagram for the solid-state imaging device according to the present embodiment. In each pixel block, when pixels "a ", " b ", " c ", and " d " are read out, the readout is the same floating region FD, amplifying transistor SF, reset transistor R, and This is done by using the select transistor X.

First, before the start of storage, the storage transistor Sa of the pixel "a" is set on, and the transfer transistor Ta and the reset transistor R are set off. At this time, the photodiode PDa of the pixel "a" is in a completely depleted state.

Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CSa of the pixel "a" (time: t ₁ ). At this time, the reset noise of (FD + CSa) captured immediately after the reset transistor R is switched off is read out by the noise signal N2 (time: t ₂ ). Here, the noise signal N2 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component.

During the storage period (time: t ₃ ), the photoelectric charge before saturation is stored by the photodiode PDa and the excess photoelectricity when the saturation is exceeded is stored in the storage capacitor CSa via the overflow gate LOa do. This operation allows the charge overflowing the photodiode PD to be used efficiently without being discarded. In this manner, the storage operation in all periods before and after saturation is performed by receiving light by the same photodiode PD for each pixel in the same storage period.

After the storage is completed (time: t ₄ ), the select transistor X is switched on. Thereafter, the reset transistor R is switched on to reset the diffusion region FD (t: t _s ), and the FD reset noise captured immediately after the reset is read out as the noise signal N1 (time: t ₆ ). Here, the noise signal N1 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component.

Next, the transfer transistor Ta is turned on to completely transmit the optical signal stored in the photodiode PDa to the floating region FD (time: t ₇ ), and the signal is read out as (S1 + N1). Thereafter, the storage transistor Sa is switched on (time: t ₈ ) to completely transfer the photocharges stored in the photodiode PDa to the floating region FD and the storage capacitor CSa; The charges of the photodiode PDa, floating region FD, and storage capacitor CSa are mixed; The signal is read as (S1 + S2 + N2). Also in the pixel "b", before the start of storage, the storage transistor Sb is set on, and the transfer transistor Tb and reset transistor R are set off. Next, the reset transistor R is switched on to reset the floating region FD and the storage capacitor CSb, and the reset noise of (FD + CSb) captured immediately after the reset transistor R is switched off. Is read into the noise signal N2. Here, the noise signal N2 includes a change in the threshold voltage of the amplifying transistor SF as a fixed pattern noise component.

During the storage period (time: t ₉ ), photocharges before saturation are stored in the photodiode PDb, and excess photocharges when saturation is exceeded are stored in the storage capacitor CSb via the overflow gate LOb. After the storage is completed (time: t ₁₀ ), the selection transistor X is switched on. At this time, the reset transistor R is switched on to reset the floating region FD (t: t ₁₁ ), and the FD reset noise that is captured immediately after the reset is read out as the noise signal N1 (time: t ₁₂ ). Next, the transfer transistor Tb is turned on to completely transmit the optical signal stored in the photodiode PDb to the floating region FD (time: t ₁₃ ), and the signal is read out as (S1 + N1). At this time, the storage transistor Sb is also turned on (time: t ₁₄ ) to completely transfer the photocharges stored in the photodiode PDb to the floating region FD and the storage capacitor CSb. Charges stored in the photodiode PDb, the floating region FD, and the storage capacitor CSb are mixed, and the signal is read as (S1 + S2 + N2). In the following, the same operation is repeated for the pixels "c" and "d".

In the solid-state imaging device according to the present embodiment, since the floating region FD, the amplifying transistor SF, the reset transistor R, and the selection transistor X are provided at a ratio of one group per four pixels, per pixel The pixel area can be reduced.

In the above operation, the case where the pixels provided to the pixel blocks are sequentially driven and signals from all the pixels are used will be described. However, as a rare operation, a signal obtained from the selected pixel may be used by selecting an arbitrary pixel from the pixel block. Alternatively, as an average operation, the pixel signals of the pixel block may be mixed and added to use the signals.

The block diagram of the solid-state imaging device according to the present embodiment is the same as that in Fig. 10 shown in the first embodiment except that the output lines are provided at one ratio per four pixels. In this embodiment, the synthesis of the signal read out sequentially from each pixel, the expansion ratio of the operating range, and the wide operating range signal are the same as described in the first embodiment.

According to the case of the first embodiment, the solid-state imaging device according to the present embodiment increases the sensitivity at the high luminance without reducing the sensitivity at the low luminance side to achieve a wide area, and the power supply voltage exceeding the region normally used. Do not use This allows the solid-state imaging device to address the minimization of future image sensors. In addition, since the addition of elements is reduced and minimized, there is no possibility of causing an increase in the pixel size.

Also, unlike conventional image sensors that realize a wide operating range, the storage cycle is not divided between the high luminance side and the low luminance side, that is, without straddling the frame, the present embodiment stores the same Store the photocharge in the cycle. This prevents the deterioration of image quality even in the imaging of moving images.

In addition, in the image sensor according to the present embodiment, in consideration of the leakage current from the floating region FD, the minimum signal of (S1 + S2) becomes the electric charge saturated from the photodiode PD, and the image sensor is the floating region. The amount of charge greater than the leakage current from (FD) can be handled. This provides the advantage of manufacturing image sensors that are insensitive to FD leakage.

Seventh Embodiment

The solid-state imaging device according to the present embodiment is an example in which the storage capacitor for storing the photocharges overflowing the photodiode in the first to sixth embodiments described above is modified.

When attempting to use a junction storage capacitor as a storage capacitor, possible electrostatic capacitors per square μm are on the order of 3 to 3 fF / μm ² , under consideration of conditions, ie the efficiency of the area is not so great and thus the operating range is It is difficult to widen.

On the other hand, in the case of planar storage capacitors, when the insulation film electric field is set to 3 to 4 MV / cm or less, the maximum applied voltage is set to 2.5 to 3 V, and the thickness of the capacitor insulation film is the insulation of the capacitor insulation film. In order to suppress the film leakage current, it is set to about 7 nm, the electrostatic capacitance is 4.8 fF / μm ² for the relative dielectric constant ε _r = 3.9, and the electrostatic capacitance is 9.9 fF / μm ² for the ε _r = 7.9, The capacitance becomes 25 fF / μm ² for ε _r = 20 and the electrostatic capacitance becomes 63 fF / μm ² for ε _r = 50.

In addition to silicon oxide (ε _r : 3.9), silicon nitride (ε _r : 7.9), Ta ₂ O ₅ (ε _r : about 20 to 30), HfO ₂ The use of so-called high k materials, such as (ε _r : about 30), ZrO ₂ (ε _r : about 30), and La ₂ O ₃ (ε _r : about 40-50), allows greater electrostatic capacitance to be realized. In this way, even in the case of planar storage capacitors having a relatively simple structure, an image sensor having an operating range as wide as 100 to 200 dB can be realized.

In addition, the application of the structure, which has the ability to expand the area contributed by the capacitor to suppress the occupied area, such as the stack type or the trench type, allows the operating range as wide as 120 dB to be achieved and the high k material described above. By using, the operating ranges as much as 140 dB and 160 dB can be obtained by stack type and trench type, respectively.

In the following, an example of a storage capacitor to which the present embodiment can be applied is shown. Fig. 28 is a sectional view of a planar MOS storage capacitor similar to that in the first embodiment. For example, this storage capacitor CS serves as a lower electrode and is formed on the surface layer of the p-type well formed on the substrate 20; a capacitor insulating film 42 made of silicon oxide, formed on the n + type semiconductor region 60; And an upper electrode 43 made of polysilicon or the like, which is formed on the capacitor insulating film 42.

29 is a sectional view illustrating the planar MOS and the junction storage capacitor. For example, this storage capacitor functions as a lower electrode, and the n + type semiconductor region 61 formed in the surface layer of the p type well formed on the n type semiconductor substrate 20 serves as the source / drain of the storage transistor. Integrally formed with the n + type semiconductor region 32; The upper electrode 43 is configured to be formed through the capacitor insulating film 42 made of silicon oxide, which is provided in the n + type semiconductor region 61. Here, the power supply voltage VDD or ground GND is applied to the upper electrode 43.

The storage capacitor shown in FIG. 30 (sectional view) is a planar MOS storage capacitor similar to that shown in FIG. However, in this storage capacitor, the capacitor insulating film 42a is made of a high k material such as silicon nitride or Ta ₂ O ₅ , unlike in FIG. 28, and the capacitance is made larger than in FIG. 28.

The storage capacitor shown in FIG. 31 (sectional view) is a planar MOS and junction storage capacitor similar to that shown in FIG. However, in this storage capacitor, the capacitor insulating film 42a is made of a high k material such as silicon nitride or Ta ₂ O ₅ , unlike in FIG. 29, and the capacitance is made larger than in FIG. 29.

32 is a cross-sectional view illustrating a stack storage capacitor. For example, the storage capacitor CS includes a lower electrode 63 formed on the element isolation insulating film 62 provided on the n-type semiconductor substrate 20; A capacitor insulating film 64 formed on the lower electrode 63; And an upper electrode 65 formed on the capacitor insulating film 64. Here, the n + type semiconductor region 32 serving as the source / drain of the storage transistor, and the lower electrode 63 are connected by the wiring 45. In this case, the power supply voltage VDD or ground GND is applied to the upper electrode 65.

33 is a sectional view illustrating the stack storage capacitor. For example, this storage capacitor CS includes a lower electrode 67 formed to be connected to an n + type semiconductor region 32 functioning as a source / drain of a storage transistor; A capacitor insulating film 68 formed on the inner wall of the lower electrode 67; And an upper electrode 69 formed through the capacitor insulating film 68 to be embedded inside the lower electrode 67. Here, a power supply voltage VDD or ground GND is applied to the upper electrode 69. The structure of the lower electrode 67 and the upper electrode 69 formed to be embedded inside the lower electrode 67 can be larger than the conventional stack type in the surface area contributing to the electrostatic capacitance.

34 is a sectional view illustrating a synthetic storage capacitor obtained by combining the planar type and the stack type. According to this example, larger capacitances with high area efficiency can be formed.

35 is a sectional view illustrating the trench storage capacitor. The storage capacitor CS includes a trench TC formed to be cut through the p-type well 21 on the n-type semiconductor substrate 20 to reach the n-type semiconductor substrate 20; An n + type semiconductor region 70 which functions as a bottom electrode and is formed on the inner wall of the trench TC; A capacitor insulating film 71 formed to coat the inner wall of the TC; And an upper electrode 71 formed to be embedded in the trench TC through the capacitor insulating film 71. Here, the n + type semiconductor region 32 serving as the source / drain of the storage transistor, and the upper electrode 72 are connected by the wiring 45.

36 is a sectional view illustrating the trench storage capacitor with a junction. This storage capacitor CS has a trench TC formed in the p-type well 21 on the n-type semiconductor substrate 20; In the inner wall of the trench TC, an n + type semiconductor region 73 serving as a lower electrode is formed integrally with the n + type semiconductor region 32 serving as a source / drain of the storage transistor; A capacitor insulating film 74 is formed to coat the inner wall of the TC; The upper electrode 75 is configured to be formed to be embedded in the trench TC through the capacitor insulating film 74.

37 is a sectional view illustrating the trench storage capacitor. The storage capacitor CS includes a trench TC formed to be cut through the p-type well 21 on the n-type semiconductor substrate 20 to reach the n-type semiconductor substrate 20; An n + type semiconductor region 76 serving as the bottom electrode and formed on the inner wall of the trench TC in a region deeper than the depth measurement of the trench TC; A capacitor insulating film 77 formed to coat the inner wall of the TC; And an upper electrode 78 formed to be embedded in the trench TC through the capacitor insulating film 77. Here, the n + type semiconductor region 32 serving as the source / drain of the storage transistor, and the upper electrode 78 are connected by the wiring 45.

38 is a sectional view illustrating the trench storage capacitor. The storage capacitor CS includes a trench TC formed to be cut through the p-type well 21 on the n-type semiconductor substrate 20 to reach the n-type semiconductor substrate 20; A p + type semiconductor region 79 that functions as a bottom electrode and is formed on the inner wall of the trench TC; A capacitor insulating film 80 formed to coat the inner wall of the TC; And an upper electrode 81 formed to be embedded in the trench TC through the capacitor insulating film 80. Here, the n + type semiconductor region 32 serving as the source / drain of the storage transistor, and the upper electrode 81 are connected by the wiring 45.

39 is a cross-sectional view illustrating a CMOS sensor using a junction capacitor having an embedded storage capacitor. For example, the p-type laminated layer 91 is formed on the p-type silicon semiconductor (p-sub; 90), and the n + type semiconductor region 92 is the p-type silicon semiconductor 90 and the p-type laminated layer 91 Is formed across). That is, an n-type (first conductivity type) semiconductor region and a p-type (second conductivity type) semiconductor region bonded together are embedded in a semiconductor substrate constituting the solid-state imaging device, and a storage capacitor built in using a junction capacitor is used. Form. In addition, the p + type isolation region 93 is formed in the p-type silicon semiconductor (p-sub) 90 and the p-type laminated layer 91. The p-type silicon semiconductor layer 94 is formed on the p-type laminated layer 91. As in the case of the above-described embodiment, for the p-type silicon semiconductor layer 94, the photodiode PD, the overflow gate LO, the transfer transistor T, the floating region FD, and the storage transistor S ) Is provided. For example, an n + type semiconductor region 92 functioning as a storage capacitor SC is formed, for example, the above-described photodiode PD, overflow gate LO, transfer transistor T, floating region. (FD), and storage transistor (S) is formed extensively. In addition, the n + type semiconductor region 32 is connected to the n + type semiconductor region 92 constituting the storage capacitor by the n + type semiconductor region 95 extending vertically from the p type semiconductor layer 94.

40 is a cross-sectional view illustrating a CMOS sensor with an embedded storage capacitor using an insulating film capacitor and a junction capacitor. This sensor has a structure similar to that of FIG. However, in this sensor, the first p-type laminated layer 91a and the second p-type laminated layer 91b are formed in the p-type silicon semiconductor layer 90 (p-sub) through the insulating film 90a, and thus Thereby forming a semiconductor on insulator (SOI) substrate such that the semiconductor layer is formed on the semiconductor substrate through the insulating film. Here, the n + type semiconductor region 92 is formed across the first p-type laminated layer 91a and the second p-type laminated layer 91b to the region bordered by the insulating film 90a, and the storage capacitor is It is formed using an insulating capacitor between the semiconductor substrate and the semiconductor layer facing each other with an insulating film. In addition, as in the case of the storage capacitor of FIG. 39, a junction capacitor is formed between the first p-type stacked layer 91a and the second p-type stacked layer 91b. The other structure is the same as in the CMOS sensor shown in FIG.

FIG. 41 is a cross-sectional view illustrating a CMOS sensor using an insulating film capacitor and a junction capacitor with embedded storage capacitors. FIG. This sensor has a structure similar to that in FIG. However, in this sensor, a low concentration semiconductor layer (i layer) 96 is formed between the n-type semiconductor region 30 constituting the photodiode PD and the n + type semiconductor region 92 constituting the storage capacitor. This structure contributes to lowering the potential barrier between the n-type semiconductor region 30 and the n + -type semiconductor region 92, which constitutes an overflow path from the photodiode PD to the storage capacitor CS. This allows charges that overflow the photodiode PD to penetrate and thereby smoothly transfer charges to the storage capacitor CS during charge storage.

The foregoing various storage capacitors are applicable to any one of the first to seventh embodiments described above. As described above, by storing photocharges overflowing the photodiode using any one of the storage capacitors having this shape, an extension of the operating range can be achieved on the high luminance side.

Example  One

In the solid-state imaging device according to the present invention, the solid-state imaging device element is manufactured by the method of manufacturing a semiconductor having two polysilicon layers and three metal wiring layers. Here, the solid-state imaging device elements are arranged in two dimensions on the condition of the number of pixels: 640 (rows) x 480 (columns), a pixel size of 7.5 µm squares, floating area capacitance C _FD = 4fF, and storage capacitance C _CS = 60 fF. Has a pixel. Each storage capacitor is constituted by a parallel capacitor, that is, a polysilicon-silicon oxide film-silicon capacitor, and a polysilicon-silicon nitride film-polysilicon capacitor. The saturation voltages for signals S1 and S1 + S2 are 500 mV and 1000 mV, respectively. The residual noise voltage remaining in S1 and (S1 + S2) after noise removal is equal to the value of 0.09 mV. The switching voltage from S1 to (S1 + S2) is set at 400 mV, which is lower than the saturation voltage for signal S1.

The S / N ratio of signal S1 + S2 to residual noise at each switching point is greater than 40 dB, whereby a solid-state imaging device with high image quality can be realized. An operating range of 100 dB is obtained. In addition, during irradiation with high brightness light, excess photocharge that overflows the photodiode PD is efficiently transferred by the overflow gate LO to the storage capacitor, resulting in enhanced high and damaged resistances. May allow leakage of excess photocharge to adjacent pixels to be suppressed.

In this Embodiment 1, the extension of the operating range can be achieved on the high luminance side while maintaining a high S / N ratio.

Example  2

In the solid-state imaging device according to the present invention, the solid-state imaging device is manufactured by arranging pixel blocks in a two-dimensional array (number of pixels: 640 (rows) x 240 (columns)). Here, each pixel block is constructed by arranging photodiodes and storage capacitors in 2x2 in a basic pixelblock having a size of 7 mu m (length) x 3.5 mu m (width). The effective number of pixels is 640 (rows) x 240 (columns). In each pixel block, the floating region capacitance C _FD is set to 3.4 fF, and the storage capacitance C _CS is set to 100 fF by applying the trench storage capacitor structure. The saturation voltages for signals S1 and S1 + S2 are 500 mV and 1000 mV, respectively. The residual noise voltage remaining in S1 and (S1 + S2) after noise removal is equal to a value of 0.09 mV. The switching voltage from S1 to (S1 + S2) is set to 400 mV, which is lower than the saturation voltage for signal S1.

The ratio (S / N) of signal (S1 + S2) to residual noise at each switching point is higher than 40 dB, whereby a solid-state imaging device with high image quality can be realized. An operating range of 110 dB is obtained. In addition, while irradiating with light of high brightness, excess photocharge that overflows the photodiode PD is efficiently transferred by the overflow gate LO to the storage capacitor, thereby providing an enhanced blowing resistance and a damaged resistance. It is possible to suppress leakage of the excess photocharges into adjacent pixels, which causes them.

In this embodiment 2, the extension of the operating range can be achieved on the high luminance side while maintaining a high S / N ratio.

It will be understood that the present invention is not limited to the above-described embodiment. For example, the present invention is applied to an optical sensor that can be obtained by individually configuring the pixels of each solid-state imaging device, or to a line sensor in which the pixels of each solid-state imaging device are linearly arranged, so that a wide operating range and high S / N is newly obtainable and is not limited to the application to the solid-state imaging device in this embodiment.

In addition, the form of a resistance capacitor etc. is not specifically limited. To increase the capacitance of memory storage capacitors, such as DRAM (dynamic random access memory), various methods developed so far may be used. The configuration of the solid-state imaging device according to the present invention is not limited as long as the photodiode and the storage capacitor storing the photocharges overflowing the photodiode are connected through the overflow gate. The solid-state imaging device according to the present invention is also applicable to CCDs in addition to CMOS image sensors. In addition, various changes and modifications may be made in the present invention without departing from the spirit and scope thereof.

The solid-state imaging device according to the present invention is used in digital cameras, camera phones, monitor cameras, built-in cameras, scanners, and the like, and can be applied to image sensors requiring a wide operating range.

The operation method for the solid-state imaging device according to the present invention can be applied to that for an image sensor requiring a wide operating range.

The solid-state imaging device according to the present embodiment can increase the sensitivity on the high luminance side without reducing the sensitivity on the low luminance side, thereby achieving a wide range, and in addition, supplying power in excess of the range generally used. Do not use voltage. This enables the present solid-state imaging device to achieve miniaturization of future image sensors. In addition, since the addition of components is reduced to a minimum, there is no possibility of causing an increased pixel size.

Also, unlike conventional image sensors that implement a wide operating range, the storage cycle is not divided between the high luminance side and the low luminance side, i.e., without straddling the frame, the present embodiment provides the same storage. Store the photocharge in the cycle. This prevents the deterioration of image quality even in the imaging of moving images.

Regarding the leakage current from the floating region, in the image sensor according to the present embodiment, the minimum signal of (S1 + S2) becomes the saturated charge from the photodiode, and the image sensor is the amount of charge of the leakage current from the floating region. To deal with larger amounts of charge. This provides an advantage in fabricating an image sensor that is not damaged by FD leakage.

Claims (33)

A solid-state imaging device comprising a plurality of pixels arranged in an array, Each of the pixels, Photodiodes that receive light and generate photocharges; A transfer transistor for transferring the photocharge to a floating region; Storage capacitor elements; And A storage transistor provided between said floating region and said storage capacitor element, One floating area is provided in common for each of the pixels or one for the plurality of pixels; Each of the pixels further comprises an overflow gate coupled between the photodiode and the storage capacitor element, And a photocharge that overflows the photodiode during the storage period is transferred from the photodiode to the storage capacitor element through the overflow gate. The method of claim 1, The overflow gate (LO in FIGS. 6, 8A, 11, 22, 25, and 28-41) is gated on a gate insulating film (35 in FIGS. 8A, and 28-41). The solid-state imaging device comprised of the transistor provided with the electrode (FIG. 8A and 36 in FIGS. 28-41). The method of claim 2, And the threshold voltage of the overflow gate is set to a value lower than the threshold voltage of the transfer transistor. The method of claim 2, The threshold voltage of the overflow gate and the threshold voltage of the transfer transistor are the same, and the potential of the gate electrode of the overflow gate is set to a value higher than zero potential. The method of claim 1, And said overflow gate (LO in FIGS. 14, 16, 18, 19, 20, and 21) is composed of a junction transistor. 6. The method of claim 5, The semiconductor region (50 in FIGS. 18, 19, 20, and 21 to 50) forming the gate of the junction transistor is formed on the surface semiconductor region (31, 21, 20, and 21 to 21) of the photodiode. Connected, and the semiconductor region and the surface semiconductor region are grounded (see FIGS. 14 and 16). The method of claim 6, The photodiode (PD in FIGS. 19-21) comprises the surface semiconductor region (31 in FIGS. 19-21) and the opposing conductive region (30 in FIGS. 19-21), Another opposing conductive type region (51 in Figs. 19, 52 in Figs. 20, and 53 in Figs. 21) is provided under the semiconductor region (50 in Figs. 19, 20 and 21). The method of claim 1, The storage capacitor device, A semiconductor region functioning as a lower electrode, formed in the semiconductor layer in which the photodiode is formed; A capacitor insulating film formed on the semiconductor layer; And And an upper electrode formed on the capacitor insulating film. The method of claim 1, The storage capacitor device, A lower electrode formed on a substrate on which the photodiode is formed; A capacitor insulating film formed on the lower electrode; And And an upper electrode formed on the capacitor insulating film. The method of claim 1, The storage capacitor device, A semiconductor region functioning as a lower electrode formed in an inner wall of a trench formed in a semiconductor layer in which the photodiode is formed; A capacitor insulating film formed on the inner wall of the trench; And And an upper electrode formed on the capacitor insulating film and embedding the trench. The method of claim 1, The floating regions are provided one for each one of the pixels; Each of the pixels further comprises an amplifying transistor for reading a signal from the charges in the floating region. The method of claim 1, One floating region is provided in common with respect to the plurality of pixels; And said solid-state imaging device further comprises an amplifying transistor for reading a signal from charges in said floating region. 13. The method according to claim 11 or 12, Photoelectricity in the photodiode is transmitted through the transfer transistor to the floating region, the amplifying transistor reads a voltage signal from the photocharge in the floating region while the storage transistor is turned off, Thereafter, the storage transistor is turned on to mix photocharges in the floating region with photocharges stored in the storage capacitor element, and the amplifying transistor reads a voltage signal from the mixed photocharges. . The method of claim 1, And each of the pixels further comprises a reset transistor connected to a connection between the storage capacitor element and the storage transistor to discharge photocharges from the floating region and from the storage capacitor element. The method of claim 1, And a reset transistor coupled to said floating region to discharge photocharges from said floating region and from said storage capacitor element. 13. The method of claim 12, And the plurality of pixels in common comprises a reset transistor connected to the floating region to discharge photocharges from the floating region and from the storage capacitor element. The method of claim 11, And a selection transistor coupled to the amplifying transistor. The method of claim 1, And wherein the overflow gate is comprised of a MOS transistor coupled between the photodiode and the storage capacitor, the gate electrode of the MOS transistor receiving a signal for determining the storage operation. The method of claim 1, A voltage signal obtained from photofloating charge transmitted to both the floating region or both the floating region and the storage capacitor element; And Voltage signal at a reset level in the floating region or both the floating region and the storage capacitor element. The solid-state imaging device further including a noise removal unit which takes the difference between. 20. The method of claim 19, And a storage unit for storing the voltage signal at the reset level. A solid-state imaging device comprising a plurality of pixels, Each of the two or more pixels have a floating gate in common, Each pixel of the plurality of pixels, A photodiode for receiving light and generating and storing photocharges; A transfer transistor connected between the photodiode and the floating region and transferring photocharges stored in the photodiode to the floating region; Storage capacitor elements; A storage transistor provided separately from said transfer transistor between said floating region and said storage capacitor element; And An overflow gate provided between the photodiode and the storage capacitor element and the connection of the storage transistor, separately from the transfer transistor and also separately from the storage transistor, In the storage period of the photodiode, the overflow gate transfers photocharge that overflows from the photodiode to the storage capacitor element without penetrating the floating region and causes the storage capacitor element to overflow. A solid-state imaging device, which makes it possible to store photocharges. A solid-state imaging device comprising a plurality of pixels, Each pixel of the plurality of pixels, Floating gate; A photodiode for receiving light and generating and storing photo charges; A transfer transistor connected between the photodiode and the floating region and transferring the photocharge stored in the photodiode to the floating region; Storage capacitor elements; A storage transistor provided separately from said transfer transistor between said floating region and said storage capacitor element; And An overflow gate provided between the photodiode and the storage capacitor element and the connection of the storage transistor, separately from the transfer transistor and also separately from the storage transistor, In the storage period of the photodiode, the overflow gate transfers photocharge that overflows from the photodiode to the storage capacitor element without penetrating the floating region and causes the storage capacitor element to overflow. A solid-state imaging device, which makes it possible to store photocharges. The method of claim 21 or 22, During the transfer period following the storage period of the photodiode, the transfer transistor is turned on to transfer charge stored in the photodiode to the floating region to enable the floating region to store the charges, During the mixing period after the transfer period, the storage transistor is turned on to mix the charge stored in the storage capacitor element with the charge stored in the floating region, The charge stored in the floating region is read before the mixing period, and the mixed charge is read after the mixing period. 24. The method of claim 23, The solid-state imaging device further includes an amplifying transistor connected to the floating region, When the storage transistor is turned off, the amplifying transistor amplifies the charge stored in the floating region and converts it into a voltage signal. And when the storage transistor is turned on, the amplifying transistor amplifies and converts the mixed charge. 25. The method of claim 24, The solid-state imaging device further includes a reset transistor, When the storage transistor is turned off, the reset transistor discharges charge from the floating region, And when the storage transistor is turned on, the reset transistor discharges electric charges from the floating region and the storage capacitor element. 26. The method of claim 25, When the storage transistor is turned off, the floating region is discharged and noise charge is read from the floating region, And when the storage transistor is turned on, the floating region and the storage capacitor element are discharged, and noise charge is read from the floating region and the storage capacitor element. A photodiode for receiving light and generating and storing photocharges; A transfer transistor for transmitting the photocharges; A floating region in which the photocharge is transferred through the transfer transistor; Storage capacitor elements; A storage transistor coupled between the floating region and the storage capacitor element; And An overflow gate connected between the photodiode and a connection, the connection including the overflow gate, between the storage capacitor element and the storage transistor, The overflow gate transfers overflowing photocharges from the photodiode to the storage capacitor element during the storage period of the photodiode, enabling the storage capacitor element to store the overflowing photocharge, The transfer transistor is turned on to transfer charge stored in the photodiode to the floating region during the transfer period following the storage period of the photodiode, thereby allowing the floating region to store the charge, The storage transistor is turned on to mix the charge stored in the storage capacitor element with the charge stored in the floating region during the mixing period after the transfer period, The charge stored in the floating region is read before the mixing period, and the mixed charge is read after the mixing period, And the overflow gate is configured to lower the potential barrier between the photodiode and the storage capacitor element. A photodiode for receiving light and generating and storing photocharges; A transfer transistor for transmitting the photocharges; A floating region in which the photocharge is transferred through the transfer transistor; Storage capacitor elements; A storage transistor coupled between the floating region and the storage capacitor element; And An overflow gate connected between the photodiode and a connection, the connection including the overflow gate, between the storage capacitor element and the storage transistor, The overflow gate transfers overflowing photocharges from the photodiode to the storage capacitor element during the storage period of the photodiode, enabling the storage capacitor element to store the overflowing photocharge, The transfer transistor is turned on to transfer charge stored in the photodiode to the floating region during the transfer period following the storage period of the photodiode, thereby allowing the floating region to store the charge, The storage transistor is turned on to mix the charge stored in the storage capacitor element with the charge stored in the floating region during the mixing period after the transfer period, The charge stored in the floating region is read before the mixing period, and the mixed charge is read after the mixing period, The overflow gate is composed of a field effect transistor, And the threshold voltage of the field effect transistor is set to a value lower than the threshold voltage of the transfer transistor. A photodiode for receiving light and generating and storing photocharges; A transfer transistor for transmitting the photocharges; A floating region in which the photocharge is transferred through the transfer transistor; Storage capacitor elements; A storage transistor coupled between the floating region and the storage capacitor element; And An overflow gate connected between the photodiode and a connection, the connection including the overflow gate, between the storage capacitor element and the storage transistor, The overflow gate transfers overflowing photocharges from the photodiode to the storage capacitor element during the storage period of the photodiode, enabling the storage capacitor element to store the overflowing photocharge, The transfer transistor is turned on to transfer charge stored in the photodiode to the floating region during the transfer period following the storage period of the photodiode, thereby allowing the floating region to store the charge, The storage transistor is turned on to mix the charge stored in the storage capacitor element with the charge stored in the floating region during the mixing period after the transfer period, The charge stored in the floating region is read before the mixing period, and the mixed charge is read after the mixing period, The overflow gate is composed of a field effect transistor, The threshold voltage of the field effect transistor is set to the same value as the threshold voltage of the transfer transistor, And the gate voltage of the field effect transistor is set to a value different from the gate voltage of the transfer transistor. 30. The method according to any one of claims 27 to 29, The solid-state imaging device further includes an amplifying transistor connected to the floating region, When the storage transistor is turned off, the amplifying transistor amplifies the charge and converts it into a voltage signal, the charge is stored in the photodiode and then transferred to the floating region, And when the storage transistor is turned on, the amplifying transistor amplifies the mixed charge and converts it into a voltage signal. 30. The method according to any one of claims 27 to 29, The solid-state imaging device includes a plurality of pixels arranged in an array of one or two dimensions, Wherein each pixel of said plurality of pixels comprises at least said photodiode, said transfer transistor, said storage capacitor element, said storage transistor and said overflow gate. 30. The method according to any one of claims 27 to 29, The solid-state imaging device further includes a reset transistor, When the storage transistor is turned off, the reset transistor discharges charge from the floating region, And when the storage transistor is turned on, the reset transistor discharges charge from the floating region and the storage capacitor element. 33. The method of claim 32, When the storage transistor is turned off, the floating region is discharged and a noise charge is read from the floating region, And when the storage transistor is turned on, the floating region and the storage capacitor element are discharged and noise charge is read from the floating region and the storage capacitor element.

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