KR101158393B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device capable of stably manufacturing a BCD device implemented in the same chip together with a CMOS transistor and a trench type DMOS transistor, for which the present invention is to provide a trench type DMOS transistor Providing a substrate defining a first region and a second region in which a CMOS transistor is to be formed, depositing a hard mask on the substrate, and performing an etching process using the hard mask to form the substrate in the first region. Forming first and second trenches in the trench, removing the hard mask, forming a gate oxide film of the DMOS transistor on inner walls of the first and second trenches, and forming the first and second trenches. Forming a data bus with a gate electrode of the DMOS transistor so that two trenches are buried, and It provides the step of forming a register of the gate oxide film, and a method of manufacturing a semiconductor device forming a CMOS gate electrode on the gate oxide of the CMOS transistors.

CMOS, DMOS, BCD

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

2 is a plan view of a semiconductor device manufactured according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: semiconductor substrate

11: field oxide film

12: buffer oxide film

13: HLD film

14: trench

15: sacrificial oxide film

16: trench gate oxide film

17a: gate electrode of DMOS transistor

17b: data bus

18a: oxide film

18b: gate oxide film of CMOS transistor

19: HLD film

20: gate electrode of CMOS transistor

21: LDD spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to implement a high frequency high voltage information communication system such as an automatic power integrated circuit (IC) and a DC / DC converter, which have recently been in great demand. The present invention relates to a method of manufacturing a BCD (Bipolar-CMOS-DMOS) device used for a smart card IC.

The process of a BCD device is complicated because it requires defining a complementary metal oxide semiconductor (CMOS) transistor and a trench type double diffused MOS (DMOS) transistor at the same time. In particular, when fabricating a CMOS transistor after fabricating a trench-type DMOS transistor, or fabricating a trench-type DMOS transistor after fabricating a CMOS transistor, the BFC device is stably manufactured because the profiles affect each other by the respective processes. There is a lot of difficulty.

Accordingly, the present invention has been made to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of stably manufacturing a BCD device implemented in the same chip together with a CMOS transistor and a trench type DMOS transistor. The purpose is.

According to an aspect of the present invention, there is provided a substrate including a substrate defining a first region in which a trench DMOS transistor is to be formed and a second region in which a CMOS transistor is to be formed, and a hard mask on the substrate. Forming a first and second trenches in the substrate of the first region by performing an etch process using the hard mask, removing the hard mask, and removing the first and second trenches. Forming a gate oxide film of the DMOS transistor on an inner sidewall of the second trench, forming a gate bus and a data bus of the DMOS transistor so that the first and second trenches are embedded, and forming the CMOS transistor in the CMOS region Forming a gate oxide film of the CMOS transistor, and forming a CMOS gate electrode on the gate oxide film of the CMOS transistor; Provided are a method of manufacturing a semiconductor device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

1A to 1H are cross-sectional views illustrating a manufacturing process of a BCD device, which is illustrated to explain a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention. Here, the same reference numerals shown in Figs. 1A to 1H are the same components to perform the same function.

First, as shown in FIG. 1A, a region in which a trench type DMOS transistor is to be formed (hereinafter referred to as a DMOS region) (DMOS) and a region in which a CMOS transistor is to be formed (hereinafter referred to as a CMOS region) (hereinafter referred to as CMOS) are defined. The field oxide film 11 is formed in the region of the semiconductor substrate 11. At this time, the field oxide film 11 is formed to a thickness of 4000 kPa to 4060 kPa. Preferably, the thickness is 4030 mm 3.

Subsequently, the buffer oxide film 12 is formed on the upper surface of the entire structure in which the field oxide film 11 is formed.

Subsequently, a high temperature low pressure dielectric (HLD) film 13 is deposited on the entire structure including the buffer oxide film 12. At this time, the HLD film 13 functions as a hard mask for forming subsequent trenches. The HLD film 13 is formed to a thickness of 4000 kPa to 5000 kPa. It is preferably formed to a thickness of 4500Å.

Subsequently, as shown in FIG. 1B, a photolithography process is performed to etch the HLD film 13 deposited on the DMOS region DMOS to expose a portion of the substrate 10 of the DMOS region DMOS.

Subsequently, an exposed substrate 10 is etched by performing an etching process using the etched HLD film 13 as an etching mask. As a result, a trench 14 is formed in a part of the DMOS region DMOS. At this time, the depth of the trench 14 is 1.2 micrometers-1.7 micrometers, and the width is 0.43 micrometers-0.47 micrometer. Preferably, the depth is 1.5 mu m and the width is 0.45 mu m. Meanwhile, although the trenches 14 are separated from each other and are formed independently in the same drawing, this is for convenience of description and actually has a form connected to each other. This will be described later.

Subsequently, as illustrated in FIG. 1C, a sacrificial oxide film 15 is formed on the inner surface of the exposed trench 14 by performing an oxidation process. At this time, the oxidation process is carried out by a dry oxidation process. In the dry oxidation process, an O ₂ gas is injected into a chamber maintained at a temperature of 1000 ° C. to 1200 ° C. (preferably 1100 ° C.), and then N ₂ gas is added to the chamber to provide a sacrificial oxide film 15 of 150 Pa. It proceeds until it is formed to a thickness of 250 kPa (preferably 200 kPa). Here, the reason why the N ₂ gas is added in the dry oxidation process is to form a sacrificial oxide film 15 having a high density by reducing the oxidation rate during the oxidation process to increase the oxidation time.

Subsequently, as shown in FIG. 1D, the sacrificial oxide film 15 (see FIG. 1C) and the HLD film 13 (see FIG. 1C) are removed.

Subsequently, the trench gate oxide film 16 is formed by performing an oxidation process on the portions where the sacrificial oxide film 15 and the HLD film are removed. In this case, the trench gate oxide layer 16 may be formed to have different thicknesses at portions formed on the inner surface of the trench 14 and portions formed on the upper surface of the substrate 10. For example, the upper surface of the substrate 10 is formed to have a thickness of 180 kPa to 220 kPa (preferably 200 kPa), and the trench 14 is formed to have a thickness of 225 kPa to 275 kPa (preferably 250 kPa). On the other hand, the oxidation process is carried out by a dry oxidation process, the dry oxidation process is injecting O ₂ gas into the chamber maintained at a temperature of 1000 ℃ to 1200 ℃ (preferably 1100 ℃) N ₂ inside the chamber This is done by adding gas.

Subsequently, as shown in FIG. 1E, a polysilicon layer is deposited on the entire structure including the trench 14 so that the trench 14 (see FIG. 1D) is embedded, and then a photolithography process is performed to form a trench type DMOS transistor. The gate electrode 17a and the data bus 17b are defined. The gate electrode 17a and the data bus 17b are as shown in FIG.

The DMOS region DMOS shown in FIG. 1E is a cross-sectional view taken along the line AA ′ and BB ′, and FIG. 1E shows the gate electrode 17a and the data bus 17b in one cross-sectional view for convenience of description. . Meanwhile, 'Active' illustrated in FIG. 2 is an active region, and 'CT1' and 'CT2' are contact plugs.

Next, as shown in FIG. 1F, the trench gate oxide film 16 remaining in FIG. 1E but not removed is removed.

Subsequently, the oxidation process is performed in a dry manner to form a gate oxide film 18b on the substrate 10 in the CMOS region (CMOS). At this time, the oxide film 18a is also formed on the top surface of the gate electrode 17a and the data bus 17b. The oxide layer 18a protects the gate electrode 17a and the data bus 17b during a gate electrode etching process to be formed in a subsequent CMOS region (CMOS).

Subsequently, the polysilicon layer, the tungsten silicide layer, and the HLD film are sequentially deposited, followed by a photolithography process to form the gate electrode 20 of the CMOS transistor in the CMOS region (CMOS). Here, the polysilicon layer is deposited at a thickness of 1300 kPa to 1700 kPa, preferably 1500 kPa, and the tungsten silicide layer is deposited at 1000 kPa to 1400 kPa, preferably 1200 kPa. Meanwhile, '19' is an HLD film.

Subsequently, as illustrated in FIG. 1G, an LDD (Lightly Doped Drain) HLD film is deposited on the entire structure on which the gate electrode 20 is formed, and then a front surface etching process is performed to form spacers on both sidewalls of the gate electrode 20. 21).

Thereafter, a source / drain ion implantation process is performed to form a source / drain region (not shown).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, it is possible to stably manufacture a BCD device in which a CMOS transistor and a trench type DMOS transistor are implemented together in the same chip.

Claims (8)

Providing a substrate defining a first region where a trench type DMOS transistor is to be formed and a second region where a CMOS transistor is to be formed; Depositing a hard mask on the substrate; Performing an etching process using the hard mask to form first and second trenches in the substrate of the first region; Removing the hard mask; Forming a gate oxide film of the DMOS transistor on inner walls of the first and second trenches; Forming a data bus with a gate electrode of the DMOS transistor to fill the first and second trenches; Forming a gate oxide film of the CMOS transistor in the CMOS region; And Forming a CMOS gate electrode on the gate oxide film of the CMOS transistor Method of manufacturing a semiconductor device comprising a. The method of claim 1, And a gate electrode and the data bus of the DMOS transistor are connected to each other. 3. The method according to claim 1 or 2, The hard mask is a semiconductor device manufacturing method of forming a HLD film. 3. The method according to claim 1 or 2, And forming a sacrificial oxide film on inner surfaces of the first and second trenches after forming the first and second trenches. The method of claim 4, wherein And removing the sacrificial oxide film at the same time during the hard mask removing process. 3. The method according to claim 1 or 2, And forming an oxide film on the gate electrode and the data bus of the DMOS transistor during the gate oxide film forming process of the CMOS transistor. The method of claim 6, And an oxide layer formed on the gate electrode of the DMOS transistor to protect the gate electrode of the DMOS transistor during a gate electrode etching process of the CMOS transistor. The method of claim 6, And an oxide layer formed on the data bus to protect the data bus during a gate electrode etching process of the CMOS transistor.

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