KR101082092B1 - Method of fabricating pattern in semicondutor device using spacer - Google Patents

Abstract

A method of forming cell patterns forming an array of 2 ⁿ cells, wherein the pattern target layer and the first mask layer are formed on a substrate, and one of the adjacent cell patterns is selected, and the outermost cell patterns are the target target patterns. The first mask patterns are formed using the first resist film pattern formed with a relatively larger line width. After forming spacers on the sidewalls of the first mask pattern, second mask patterns separated by the first mask patterns on which the spacers are formed are formed, and the spacers are removed. After patterning a region where the outermost cell pattern is to be formed as a target target pattern by using a second resist layer pattern partially exposing the first mask pattern of the outermost portion, the first mask patterns and the second mask patterns are etched. Etching the pattern target layer exposed by the mask to form an even number of cell patterns, and removing the first mask patterns and the second mask patterns.

Word Line, Cell Pattern, Flash Memory, Selective Transistors, Spacers

Description

Pattern forming method of semiconductor device using spacer {Method of fabricating pattern in semicondutor device using spacer}

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a pattern of a semiconductor device using a spacer.

Design rules are gradually reduced due to high integration of memory devices such as flash memory devices, which makes it difficult to implement fine patterns of devices. In particular, in manufacturing semiconductor devices, patterns using photolithography equipment are used. To form.

However, as the degree of integration of semiconductor devices increases, the pitch of the patterns also increases rapidly. However, it is difficult to form a fine pattern suitable for a required design rule using photolithography equipment. That is, the resolution required by the semiconductor device is smaller than the minimum resolution that can be decomposed using the photolithography equipment, which shows its limitation.

Accordingly, a pattern forming method using a spacer has been proposed to form a fine pitch pattern. In the pattern formation method using a spacer, patterns having a fine pitch that cannot be separated by a single exposure are formed in a double pitch form, that is, only one of two adjacent lines is first formed, and then a spacer is formed on the formed pattern, and the other is formed thereon. After depositing and planarizing an arbitrary sacrificial film, the deposited pattern is removed to pattern the remaining pattern target layer using the remaining pattern as an etch mask.

This method can form the thickness of a spacer normally thin enough, and since the control of the thickness is also easy, a fine pitch pattern can be formed using such a spacer.

However, such a pattern forming method requires the number of gate patterns required in the memory mainly to form an odd number of fine patterns, for example, 32 cells or 34 even cells in the case of a flash memory device. There is a problem that can not form a cell pattern.

According to an aspect of the present invention, there is provided a method of forming a pattern of a semiconductor device using a spacer, the method comprising: forming a cell pattern having 2 ⁿ arrays, including: forming a pattern target layer and a first mask layer on a substrate; Forming first mask patterns by selecting one of the adjacent cell patterns, wherein the outermost cell patterns are formed using a first resist film pattern having a line width relatively larger than a target target pattern; Forming spacers on sidewalls of the first mask pattern; Forming second mask patterns node-separated by the first mask patterns on which the spacers are formed; Removing the spacers; Patterning a region where the outermost cell pattern is to be formed as a target target pattern by using a second resist layer pattern partially exposing the first mask pattern of the outermost portion; Etching the pattern target layer exposing the first mask patterns and the second mask patterns as an etch mask to form an even number of cell patterns; And removing the first mask patterns and the second mask patterns.

The pattern formation method of a semiconductor device using a spacer according to an embodiment of the present invention,

CLAIMS What is claimed is: 1. A method of forming a select line on both sides of a word line and a word line forming 2 ⁿ arrays, the method comprising: forming a pattern target layer and a first mask layer on a substrate; Forming first mask patterns using a first resist layer pattern formed by selecting one of the adjacent word lines while having a line width relatively larger than a target pattern of the selection transistor; Forming spacers on sidewalls of the first mask pattern; Forming second mask patterns node-separated by the first mask pattern on which the spacers are formed; Removing the spacers; Patterning a region where the selection transistor is to be formed into a desired target pattern using a second resist layer pattern partially exposing the first mask pattern of the outermost portion; Forming a selection transistor on both sides of the word line and the word line forming 2 ⁿ arrays by etching the pattern target layer exposed through the first mask patterns and the second mask patterns as an etch mask; And removing the first mask patterns and the second mask patterns.

The line width of the outermost first mask pattern among the first mask patterns may be set in consideration of the spacer position formed on the sidewall of the first mask pattern adjacent to the spacer position deposited on the sidewall of the outermost first mask pattern. .

The forming of the spacer may include forming a spacer layer on the substrate on which the first mask patterns are formed; And forming an spacer on the sidewalls of the first mask patterns while anisotropically etching the spacer layer to expose the pattern target layer between the first mask patterns.

The forming of the second mask patterns may include forming a second mask layer on the substrate on which the spacer is formed; The planarization of the second mask layer may include exposing an upper surface of the first mask patterns.

(Example)

Referring to FIG. 1, the pattern target layer 110 to form a pattern is formed on the semiconductor substrate 100, and the barrier layer 120 and the first mask layer 130 are formed on the pattern target layer 110. Form. The pattern target film 110 may be formed of an insulating film or a conductive film. The barrier layer 120 is formed of a material layer having an etching selectivity with the pattern target layer 110 according to the material of the pattern target layer 110. The first mask layer 130 is formed of a material layer having an etching selectivity with the pattern target layer 110 and the barrier layer 120.

Here, the semiconductor substrate 100 has a plurality of blocks in which source lines (SSL) and drain selective lines (DSL) are arranged on both sides of word lines and word lines forming 2 ⁿ arrays through subsequent patterning. Can be arranged.

A first resist layer pattern 140 is formed on the first mask layer 130 to selectively expose the first mask layer 130. At this time, when the first resist film pattern 140 is formed, one of two adjacent word lines is selected and formed from the final target patterns, and SSL and DSL are simultaneously formed, but the size of SSL is larger than the line width of the target pattern of SSL. It is formed to have a relatively large line width.

Meanwhile, as shown in FIG. 10, the layout 200 of the final target pattern includes a plurality of word lines, for example, WL0 20, WL1 30, and WL2 ( 40, WL3 50... 32 WL31 (not shown) are arranged, and SSL 10 is disposed on the outermost WL0 20 side of the word line.

The layout of the first resist film pattern 140 with reference to the layout 200 of the final target pattern is one of two adjacent word lines, for example, odd number word line WL1 ( 30a), WL3 (50a) ... WL31 (not shown) is formed, and the line width of the SSL (10a) is formed relatively large, the position of the SSl (10) is a spacer formed in the WL0 (20) It is configured to target the location.

More specifically, as shown in FIG. 12, A represents the position of the final SSL 10 target pattern adjacent to the final WL0 20 target pattern, and B represents the position of the final WL0 20 target pattern. d1 denotes an interval of SSL 10a that is relatively large so as to be targeted to a position formed at the final WL0 20 from the position of the final SSL 10 to form an even number of fine patterns, and d2 denotes an SSL 10a. ) Shows the spacer line width formed on the sidewalls. d3 represents a line width of WL0 20 of the final target pattern, and d4 represents an interval between the WL0 20 and WL1 30 patterns.

That is, in consideration of the spacer position deposited by the SSL 10a in the first resist film pattern 140 and the spacer position formed on the sidewall of the WL1 30 of the final target pattern in order to realize the final desired target pattern, It is desirable to determine the size.

Referring to FIG. 2, the first mask layer 131 is formed by selectively etching the first mask layer using the first resist layer patterns 140 (in FIG. 1) as an etching mask. Here, the first mask patterns 131 serve as an etching mask for forming SSL having a relatively large line width and word lines having an odd number of numbers, for example, WL1, WL3 .. WL31. In this case, first mask patterns serving as an etching mask for forming a drain selective line (DSL) may be formed on the word line having the WL31 number.

The first mask patterns 131 may be formed using dry etching, for example, reactive ion etching.

 Referring to FIG. 3, after removing the first resist layer pattern, a sacrificial spacer 150 is formed on sidewalls of the first mask pattern 131. Specifically, after the sacrificial layer is formed on the semiconductor substrate 100 on which the first mask patterns 150 are formed, the sacrificial spacer 150 is formed on the sidewalls of the first mask pattern 131 by anisotropic etching to form the first mask pattern. The barrier film 120 between the 131 is selectively exposed. Anisotropic etching may be performed using an etch back method, but is not limited thereto.

Referring to FIG. 4, a second mask layer 160 is formed on the semiconductor substrate 100 on which the sacrificial spacers 130 are formed. The second mask layer 160 may be formed of the same material layer as the first mask layer, but is not limited thereto.

Referring to FIG. 5, a second mask pattern 161 is formed between the first mask patterns 131 on which the sacrificial spacers 150 are formed by exposing the upper surface of the first mask pattern 131 by performing a planarization process. . As a result, second mask patterns 161 having the same height are formed in the space between the first mask patterns 131.

Here, the second mask patterns 161 serve as an etching mask for forming subsequent even-numbered word lines, for example, WL0, WL2,... WL31.

Referring to FIG. 6, sacrificial spacers between the first mask patterns 131 and the second mask patterns 161 are removed. Removal of the sacrificial spacer can be performed by a wet etching process.

Referring to FIG. 7, a second resist pattern 170 is formed on the first mask patterns 131 and the second mask patterns 161 to selectively expose the outermost first mask pattern. The second resist pattern 170 protects the first mask patterns 131 and the second mask patterns 161 while patterning the outermost first mask pattern 131 for forming SSL as a final target pattern. Play a role. At this time, the second resist pattern 170 is preferably formed to be located at the final SSL position, for example, A shown in FIG. 12, in order to form the outermost first mask pattern 131 at the line width of the final desired SSL.

Referring to FIG. 8, the outermost first mask pattern exposed by the second resist pattern 170 (in FIG. 7) is etched to a final desired size of SSL. Then, an even number of fine patterns including the first mask patterns 131a and the second mask patterns 161 are formed. For example, the first mask patterns 131a and the second mask patterns 161 may include 32 word lines including an even number of word lines (WL), for example, WL0, WL1, WL2, WL3 ..... WL31. And an etch mask to form SSL and DSL with final target size.

After the barrier layers exposed by the first mask patterns 131a and the second mask patterns 161 are selectively etched to form even barrier layers 121, the second resist layer patterns are removed.

Referring to FIG. 9, after selectively etching the pattern target layer exposed by the barrier layer patterns, the first mask patterns, the mask patterns, and the barrier layer patterns are removed to form an even number of fine patterns 111. . The fine patterns 111 represent 32 word lines of WL0, WL1, WL2, WL3 ..... WL31 and memory cells of SSL and DSL on both sides of the wordline.

As described above, according to the present invention, an even number of cell patterns may be implemented without additional chip size.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 to 12 are views illustrating a method of forming a pattern of a semiconductor device using a spacer according to the present invention.

Claims (7)

In the method of forming a cell pattern of 2 ⁿ arrays, Forming a pattern target layer and a first mask layer on the substrate; Forming first mask patterns by selecting one of the adjacent cell patterns, wherein the outermost cell patterns are formed using a first resist film pattern formed with a line width relatively larger than a target target pattern; Forming spacers on sidewalls of the first mask pattern; Forming second mask patterns node-separated by the first mask patterns on which the spacers are formed; Removing the spacers; Patterning a region where the outermost cell pattern is to be formed as a target target pattern using a second resist layer pattern partially exposing the first mask pattern of the outermost portion; Etching the pattern target layer exposing the first mask patterns and the second mask patterns as an etch mask to form an even number of cell patterns; And  And removing the first mask patterns and the second mask patterns. Claim 2 has been abandoned due to the setting registration fee. Forming the spacers, Forming a spacer layer on the substrate on which the first mask patterns are formed; And Forming a spacer on the sidewalls of the first mask patterns while anisotropically etching the spacer film to expose the pattern target layer between the first mask patterns. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Forming the second mask patterns, Forming a second mask film on the substrate on which the spacer is formed; And planarizing the second mask layer to expose an upper surface of the first mask patterns. In the method of forming a select transistor on both sides of the word line and the word line forming a 2 ⁿ array, Forming a pattern target layer and a first mask layer on the substrate; Forming first mask patterns using a first resist layer pattern formed by selecting one of the adjacent word lines while having a line width relatively larger than a target pattern of the selection transistor; Forming spacers on sidewalls of the first mask pattern; Forming second mask patterns node-separated by the first mask pattern on which the spacers are formed; Removing the spacers; Patterning a region where the selection transistor is to be formed into a desired target pattern by using a second resist layer pattern partially exposing the first mask pattern of an outermost portion; Forming a selection transistor on both sides of the word line and the word line forming 2 ⁿ arrays by etching the pattern target layer exposed through the first mask patterns and the second mask patterns as an etch mask; And And removing the first mask patterns and the second mask patterns. Claim 5 was abandoned upon payment of a set-up fee. 5. The method of claim 4, The line width of the outermost first mask pattern among the first mask patterns may be set in consideration of a spacer position formed on a sidewall of the first mask pattern adjacent to the spacer position deposited on the outermost first mask pattern. Pattern formation method. Claim 6 was abandoned when the registration fee was paid. Forming the spacers, Forming a spacer layer on the substrate on which the first mask patterns are formed; And Forming a spacer on the sidewalls of the first mask patterns while anisotropically etching the spacer film to expose the pattern target layer between the first mask patterns. Claim 7 was abandoned upon payment of a set-up fee. 5. The method of claim 4, Forming the second mask patterns, Forming a second mask film on the substrate on which the spacer is formed; And planarizing the second mask layer to expose an upper surface of the first mask patterns.

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