KR100980423B1 - Input/output apparatus of semiconductor integrated circuit - Google Patents

Abstract

The present invention provides a receiver for receiving and comparing the write data input through the input and output pads with a reference voltage; A mismatch detector configured to detect a mismatch between the impedance of the input / output pad and a target impedance according to the output of the receiver and generate a mismatch detection signal; An impedance compensation code generator for generating an impedance compensation code by using the mismatch detection signal; And an impedance compensator for compensating a mismatch between the impedance of the input / output pad and a target impedance according to the impedance compensation code.

Semiconductor Integrated Circuits, Impedance Mismatch

Description

Input / output device for semiconductor integrated circuits {INPUT / OUTPUT APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to input and output devices of semiconductor integrated circuits.

Semiconductor integrated circuits employ On Die Termination to standardize impedance due to PVT (Process / Voltage / Temperature) variations.

The on die termination is an operation of matching the impedance of the DQ to a target value.

1 is a block diagram of an input / output device of a semiconductor integrated circuit according to the related art.

As shown in FIG. 1, an input / output device of a semiconductor integrated circuit according to the related art includes a receiver RX for receiving data, a latch LT for latching received data, and impedance matching of an input / output pad DQ. On-die termination block (ODT) for storage, fuse set for storing impedance adjustment information, impedance mismatch adjusting unit (RTT_CTRL) for impedance adjustment, driver (DRV) and input / output pad (DQ) for data output Test equipment is provided for controlling the fuse set through the impedance measurement of.

The above-described conventional technique uses the calibration code ZQC_CODE <0: N> to equalize the impedance of each input / output pad DQ with an external resistor connected to a ZQ pad (not shown) through the on die termination block ODT. It was operated to match.

Since the impedance matching operation described above is performed internally, an impedance mismatch may occur in which an impedance of the input / output pad DQ does not substantially match the impedance of an external resistor connected to the ZQ pad.

Therefore, the fuse set is configured for each input / output pad DQ, the impedance set is measured by measuring the impedance mismatch of the input / output pad DQ through test equipment, and the impedance mismatch adjusting unit RTT_CTRL is operated accordingly. Mismatch was compensated.

However, in the above-described conventional method, the impedance mismatch compensation can be performed only by the operator controlling the separate test equipment, and the mismatch compensation greatly occurs according to the resolution of the test equipment, and fuses are applied to the input / output pads (DQ). Since the set must be configured, there is a problem of increasing the circuit area due to the fuse set.

It is an object of the present invention to provide an input / output device of a semiconductor integrated circuit to automatically compensate for impedance mismatch without additional test equipment.

Another object of the present invention is to provide an input / output device of a semiconductor integrated circuit which enables uniform impedance mismatch compensation.

Another object of the present invention is to provide an input / output device of a semiconductor integrated circuit capable of reducing a circuit area for impedance mismatch adjustment.

An input / output device of a semiconductor integrated circuit according to the present invention includes a receiver for receiving write data inputted through an input / output pad in comparison with a reference voltage; A mismatch detector configured to detect a mismatch between the impedance of the input / output pad and a target impedance according to the output of the receiver and generate a mismatch detection signal; An impedance compensation code generator for generating an impedance compensation code by using the mismatch detection signal; And an impedance compensator for compensating for mismatch between the impedance of the input / output pad and the target impedance according to the impedance compensation code.

An input / output device of a semiconductor integrated circuit according to the present invention includes a driver configured to output data through an input / output pad with an impedance determined according to a first code; A receiver configured to receive data input through the input / output pad in comparison with a reference voltage; And an impedance configured to detect a mismatch between the impedance of the input / output pad and a target impedance according to the output of the receiver and compensate for the mismatch between the impedance of the input / output pad and the target impedance according to a second code generated according to the detection result. Compensation circuit section is another feature.

Since the input / output device of the semiconductor integrated circuit according to the present invention can automatically compensate for impedance mismatch, it is possible to improve convenience and work efficiency of impedance mismatch adjustment.

In addition, since the input / output device of the semiconductor integrated circuit according to the present invention performs impedance mismatch adjustment through a standardized internal circuit configuration, uniform impedance mismatch compensation between different semiconductor integrated circuit chips is possible.

In addition, since the input / output device of the semiconductor integrated circuit according to the present invention does not need a fuse set for impedance mismatch compensation, the layout margin can be improved.

Hereinafter, exemplary embodiments of an input / output device of a semiconductor integrated circuit according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of an input / output device of a semiconductor integrated circuit according to the present invention.

As shown in FIG. 2, an input / output device of a semiconductor integrated circuit according to the present invention includes a receiver 110, a driver 120, an on die termination block 130, a write data latch unit 140, and an impedance mismatch detection unit ( 150, an impedance compensator 160 and a control signal generator 170.

The receiver 110 is configured to receive data input through the input / output pad DQ.

The driver 120 has an impedance set by the calibration code ZQC_CODE <0: N>, and is configured to output the read data READ_DATA_OUT to the input / output pad DQ in response to the output enable signal DOE.

The on die termination block 130 is configured to set an impedance of the input / output pad DQ to match the calibration code ZQC_CODE <0: N> in response to an on die termination enable signal ODT_EN.

The write data latch unit 140 is configured to latch data received through the receiver 110 according to the data strobe signal DQS.

The impedance mismatch detection unit 150 is configured to latch the data received through the receiver 110 according to the impedance strobe signal RTT_STROBE to generate the mismatch detection signal COMPARE_OUT.

The impedance compensator 160 transmits the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> in response to the impedance control enable signals ENABLE_P <0: 2> and ENABLE_N <0: 2>. Therefore, the impedance mismatch of the input / output pad DQ is compensated for.

The impedance compensation code generating unit 170 generates the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> using the mismatch detection signal COMPARE_OUT according to the impedance strobe signal RTT_STROBE. It is composed.

3 is a circuit diagram of an impedance compensator of FIG. 2.

As shown in FIG. 3, the impedance compensator 160 includes a plurality of pull up legs 161a to 161c and pull down legs 163a to 163c. The pull-up legs 161a to 161c may be configured in the same manner. The pull-down legs 163a to 163c may be configured in the same manner.

In the embodiment of the present invention, the pull-up legs 161a to 161c and the pull-down legs 163a to 163c are three examples, respectively. The larger the number, the more mismatch compensation capability is improved. Therefore, the number can be appropriately adjusted in consideration of the layout. Of course, as the number of pull-up legs 161a to 161c and pull-down legs 163a to 163c increases, the impedance control enable signals ENABLE_P <0: 2> and ENABLE_N <0: 2> and impedance compensation codes ( The number of bits of RP_CODE <0: 2> and RN_CODE <0: 2> also increases.

The pull up leg 161a is activated according to the impedance control enable signal ENABLE_P <0: 2>, and the pull down leg 163 is activated according to the impedance control enable signal ENABLE_N <0: 2>. .

Each of the pull up leg 161 and the pull down leg 163 is basically designed to have an impedance of 120 ohms, and the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> Accordingly, impedance adjustment is performed in a direction to compensate for the impedance mismatch of the input / output pad DQ. By selectively enabling the impedance control enable signals ENABLE_P <0: 2> and ENABLE_N <0: 2>, the impedance of the impedance compensator 160 may be changed to 120 ohms, 60 ohms, 40 ohms, or the like. Can be.

4 is a circuit diagram of the pull up leg of FIG.

As shown in FIG. 4, the pull-up leg 161a includes a signal processing circuit 161-1, a plurality of transistors WP to WP * 4, and a plurality of resistors RP * 32 to RP * 8. do.

In the signal processing circuit 161-1, a circuit including an inverter IV1 and a NAND gate ND1 is provided with the number of bits of the impedance compensation code RP_CODE <0: 2>.

When the impedance control enable signal ENABLE_P <0> is activated, the signal processing circuit 161-1 may output the impedance compensation code RP_CODE <0: 2> to the impedance pull-up compensation signal RTT_UPCODE <0: 2>. ) Are output to the plurality of transistors WP to WP * 4.

5 is a circuit diagram of the pull-down leg of FIG.

As shown in FIG. 5, the pull down leg 163a includes a signal processing circuit unit 163-1, a plurality of resistors RN * 32 to RN * 8, and a plurality of transistors WN to WN * 4. do.

The signal processing circuit unit 163-1 includes a circuit including the NAND gate ND11 and the inverter IV11 as many as the number of bits of the impedance compensation code RN_CODE <0: 2>.

When the impedance control enable signal ENABLE_N <0> is activated, the signal processing circuit unit 163-1 may convert the impedance compensation code RN_CODE <0: 2> to the impedance pull-down compensation signal RTT_DNCODE <0: 2>. ) Are output to the plurality of transistors WN to WN * 4.

In this case, the symbols of the transistors and the resistors provided in the pull up leg 161a and the pull down leg 163a are given based on the corresponding size. That is, the transistor WP * 4 is designed to be four times larger than the transistor WP, and the resistor RP * 32 is designed to be four times larger than the resistor RP * 8.

Although not shown in the drawings, the pull-up legs and the pull-down legs as shown in FIGS. 4 and 5 also exist in the on die termination block 130. The pull-up leg 161a and the pull-down leg 163a of the impedance compensator 160 receive the upper part bits of the calibration code ZQC_CODE <0: N> from the on die termination block 130. And a combination of a transistor and a resistor of the pull down leg.

6 is a circuit diagram of an impedance compensation code generator of FIG. 2.

As shown in FIG. 6, the impedance compensation code generator 170 includes a compensation code adjustment activation unit 171 and a signal generator 172.

The compensation code adjustment enabler 171 is configured to generate a compensation code adjustment enable signal ENABLE according to the start pulse signal INITP, the impedance strobe signal RTT_STROBE, and the mismatch detection signal COMPARE_OUT.

The compensation code adjustment activation unit 171 includes an inverter IV21, transistors M21 and M22, a latch 171-1, a first flip-flop 171-2, a second flip-flop 171-3, and a NAND. A gate ND21 and an XOR gate XOR21 are provided.

The compensation code adjustment activation unit 171 initializes the compensation code adjustment activation signal ENABLE as the start pulse signal INITP is generated. The compensation code adjustment activation unit 171 activates the compensation code adjustment activation signal ENABLE in response to the impedance strobe signal RTT_STROBE. In addition, the compensation code adjustment activator 171 detects a change in the mismatch detection signal COMPARE_OUT when the previous mismatch detection signal COMPARE_OUT and the current mismatch detection signal COMPARE_OUT have different values, and adjusts the compensation code adjustment. Reinitialize the enable signal (ENABLE).

The signal generator 172 may perform impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> according to the compensation code adjustment enable signal ENABLE, the mismatch detection signal COMPARE_OUT, and the impedance strobe signal RTT_STROBE. Is generated).

The signal generator 172 includes a delay element DLY, an inverter IV31, NAND gates ND31 to ND34, a first counter 172-1, and a second counter 172-2.

The signal generator 172 may perform an impedance compensation code RP_CODE <0: 2 according to a mismatch detection signal COMPARE_OUT during an activation period of the impedance strobe signal RTT_STROBE while the compensation code adjustment activation signal ENABLE is activated. >, RN_CODE <0: 2>) is increased. In addition, counting values of the first counter 172-1 and the second counter 172-2 may be initialized by a reset signal RST.

The mismatch detection signal COMPARE_OUT maintains the same logic value during impedance mismatch compensation. Subsequently, when the voltage level of the input / output pad DQ increases or decreases repeatedly to exceed the reference voltage level, the impedance mismatch compensation is completed. When the impedance mismatch compensation is completed, the impedance value to be compensated for is smaller than that of the impedance change unit of the impedance compensator 160. Therefore, the subsequent mismatch detection signal COMPARE_OUT changes to a different logic level than before.

As the mismatch detection signal COMPARE_OUT changes to a logic level different from the previous one, the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> also change in the opposite manner, and thus the voltage level of the input / output pad DQ. The reference voltage (VERF) level is exceeded in the opposite direction as before. Through this process, even if the impedance mismatch compensation is completed, the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> do not maintain their current values and continue to toggle.

Therefore, by detecting the mismatch detection signal COMPARE_OUT and initializing the compensation code adjustment enable signal ENABLE, the unnecessary impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> are toggled. To prevent.

7 is an operation timing diagram of an input / output device of a semiconductor integrated circuit according to the present invention.

First, in an ideal semiconductor integrated circuit that completely compensates for PVT variation, the voltage level of the input / output pad DQ and the reference voltage VERF should be the same in a non-operating state, that is, a state in which no data output or input is made.

However, in an actual situation, as shown in FIG. 7, a predetermined level difference exists between the voltage level of the input / output pad DQ and the reference voltage VERF.

Accordingly, the present invention uses the above-described principle, and detects and compensates a voltage level mismatch between the input / output pad DQ and the reference voltage VERF in the inactive state of the semiconductor integrated circuit.

Referring to FIG. 6, the compensation code adjustment enabler 171 outputs the output signal XOR_ENABLE of the low level first flip-flop 171-2 to the NAND gate ND21 as the impedance strobe signal RTT_STROBE is generated. Is applied and accordingly activates the compensation code adjustment enable signal ENABLE to a high level.

Thereafter, as the second impedance strobe signal RTT_STROBE is generated, the output signal XOR_ENABLE of the first flip-flop 171-2 transitions to a high level. At this time, the mismatch detection signal COMPARE_OUT and the previous mismatch detection signal COMPARE_SHIFT are at the same level (low level), and accordingly, the output signal COMPARE_XOR of the XOR gate XOR21 is low level, so that the compensation code adjustment enable signal ENABLE. Keep it active.

Meanwhile, the signal generator 172 of FIG. 6 logically multiplies the mismatch detection signal COMPARE_OUT and the delayed impedance strobe signal RTT_STROBE_D by which the impedance strobe signal RTT_STROBE is delayed, thereby performing impedance compensation code RP_CODE <0: 2>. , RN_CODE <0: 2>) is increased.

In this case, since the mismatch detection signal COMPARE_OUT is generated by the impedance strobe signal RTT_STROBE (see FIG. 2), a predetermined time difference exists between the two signals. Therefore, in consideration of the predetermined time difference, the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> are adjusted by combining the delayed impedance strobe signal RTT_STROBE_D and the mismatch detection signal COMPARE_OUT.

The mismatch detection signal COMPARE_OUT detects whether the voltage level of the input / output pad DQ is higher or lower than the reference voltage VERF. If the mismatch detection signal COMP_EOUT is low, the input / output pad DQ is detected. When the voltage level is lower than that of the reference voltage VERF and the pull-up impedance of the impedance compensator 160 is large, the mismatch detection signal COMPPARE_OUT means a high level, and vice versa.

Therefore, when the mismatch detection signal COMPARE_OUT is at the low level, the first counter 172-1 operates to increase the impedance compensation code RP_CODE <0: 2>.

The voltage level of the input / output pad DQ increases in proportion to the increase in the impedance compensation code RP_CODE <0: 2>.

Whenever the impedance strobe signal RTT_STROBE occurs, the increase of the impedance compensation code RP_CODE <0: 2> is repeated, thereby increasing the voltage level of the input / output pad DQ.

When the above-described adjustment of the impedance compensation codes RP_CODE <0: 2> and RN_CODE <0: 2> is repeated, the voltage level of the input / output pad DQ substantially matches the reference voltage VERF at a predetermined point in time. In practice, this is higher than the reference voltage (VERF).

Since the voltage level of the input / output pad DQ is higher than the reference voltage VERF, the mismatch detection signal COMP_E_OUT transitions to a high level.

Since the previous mismatch detection signal COMPARE_SHIFT is at a low level when the mismatch detection signal COMPARE_OUT is at a high level, the output signal COMPARE_XOR of the XOR gate XOR21 of the compensation code adjustment enabler 171 is at a high level. To transition to.

Since the output signal COMPARE_XOR of the XOR gate XOR21 is at a high level and the output signal XOR_ENABLE of the first flip-flop 171-2 is also maintained at a high level, the compensation code adjustment enable signal ENABLE is at a low level. Is initialized to

Since the compensation code adjustment enable signal ENABLE is initialized to a low level, the impedance compensation code RP_CODE <0: 2>, even if the logic value of the mismatch detection signal COMPPARE_OUT continues to change according to the generation of the impedance strobe signal RTT_STROBE, RN_CODE <0: 2>) is maintained at the final value, that is, the value at the completion of the impedance compensation.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of an input / output device of a semiconductor integrated circuit according to the prior art;

2 is a block diagram of an input / output device of a semiconductor integrated circuit according to the present invention;

3 is a circuit diagram of an impedance compensator of FIG. 2;

4 is a circuit diagram of the pull up leg of FIG.

5 is a circuit diagram of the pull-down leg of FIG.

6 is a circuit diagram of an impedance compensation code generator of FIG. 2;

7 is an operation timing diagram of an input / output device of a semiconductor integrated circuit according to the present invention.

<Description of Symbols for Main Parts of Drawings>

110: receiver 120: driver

130: on die termination block 140: write data latch portion

150: impedance mismatch detection unit 160: impedance compensation unit

170: impedance compensation code generator

Claims (23)

A receiver configured to receive write data input through an input / output pad in comparison with a reference voltage; A mismatch detector configured to detect a mismatch between the impedance of the input / output pad and a target impedance according to the output of the receiver to generate a mismatch detection signal; An impedance compensation code generator configured to generate an impedance compensation code using the mismatch detection signal; And And an impedance compensator configured to compensate for mismatch between the impedance of the input / output pad and the target impedance by varying the impedance of the input / output pad according to the impedance compensation code. The method of claim 1, And an on die termination block configured to perform on die termination of the input / output pad according to a code signal generated by comparing an external resistor and an internal resistor. The method of claim 1, The impedance compensation code generator And an input / output device of a semiconductor integrated circuit configured to vary a code value of the impedance compensation code according to the mismatch detection signal during an activation period of a strobe signal. The method of claim 3, wherein The impedance compensation code generator A compensation code adjustment activation unit configured to activate a compensation code adjustment activation signal in response to the strobe signal; And a signal generator configured to vary a code value of the impedance compensation code according to the mismatch detection signal during an activation period of the strobe signal while the compensation code adjustment activation signal is activated. The method of claim 4, wherein The compensation code adjustment activation unit And an inactivating compensation code adjustment enable signal according to a comparison result of a current value and a previous value of the mismatch detection signal. The method of claim 5, The compensation code adjustment activation unit A first flip-flop for shifting a latched signal according to the strobe signal in response to activation of the strobe signal, A second flip-flop for shifting a current value of the mismatch detection signal in response to activation of the strobe signal; A first logic element for performing a first logic operation on a current value of the mismatch detection signal and an output of the second flip-flop, and And a second logic element configured to perform a second logic operation on the output of the first flip-flop and the output of the first logic element. The method of claim 4, wherein The signal generator A first counter configured to count a predetermined code signal in response to the mismatch detection signal and output the first code as a first impedance compensation code; A second counter configured to count a predetermined code signal in response to the inverted mismatch detection signal and output the second code as a second impedance compensation code; and And a plurality of logic elements configured to deliver the mismatch detection signal to the first counter and the second counter in a phase opposite to the original phase in response to the activation of the compensation code adjustment activation signal and the strobe signal. I / O device of integrated circuit. The method of claim 5, The mismatch detection unit An input / output device of a semiconductor integrated circuit configured to latch an output signal of the receiver in response to the strobe signal to output the mismatch detection signal. The method of claim 8, The mismatch detection unit And a flip flop for latching an output signal of the receiver using the strobe signal as a clock signal. The method of claim 5, The impedance compensator A semiconductor having a plurality of leg circuits connected to the input / output pads, the impedances of the plurality of leg circuits being determined according to the impedance compensation code, and configured to selectively operate the plurality of leg circuits according to an impedance control enable signal; I / O device of integrated circuit. The method of claim 10, The impedance compensation code includes a first impedance compensation code and a second impedance compensation code, The impedance control enable signal includes a first impedance control enable signal and a second impedance control enable signal, The plurality of leg circuits are at least two pull up legs whose impedance is determined according to the first impedance compensation code and is activated according to the first impedance control enable signal, and An input / output device of a semiconductor integrated circuit having an impedance determined according to the second impedance compensation code and having at least two pull down legs activated according to the second impedance control enable signal. The method of claim 11, The pull up leg A logic circuit for passing the first impedance compensation code according to the first impedance control enable signal; A plurality of transistors connected to a power supply terminal and operating according to the first impedance compensation code transmitted from the logic circuit; And a plurality of resistors having one end connected to each of the plurality of transistors and the other end connected to the input / output pad in common. The method of claim 11, The pull down leg A logic circuit for passing the second impedance compensation code according to the second impedance control enable signal; A plurality of transistors connected to a ground terminal and operating according to the second impedance compensation code transmitted from the logic circuit; And a plurality of resistors having one end connected to each of the plurality of transistors and the other end connected to the input / output pad in common. A driver configured to output data through the input / output pad with an impedance determined according to the first code; A receiver configured to receive data input through the input / output pad in comparison with a reference voltage; And An impedance compensation circuit unit configured to detect a mismatch between the impedance of the input / output pad and a target impedance according to the output of the receiver and compensate a mismatch between the impedance and the target impedance of the input / output pad according to a second code generated according to a detection result An input / output device of a semiconductor integrated circuit having a. The method of claim 14, And an on die termination block configured to perform on die termination of the input and output pads according to the first code. The method of claim 14, The impedance compensation circuit unit A mismatch detection unit configured to generate mismatch detection signals by detecting mismatch between impedances of the input / output pads and target impedances according to the output of the receiver; A code generator configured to generate the second code using the mismatch detection signal, and And an impedance compensator configured to compensate for mismatch between the impedance of the input / output pad and the target impedance by varying the impedance of the input / output pad according to the second code. The method of claim 16, The mismatch detection unit And an output device of the semiconductor integrated circuit configured to latch an output signal of the receiver in response to a strobe signal to output the mismatch detection signal. The method of claim 16, The code generation unit An input / output device of a semiconductor integrated circuit configured to vary a code value of the second code according to the mismatch detection signal during an activation period of a strobe signal. The method of claim 18, The code generation unit And an input / output device of a semiconductor integrated circuit configured to prevent the second code from being changed according to a comparison result between a current value and a previous value of the mismatch detection signal. The method of claim 16, The impedance compensator A plurality of leg circuits connected to the input / output pads, the impedances of the plurality of leg circuits are determined according to the second code, and the plurality of leg circuits are selectively operated according to an impedance control enable signal. An input / output device of a semiconductor integrated circuit configured to vary an impedance of the semiconductor integrated circuit. The method of claim 20, The second code includes a first impedance compensation code and a second impedance compensation code, The impedance control enable signal includes a first impedance control enable signal and a second impedance control enable signal, The plurality of leg circuits are at least two pull up legs whose impedance is determined according to the first impedance compensation code and is activated according to the first impedance control enable signal, and An input and output device of a semiconductor integrated circuit having an impedance determined according to the second impedance compensation code and having at least two pull down legs activated according to the second impedance control enable signal. The method of claim 21, The pull up leg A logic circuit for passing the first impedance compensation code according to the first impedance control enable signal; A plurality of transistors connected to a power supply terminal and operating according to the first impedance compensation code transmitted from the logic circuit; And a plurality of resistors having one end connected to each of the plurality of transistors and the other end connected to the input / output pad in common. The method of claim 21, The pull down leg A logic circuit for passing the second impedance compensation code according to the second impedance control enable signal; A plurality of transistors connected to a ground terminal and operating according to the second impedance compensation code transmitted from the logic circuit; And a plurality of resistors, one end of which is connected to the plurality of transistors and the other end of which is commonly connected to the input / output pad.

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