KR100928163B1 - A display device and a method of manufacturing a semiconductor device - Google Patents

Abstract

Optimum TFT structures for the pixel portion and the driving conditions of the driving circuit are obtained using a small number of photo masks. First to third semiconductor films are formed on the first insulating film. First, second, and third electrodes of a first shape are formed in the first to third semiconductor films. The first, second, and third electrodes of the first shape are used as masks in the first doping process to form impurity regions of one conductivity type at a first concentration in the first to third semiconductor films. The first, second, and third electrodes of the second shape are formed from the first, second, and third electrodes of the first shape. In the second doping treatment, an impurity region of one conductivity type with a second concentration overlapping the second electrode of the second shape is formed in the second semiconductor film. Further, in the second doping treatment, impurity regions of one conductivity type at a third concentration which are placed on the first and second semiconductor films are formed. In the third doping process, impurity regions of the fourth and fifth concentrations having another conductivity type opposite to one conductivity type are formed in the third semiconductor film.

Doping treatment, semiconductor device, semiconductor film, conductive film, impurity region, electrode

Description

A display device and a method of manufacturing a semiconductor device

1A and 1B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

2A and 2B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

3A and 3B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

4 is a cross-sectional view illustrating a process of manufacturing a TFT according to the present invention.

5 is a top view illustrating the structure of a pixel portion of an active matrix substrate of a reflective display device.

6 is a diagram illustrating a circuit structure of an active matrix substrate.

7A and 7B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

8A and 8B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

9A and 9B are cross-sectional views illustrating a process of manufacturing a TFT according to the present invention.

10 is a cross-sectional view illustrating a process of manufacturing a TFT according to the present invention.

11A and 11B are cross-sectional views illustrating a method of manufacturing a transmissive display device.

12 is a cross-sectional view showing a structure of a transmissive liquid crystal display device.

13 is a cross-sectional view illustrating a structure of a pixel portion in a light emitting device.

14 is a sectional view showing a structure of a light emitting device.

15 is a transmission diagram illustrating the structure of an active matrix substrate.

16A to 16E illustrate a process of manufacturing a semiconductor film having a liquid crystal structure.

17A to 17C are views for explaining a process for producing a semiconductor film having a liquid crystal structure.

18 is a cross-sectional view illustrating a structure of an active matrix substrate of the present invention.

19A and 19B show the structure of an NMOS circuit.

20A and 20B show the structure of a shift register.

Fig. 21 is a diagram showing the structure of a gate line driver circuit composed of n-channel TFTs.

22 is a timing diagram of a decoder input signal.

Fig. 23 is a diagram showing the structure of a data line driver circuit composed of n-channel TFTs.

Fig. 24 is a diagram showing the structure of a gate line driver circuit composed of p-channel TFTs.

25 is a timing diagram of a decoder input signal.

Fig. 26 is a diagram showing the structure of a data line driver circuit composed of p-channel TFTs.

27A-27F illustrate examples of semiconductor devices.

28A-28C illustrate examples of semiconductor devices.

29 is an explanatory diagram illustrating the process of manufacturing a semiconductor film having a crystal structure.

30 is a graph showing a profile of phosphorous doping through a gate insulating film and a tantalum nitride film.

FIG. 31 is a graph in which the tantalum nitride film thickness is converted to the gate insulating film thickness and fitted, where the tantalum nitride film thickness is multiplied by a constant.

Explanation of symbols on the main parts of the drawings

101: substrate 102, 103: first insulating film

104 to 107: semiconductor film 108, 122: second insulating film

111 to 114: resist mask

116 to 118: electrodes of the first shape

Field of invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a thin film transistor (hereinafter referred to as TFT) composed of a semiconductor film formed on a substrate with a crystal structure, and a method of manufacturing the semiconductor device.

Description of the related technology

Displays for displaying text and images are an essential means for people to obtain information in various semiconductor devices having semiconductor elements such as television receivers, personal computers, and cellular phones. CRT has long been a representative display in the market. On the other hand, liquid crystal displays and other flat panel displays (flat panel displays) have recently increased exponentially, which is desirable to reduce the weight and size of electronic devices.

One mode of flat panel displays is an active matrix driving scheme in which TFTs are provided for each pixel or dot, and data signals are sequentially recorded to display an image. TFT is an essential element in active matrix driving.

Most of the TFTs are formed of amorphous silicon. Since these TFTs cannot operate at high speed, they are used only as switching elements provided in each dot. Since the TFT cannot make a device other than a switching element, an external IC (driver IC) mounted by tape automated bonding (TAB) or chip on glass (COG) allows a data line side driving circuit and a scan to output a video signal to a data line. It is used in a scanning line side driving circuit for outputting a signal to a scanning line.

However, mounting the driver IC is considered to be a limited method because the pixel pitch decreases as the pixel density increases. For example, at the pixel density of the UXGA level (1200 x 1600 pixels) of the RGB color method, at least 6000 connection terminals are required as a rough estimate. Increasing the number of connection terminals increases the number of occurrences of contact failure. This also increases the border area (called an image frame area) around the pixel portion, which hinders the reduction of the size of the semiconductor device using this display and ruins the external design of the semiconductor device. Against this background, there is a clear need for a display device in which the driving circuit is integrated in the pixel portion. By integrating and forming the pixel portion and the scanning line side and data line side driving circuits on the same substrate, not only the number of connecting terminals but also the area of the image frame area can be significantly reduced.

Integrated drive circuitry is required to improve certainty by having high drive performance (ON current: I _on ) and preventing degradation due to hot carrier effects, while low OFF current (I _off ) is required in the pixel portion. do. Lightly doped drain (LDD) structures are known as TFT structures that can reduce the OFF current value. In the LDD structure, an LDD region slightly doped with an impurity element is located between the channel formation region and a drain region or source region heavily doped with an impurity element. A structure known to be effective in preventing a decrease in the ON current due to hot carriers is known as an LDD structure in which the LDD region partially overlaps the gate electrode (gate-drain overlapped LDD; later referred to as gate-drain overlapped LDD). )to be.

The TFT is manufactured by laminating a semiconductor film, an insulating film or a conductive film while etching the film into a predetermined shape using a photo mask. If the optimization of the TFT structure is dealt with simply by increasing the number of photo masks as required for the pixel portion and the driving circuit, the manufacturing process becomes complicated and the number of steps inevitably increases.

Since the present invention has been made to solve this problem, it is an object of the present invention to provide a technique for obtaining a TFT structure that is optimal for driving conditions of a pixel portion and a driving circuit using a small number of photo masks.

To achieve the above object of the present invention, the present invention adopts a two-layered gate electrode in which the first layer in contact with the gate insulating film is longer in the channel length direction than the second layer. The gate electrode of the two-layer structure is used to form source and drain regions and LDD regions in a self-aligned manner in the n-channel TFT of the driver circuit portion. In the pixel portion, the source and drain regions of the n-channel TFT and the LDD region are formed using a photo mask rather than a self-aligning method. In the driver circuit portion, the LDD region of the n-channel TFT is positioned to overlap with the gate electrode, and in the pixel portion, the LDD region of the n-channel TFT is positioned outside the gate electrode (not overlapping with the gate electrode). The source and drain regions and two types of LDD regions having different positional relations with respect to the gate electrode are formed through two doping processing steps.

As mentioned above, a method of manufacturing a semiconductor device according to the present invention is:

Forming first to third semiconductor films separated from each other in the first insulating film;

Forming a first electrode, a second electrode, and a third electrode on the first semiconductor film, the second semiconductor film, and the third semiconductor film by interposing a second insulating film between the electrodes and the films; Said forming step having a first shape;

Using first to third electrodes of a first shape as a mask in a first doping process to form an impurity region of one conductivity type at a first concentration in the first to third semiconductor films;

Forming first to third electrodes of a second shape from first to third electrodes of a first shape;

Forming a single impurity region of a second conductivity type in the second semiconductor film through a second doping process, and forming an impurity region of a third conductivity type in the first semiconductor film and the second semiconductor film as The forming step wherein the impurity region of the second concentration overlaps with a second electrode of a second shape; And

Forming an impurity region of a fourth concentration and an impurity region of a fifth concentration in a third semiconductor film through a third doping process, the regions having the other conductivity type opposite to one conductivity type; It is characterized by. In other words, the semiconductor device manufacturing method of the present invention is characterized in that the etching process for forming the gate electrode of the TFT is combined with the doping process to form the LDD region and the source or drain region in a self-aligned manner.

Furthermore, according to another structure of the present invention, the method is:

Forming a first semiconductor film, a second semiconductor film, and a third semiconductor film separated from each other in the first insulating film; Forming a first electrode having a first shape by interposing a second insulating film on the first semiconductor film; Using a first electrode of a first shape as a mask to form an impurity region of one conductivity type at a first concentration in the first semiconductor film; Forming a second electrode and a third electrode having a first shape by interposing a second insulating film between the semiconductor films and the electrodes on the second semiconductor film and the third semiconductor film; Etching the second electrode and the third electrode of the first shape to form a second electrode and the third electrode of the second shape; Forming an impurity region of one conductivity type at a second concentration in the second semiconductor film, and forming an impurity region of one conductivity type at a third concentration in the first semiconductor film and the second semiconductor film through a second doping process Wherein the impurity region of the second concentration overlaps with the second electrode of the second shape; And forming an impurity region of a fourth concentration and an impurity region of a fifth concentration in the third semiconductor film through a third doping process, wherein the regions have another conductivity type opposite to one conductivity type. It is characterized by including.

With this manufacturing method, the LDD overlapping with the gate electrode is formed in a self-aligned manner in the n-channel TFT of the drive circuit. This LDD is obtained at the same time as the source or drain region is formed through the same doping step by using the film thickness difference (level difference) of the gate electrode. On the other hand, a mask is used to form an LDD that does not overlap the gate electrode in the n-channel TFT of the pixel portion.

The term semiconductor device in the present invention generally refers to a device using semiconductor functional characteristics, and typically, a display device, a liquid crystal display device having a TFT, and a semiconductor integrated circuit (microprocessor, signal processing circuit, high frequency circuit, etc.) It is included there.

Example mode 1

An embodiment mode of the present invention is described with reference to FIGS. 1A-6. Here, a method of simultaneously forming TFTs of the pixel portion and TFTs (n-channel TFT and p-channel TFT) of the driving circuit located near the pixel portion on the same substrate will be described in detail.

In FIG. 1A, the substrate 101 is a glass substrate, a quartz substrate, or a ceramic substrate. A silicon substrate, a metal substrate, or a stainless steel substrate, with an insulating film formed on its surface, may be used instead. Plastic substrates can also be used, provided they have a thermal resistance that can withstand the processing temperatures of this embodiment mode.

First insulating films 102 and 103 are formed on the substrate 101. The first insulating film shown here has a two-layer structure, but may of course have a single layer structure. The semiconductor films 104 to 107 are semiconductors having a crystal structure. The semiconductor film is obtained by crystallizing the amorphous semiconductor film formed on the first insulating film. After deposition, the amorphous semiconductor film is crystallized by heat treatment or laser light irradiation. Although the material of the amorphous semiconductor film is not limited, an alloy of silicon or silicon germanium (Si _x Ge _1-x ; 0 <x <1, typically x = 0.001 to 0.05) is preferably used.

When the amorphous semiconductor film is crystallized by laser beam irradiation, a pulse oscillation type or continuous-wave gas gas or solid state laser is used. Examples of gas lasers used include KrF excimer lasers, ArF excimer lasers, and XeCl excimer lasers. In the laser emitter used, crystals of YAG, YVO ₄ , YLF, YAlO _3, etc., are doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm. Although the material used for the doping varies, the fundamental wave of the laser emitted from the laser emitter has a wavelength of 1 μm to 2 μm. In order to crystallize the amorphous semiconductor film, laser light must be selectively absorbed by the semiconductor film. Therefore, it is preferable to select a laser light having a wavelength between visible light and ultraviolet light and to use second to fourth harmonics of the fundamental wave. Typically, the amorphous semiconductor film is crystallized using a second harmonic (532 nm) by an Nd: YVO ₄ laser emitter (fundamental wave: 1064 nm). In addition, gas laser emitters such as argon laser emitters and krypton laser emitters can be used.

Prior to crystallization, the amorphous semiconductor film may be doped with nickel or another metal element having a catalytic effect on the crystallization of the semiconductor. For example, a solution containing nickel is kept on the surface of an amorphous silicon film, and the film is dehydrated (for 1 hour at 500 ° C.), and then thermal crystallization is performed (for 4 hours at 550 ° C.). At this time, the film is irradiated with a second harmonic of continuous wave laser light selected from YAG laser, YVO ₄ laser, and YLF laser to improve crystallinity.

Next, a second insulating film 108 is formed to cover the semiconductor films 104 to 107. The second insulating film 108 is an insulating film containing silicon, and is formed by plasma CVD or sputtering. Its thickness is set to 40 to 150 nm. The second insulating film formed to cover the semiconductor films 104 to 107 is used as the gate insulating film of the TFT manufactured in this embodiment mode.

A conductive film for forming the gate electrode and the wiring is formed on the second insulating film 108. The gate electrode of the present invention is formed by stacking two or more conductive films. The first conductive film 109 is formed on the second insulating film 108 from a nitride of a metal having a high melting point such as molybdenum or tungsten. The second conductive film 110 is formed on the first conductive film from a metal having a high melting point, or a low resistance metal such as aluminum and copper, or polysilicon. In particular, a nitride of at least one element type selected from the group consisting of W, Mo, Ta, and Ti is used as the first conductive film, while the second conductive film is a group consisting of W, Mo, Ta, Ti, Al, and Cu. Alloys of one or more element types selected from n or polycrystalline silicon are used.

As shown in Fig. 1B, resist masks 111 to 114 are next formed to perform a first etching process on the first conductive film and the second conductive film. Through this etching process, tapered first shaped electrodes 116 to 118 and first shaped wirings 114 and 115 are formed around the edges. The electrodes are tapered at an angle of 45 to 75 degrees. The region of the second insulating film 122 which is not covered with the first shaped electrodes 116 to 118 and the wirings 114 and 115 of the first formation is etched to become thin by 20 to 50 nm.

The first doping treatment uses ion implantation or ion doping in which ions are inserted without mass splitting. In doping, the first shaped electrodes 116 to 118 are used as masks to form one conductivity type impurity regions 123 to 126 of the first concentration in the semiconductor films 104 to 107. The first concentration is equal to 1 x 10 ¹⁷ to 1 x 10 ¹⁹ atoms / cm ³ .

The second etching process, which does not remove the resist masks 111 to 114, is performed as shown in Fig. 2A. In this etching process, anisotropic etching is performed to the 2nd conductive film, and the 2nd shape electrode 127-129 and the 2nd shape wiring 130 and 131 are formed. The regions of the second insulating film not covered with the second shaped electrodes 127 to 129 and the second shaped wirings 130 and 131 are etched to become thin by 20 to 50 nm.

Thereafter, the mask 133 covering the entire semiconductor film 104, the mask 134 covering the second shape electrode 129 positioned in the semiconductor film 106, and the mask 134 covering the semiconductor film 107. ) Is formed to execute the second doping process. Through the second doping treatment, one conductive impurity region of the second concentration is formed in the semiconductor film 105, and one conductive impurity region of the third concentration is formed in the semiconductor films 105 and 106.

The one conductivity type impurity region 135 of the second concentration is formed in a self-aligning manner at a position overlapping with the first conductive film 128a constituting the second shape electrode 128. Impurities given by ion doping are transferred through the first conductive film 128a before the semiconductor film is doped. Therefore, the number of ions reaching the semiconductor film is reduced such that the concentration in the region 135 is lower than in the n-type impurity region of the third concentration. The impurity concentration of the region 135 is 1 x 10 ¹⁶ to 1 x 10 ¹⁷ atoms / cm ³ . The impurity regions 136 and 137 of the third concentration are doped with n-type impurities at concentrations of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Next, as shown in Fig. 3A, a resist mask 138 is formed to perform a third doping process. In the semiconductor film 104, the impurity region 139 of the fourth concentration of another conductivity type (conductive type opposite to one conductivity type) and the impurity region 140 of the fifth concentration of another conductivity type are formed through the third doping process. Is formed. An impurity region of another conductivity type fourth impurity region is formed in a region overlapping with the second shape electrode 127 and doped with an impurity element at a concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . This impurity concentration allows the region to operate with LDD. The impurity region 140 of the fifth concentration is doped with an impurity element at a concentration of 2 × 10 ²⁰ to 3 × 10 ²¹ atoms / cm ³ .

Through the above steps, regions doped with impurities are formed in each semiconductor film for the purpose of controlling valence electrons. The second shaped electrodes 127 to 129 act as gate electrodes. The second shape of the wiring 130 operates as one of the electrodes constituting the storage capacitor in the pixel portion. The second shape wiring 131 forms a data line in the pixel portion.

Next, the third insulating film 143 is formed by plasma CVD or sputtering. The third insulating film 143 is a silicon oxynitride film, a silicon oxide film, or the like.

Then, the impurity element doped with the semiconductor film is activated as shown in Fig. 3B. This activation step is carried out using furnace annealing or rapid thermal annealing (RTA). The heat treatment is carried out in a nitrogen atmosphere at a temperature of 400 to 700 ° C, typically 450 to 500 ° C. Instead, laser annealing using the second harmonic (532 nm) of the YAG laser can be used. The semiconductor film is irradiated with the second harmonic (532 nm) of the YAG laser to activate the impurity element. The activation method is not limited to laser light irradiation, and an RTA using a lamp light source to heat the semiconductor film by irradiating a lamp light source to both or one side of the substrate may be used.

As shown in Fig. 4, a fourth insulating film 144 made of silicon nitride is then formed by plasma CVD to have a thickness of 50 to 100 nm. The heat treatment at 410 ° C. is performed in a clean oven to hydrogenate the semiconductor film with hydrogen released from the silicon nitride film.

Next, a fifth insulating film 145 made of an organic insulating material is formed in the fourth insulating film 144. The organic insulating material is used to level the outermost surface of the fifth insulating film. Subsequently, a contact hole penetrating the third to fifth insulating films is formed by an etching process. In this etching process, the area | region of the 3rd-5th insulating film located in the external input terminal part is removed. The tantalum film and the aluminum film are layered to form the wirings 146 to 149, the pixel electrode 151, the scanning line 152, the connection electrode 150, and the wiring 153 connected to the external input terminal.

If one conductivity type is n type and the other conductivity type (as opposed to one conductivity type) is p type, the driving circuit 205 having the p-channel TFT 200 and the first n-channel TFT 201, A pixel portion 206 having a second n-channel TFT 203 and a capacitor portion 204 is formed on the same substrate through this step. The capacitor portion 204 is composed of the semiconductor film 107, the portion 122 of the second insulating film, and the capacitance wiring 130 of the first shape.

The p-channel TFT 200 of the driving circuit 205 has a p-type impurity region 140 having a fifth concentration located outside the channel forming region 154 and the second electrode 127 serving as the gate electrode (region ( 140 functions as a drain region or a source region), and a p-type impurity region LDD having a fourth concentration overlapping with the second electrode 127.

The first n-channel TFT 201 is a channel formation region 155, an n-type impurity region 124 (LDD) having a second concentration overlapping with the second shape electrode 128, which acts as a gate electrode, And an n-type impurity region 135 having a third concentration serving as a source region or a drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 mu m, preferably 1.5 mu m. This LDD structure is for preventing TFT degradation mainly caused by the hot carrier effect. The n-channel TFT and p-channel TFT can be used to form shift register circuits, buffer circuits, level shifter circuits, latch circuits, and the like. The structure of the first n-channel TFT 201 is particularly suitable for a buffer circuit having a high driving voltage since the degradation due to the hot carrier effect can be prevented.

The second n-channel TFT 203 of the pixel portion 206 is an n-type impurity region 125 having a first concentration formed outside the channel forming region 156 and the second shaped electrode 129 acting as a gate electrode. And an n-type impurity region 136 having a third concentration serving as a source region or a drain region. The p-type impurity regions 141 and 142 functioning as one of the electrodes of the capacitor portion 204 are formed in the semiconductor film 107.

The pixel portion 206 has a connection electrode 150 connecting the data line 131 to the pixel electrode 151 and the n-type impurity region 136 of the third concentration of the semiconductor film 106. The pixel portion also has a gate wiring 152 connected to a second shaped electrode 129 which functions as a gate electrode, although not shown in the figure.

As described above, the present invention is the same as the first n-channel TFT having one conductivity type impurity region including the LDD overlapping the gate electrode, and the second n-channel TFT in which the LDD does not overlap the gate electrode. Makes it possible to form on a substrate. Both types of TFTs are arranged separately in circuits of different operating conditions. For example, one TFT is arranged in the driver circuit portion and the other TFT is arranged in the pixel portion. In the p-channel TFT, the LDD overlaps with the gate electrode.

The substrate formed in this embodiment mode having the driving circuit portion 205 and the pixel portion 206 is called an active matrix substrate for convenience. This active matrix substrate can be used to manufacture active matrix driven display devices. Since the active matrix substrate of this embodiment mode has pixel electrodes formed from light reflecting materials, a reflective liquid crystal display device can be made. Not only the liquid crystal display device but also the light emitting device in which the organic light emitting element is used in the pixel portion can be manufactured from the active matrix substrate.

Example mode 2

Another embodiment mode of the present invention is described with reference to FIGS. 7A to 10. Here, a method of simultaneously forming TFTs of the pixel portion and TFTs (n-channel TFT and p-channel TFT) of the driving circuit located near the pixel portion at the same time will be described in detail.

For the description of the substrate, the insulating film, the semiconductor film, and the conductive film in Embodiment Mode 1, the substrate 301, the first insulating films 302 and 303, the semiconductor films 304 to 307, and the second insulating film 308 of FIG. 7A are described. ), The first conductive film 309, and the second conductive film 310.

Masks 311 and 312 are formed in FIG. 7B. The mask 311 covers the driving circuit portion, and the mask 312 covers the pixel portion. With the mask covering the pixel and the driving circuit portion, the first conductive film and the second conductive film are etched by the first etching process to form the first shaped electrode 313 and the first shaped wirings 314 and 315 ( The electrode is composed of the first conductive film 313a and the second conductive film 313b, the wiring 314 is composed of the first conductive film 314a and the second conductive film 314b, and the wiring 315 is A first conductive film 315a and a second conductive film 315b). Next, the semiconductor films 306 and 307 are doped with an impurity element of one conductivity type in the first doping process to form impurity regions 316 and 360 of one conductivity type at the first concentration.

The masks 311 and 312 are removed, and then a mask 317 covering the first shaped electrode 313 and the first shaped wirings 314 and 315 is formed as shown in FIG. 8A. In addition, the masks 318 to 320 are formed in the driving circuit portion to form the electrodes 321 to 323 of the first shape in the driving circuit portion through the second etching process.

Both the first etching process and the second etching process are for etching the first conductive film and the second conductive film, and form a tapered portion around the edge at an angle of 45 to 75 °.

The second etching process is followed by a third etching process as shown in Fig. 8B. The third etching process is for selectively etching the second conductive film to form the second shaped electrodes 324 to 326. The second shaped electrode has protrusions of the first conductive films 324a to 326a.

The second shaped electrodes 324 and 325 are used as masks in the second doping process using the film thickness difference between the first conductive films 324a and 325a and the second conductive films 324b and 325b. As a result, an impurity region of one conductivity type is formed in the semiconductor films 304 and 305. The one conductivity type impurity regions 330 and 331 of the second concentration are positioned to overlap with the electrode of the second shape, while the one conductivity type impurity regions 327 and 328 of the third concentration are outside the second shape electrode. Is formed in the area. An impurity region 329 of one conductivity type at a third concentration is formed in the semiconductor film 306.

Subsequently, masks 332 and 333 are formed as shown in FIG. 9A to dope the semiconductor film 304 with other conductivity type impurities through a third doping process. The resulting impurity regions are the impurity regions 335 of the fourth concentration of different conductivity type and the impurity regions 334 of the fifth concentration of another conductivity type. An impurity region 336 of a fifth conductivity type of another conductivity type is formed in the semiconductor film 307.

Then, a third insulating film 337 is formed, and the impurities used to dope the semiconductor film are activated similarly to the embodiment mode 1.

The fourth insulating film 338 is then formed as shown in FIG. 10, and heat treatment is performed at 410 ° C. to hydrogenate the semiconductor film. Next, a fifth insulating film 339 is formed on the fourth insulating film 338 with an organic insulating material. The organic insulating material is used to level the outermost surface of the fifth insulating film. Subsequently, contact holes penetrating the third to fifth insulating films are formed by etching. The wirings 340 to 343, the pixel electrode 345, the gate line 346, and the wirings 344 and 347 are formed.

If one conductivity type is n-type and the other conductivity type (as opposed to one conductivity type) is p-type, then the driving circuit 405 and the first circuit having the p-channel TFT 400 and the first n-channel TFT 401 are formed. A pixel portion 406 having an n-channel TFT 403 and a capacitor portion 404 of two is formed on the same substrate through this step. The capacitor portion 404 is composed of a semiconductor film 307, a part 361 of the first insulating film, and a capacitance wiring 314 of the first shape.

The p-channel TFT 400 of the driving circuit 405 is an impurity region 332 of a fourth conductivity type of another conductivity type positioned so as to overlap the channel forming region 348 and the second electrode 324 acting as a gate electrode. And an impurity region 333 of a fifth concentration of another conductivity type which is located outside the second electrode 324.

The first n-channel TFT 401 has a channel formation region 349 and an impurity region (LDD region) 331 having a second concentration overlapping with the electrode 325 having a second shape serving as a gate electrode. And an impurity region 328 of one conductivity type at a third concentration serving as a source region or a drain region. The LDD length in the channel length direction is 0.5 to 2.5 mu m, preferably 1.5 mu m. This LDD structure is for preventing TFT deterioration mainly caused by the hot carrier effect. The n-channel TFT and p-channel TFT can be used to form shift register circuits, buffer circuits, level shifter circuits, latch circuits, and the like. The structure of the first n-channel TFT 401 is particularly suitable for a buffer circuit having a high driving voltage since the degradation due to the hot carrier effect can be prevented.

The second n-channel TFT 403 of the pixel portion 406 is an impurity region of one conductivity type at a first concentration formed outside the channel formation region 350 and the first shape electrode 313 acting as a gate electrode. 316, and an impurity region 329 of one conductivity type at a third concentration acting as a source region or a drain region. In the semiconductor film 307, an impurity region 336 of another conductivity type, which functions as one of the electrodes of the capacitor portion 404, is formed.

As described above, the gate electrode of the driving circuit portion and the gate electrode of the pixel portion are configured differently in this embodiment mode to obtain TFTs having different LDD structures. The LDD overlapping with the gate electrode can be formed in a self-aligned manner with high accuracy without using a photo mask.

Example 1

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1A to 6. Here, a method of simultaneously forming TFTs of the pixel portion and TFTs (n-channel TFT and p-channel TFT) of the driving circuit located in the vicinity of the pixel portion at the same substrate will be described in detail.

In FIG. 1A, alumino borosilicate glass is used as the substrate 101. The first insulating film of this embodiment is a laminate of a first silicon oxynitride film 102 having a thickness of 50 nm and a second silicon oxynitride film 103 having a thickness of 100 nm. The film 102 is formed using SiH ₄ , NH ₃ , and N ₂ O as the reaction gas. The film 103 is formed using SiH ₄ and N ₂ O as the reaction gas.

The semiconductor films 104 to 107 are semiconductors having a crystal structure. The semiconductor film is obtained by forming an amorphous semiconductor film on the first insulating film and crystallizing the film through a known crystallization method. In this embodiment, the amorphous silicon film is formed by being deposited to have a thickness of 50 nm, and crystallized by irradiating excimer laser light collected by a linear beam by an optical system. The laser light is shaped to have a power density of 300 mJ / cm ² and shaped into a 500 μm linear beam to irradiate the entire surface of the amorphous silicon film at an overlap ratio of 90 to 98%.

Alternatively, a continuous wave YVO ₄ laser can be used. The laser is converted into second harmonics by a wavelength converting element, and an energy beam of 10 W is given to the film at a rate of 1 to 100 cm / sec to crystallize the amorphous film.

After crystallization, the semiconductor film is doped with boron, which is acceptor type, by ion doping to control the threshold voltage of the TFT. The doping concentration of the impurity can be appropriately set by the operator.

The polycrystalline silicon film thus obtained is divided into islands by etching to form the semiconductor films 104 to 107. A silicon oxynitride film having a thickness of 110 nm and formed by plasma CVD using SiH ₄ and N ₂ O is formed on the semiconductor film with the second insulating film 108.

The tantalum nitride film is formed as a first conductive film 109 on the second insulating film 108 by sputtering so as to have a thickness of 30 nm. Subsequently, a 300 nm thick tungsten film is formed of the second conductive film 110.

The thickness of the tantalum nitride film is determined in consideration of the doping efficiency of phosphorus used as the n-type impurity in ion doping (or the function of the tantalum nitride film to block phosphorus). FIG. 30 shows the phosphorus concentration distribution when the gate insulating film thickness is constant and the tantalum nitride film thickness varies from 15 nm to 45 nm. During doping, the acceleration voltage is set to 90 keV. The concentration of phosphorus injected into the semiconductor film varies depending on the thickness and material of the film (gate insulating film and tantalum nitride film) covering the semiconductor film. FIG. 31 shows the phosphorus concentration profile when the thickness of the tantalum nitride film is converted to the thickness of the gate insulating film. According to Fig. 31, the gate insulating film 2.4 to 2.66 times thicker is the same as the phosphorus blocking function of the tantalum nitride film. In other words, tantalum nitride exhibits a higher phosphorus blocking function even at smaller film thicknesses.

The thickness of the tantalum nitride film is determined in consideration of the resistance and the doping preventing function. It can be concluded from FIG. 30 and FIG. 31 that the optimum film thickness for the tantalum nitride film is between 15 nm and 300 nm.

Next, masks 111 to 114 are formed of the photosensitive resist material shown in Fig. 1B. Subsequently, a first etching process is performed on the first conductive film 109 and the second conductive film 110. The etching process uses inductively coupled plasma (ICP) etching. There is no limit to the choice of etching gas, but CF ₄ , Cl ₂ , and O ₂ are used to etch the W film and the tantalum nitride film. Its gas flow ratio is set to 25:25:10 and is given 500 W RF (13.56 MHz) power to the coil electrode at a pressure of 1 Pa for etching. In this case, the substrate side (sample stage) also receives 150 W of RF (13.56 MHz) power to apply a substantially negative self-bias voltage. Under such first etching conditions, the W film is mainly etched into a predetermined shape.

Thereafter, the etching gas is changed to CF ₄ and Cl ₂ . The gas flow ratio is set to 30:30, and 500 W RF (13.56 MHz) power is applied to the coil electrode at a pressure of 1 Pa to generate plasma during the 30 second etching. The substrate side (sample stage) also receives 20 W RF (13.56 MHz) power to apply a substantially negative self-bias voltage. The mixed gas of CF ₄ and Cl ₂ etches the tantalum nitride film and the W film at about the same ratio. Thus, the first shaped electrodes 116 to 118 and the first shaped wirings 114 and 115 formed at an angle near the edge are formed. The electrodes are tapered at an angle of 45 to 75 degrees. In order to etch the film without leaving residue in the second insulating film, the etching time is preferably extended by 10 to 20%. The region of the second insulating film 122 which is not covered with the first shaped electrodes 116 to 118 and the first shaped wirings 114 and 115 is etched to become thin by 20 to 50 nm.

The first doping treatment uses ion doping in which ions are implanted without mass separation. During doping, the first shaped electrodes 116 to 118 are used as masks, and hydrogen phosphide (PH ₃ ) gas diluted with hydrogen or hydrogen phosphide gas diluted with noble gas is applied to the semiconductor films 104 to 107. Is used to form the n-type impurity regions 123 to 126 of the first concentration. The n-type impurity regions of the first concentration formed in this doping have phosphorus concentrations of 1 x 10 ¹⁷ to 1 x 10 ¹⁹ atoms / cm ³ , respectively.

Without removing the masks 111 to 114, a second etching process is performed next, as shown in Fig. 2A. CF ₄ , Cl ₂ , and O ₂ are used as the etching gas, the gas flow ratio is set to 20:20:20, and an RF (13.56 MHz) power of 500 W is given to the coil electrode at a pressure of 1 Pa to provide etching. Generate plasma. The substrate side (sample stage) also receives 20 W of RF (13.56 MHz) power to apply a lower self-bias voltage than in the first etching process. Under such etching conditions, the W film used as the second conductive film is etched. Anisotropic etching is applied to the W film to form the second shaped electrodes 127 to 129 and the second shaped wirings 130 and 131. The regions of the second insulating film not covered with the second shaped electrodes 127 to 129 and the second shaped wirings 130 and 131 are etched to become thin by 20 to 50 nm.

Next, the mask 133 covering the entire semiconductor film 104, the mask 134 covering the second shape electrode 129 positioned in the semiconductor film 106, and the semiconductor film 107 for the second doping process. A mask 134 covering the gap is formed. Through the second doping process, an n-type impurity region having a second concentration is formed in the semiconductor film 105, and an n-type impurity region having a third concentration is formed in the semiconductor films 105 and 106. In this ion doping, phosphorus is used, the dose is set to 1.5 x 10 ¹⁴ atoms / cm ³ , and the acceleration voltage is set to 100 keV.

The n-type impurity region 135 having the second concentration is formed in a self-aligning manner at a position overlapping with the first conductive film 128a constituting the second shape electrode 128. Impurities given by ion doping are transferred through the first conductive film 128a before the semiconductor film is doped. Therefore, the second concentration is much lower than the impurity concentration in the n-type impurity region of the third concentration. The impurity concentration of the region 135 is 1 x 10 ¹⁶ to 1 x 10 ¹⁷ atoms / cm ³ . The impurity regions 136 and 137 of the third concentration are doped with phosphorus to achieve a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Next, a mask 138 is formed to perform the third doping process as shown in Fig. 3A. During doping, diborane B ₂ H ₆ gas diluted with hydrogen or diborane gas diluted with noble gas is added to the p-type impurity region 139 and the fourth concentration in the semiconductor film 104. It is used to form the p-type impurity region 140 of 5 concentrations. The p-type impurity region of the fourth concentration is positioned to overlap with the electrode of the second shape 127, and is doped with boron at a concentration of 1 x 10 ¹⁸ to 1 x 10 ²⁰ atoms / cm ³ . The impurity region 140 of the fifth concentration is doped with boron at a concentration of 2 × 10 ²⁰ to 3 × 10 ²¹ atoms / cm ³ . The p-type impurity region 142 of the fifth concentration and the p-type impurity region 141 of the fourth concentration are formed in part of the semiconductor film 107 used to form the storage capacitor in the pixel portion.

Through this step, a region doped with phosphorus or a region doped with boron is given to each of the semiconductor films. The second shaped electrodes 127 to 129 act as gate electrodes. The second shape wiring 130 forms one of the electrodes constituting the storage capacitor in the pixel portion. The second shape wiring 131 operates as a data line in the pixel portion.

Next, a silicon oxynitride film is formed of the third insulating film 143 by plasma CVD with a thickness of 50 nm. The impurity element used to dope the semiconductor film is activated by irradiating the semiconductor film with the laser light of the second harmonic (532 nm) of the YAG laser as shown in Fig. 3B.

As shown in Fig. 4, the fourth insulating film 144 is formed of silicon nitride by plasma CVD with a thickness of 50 nm. In order to hydrogenate the semiconductor film with hydrogen released from the silicon nitride film, heat treatment is performed at 410 ° C. in a clean oven.

Next, the fifth insulating film 145 is made of acrylic on the fourth insulating film 144. Subsequently, a contact hole is formed. In this etching process, the third to fifth insulating films located at the external input terminal portion are removed. The tantalum film and the aluminum film are stacked to form the wirings 146 to 149, the pixel electrode 151, the scanning line 152, the connection electrode 150, and the wiring 153 connected to the external input terminal.

Thus, with the driving circuit 205 having the p-channel TFT 200 and the first n-channel TFT 201 and the second n-channel TFT 203 and the capacitor portion 204 on the same substrate. Pixel portion 206 is formed. The capacitor portion 204 is composed of a semiconductor film 107, a part of the second insulating film 122, and a capacitance wiring 130 of a first shape.

The p-channel TFT 200 of the driving circuit 205 has a p-type impurity region 140 having a fifth concentration located outside the channel forming region 154 and the second electrode 127 serving as the gate electrode (region ( 140 serves as a source region or a drain region), and a p-type impurity region having a fourth concentration overlapping with the second electrode 127.

The first n-channel TFT 201 is a channel forming region 155, an n-type impurity region 124 (LDD) having a second concentration overlapping with the second shape electrode 128 serving as a gate electrode, and An n-type impurity region 135 having a third concentration serving as a source region or a drain region is provided. The LDD length in the channel length direction is 0.5 to 2.5 mu m, preferably 1.5 mu m. This LDD structure is for preventing TFT degradation mainly caused by the hot carrier effect. N-channel TFTs and p-channel TFTs are used to form shift register circuits, buffer circuits, level shifter circuits, latch circuits, and the like. The structure of the first n-channel TFT 201 is particularly suitable for a buffer circuit having a high driving voltage because it can prevent the degradation caused by the hot carrier effect.

The second n-channel TFT 203 of the pixel portion 206 is an n-type impurity region 125 having a first concentration formed outside the channel forming region 156 and the second shaped electrode 129 acting as a gate electrode. And an n-type impurity region 136 having a third concentration serving as a source region or a drain region. In the semiconductor film 107, p-type impurity regions 141 and 142 functioning as one of the electrodes of the capacitor portion 204 are formed.

The pixel portion 206 has a connection electrode 150 and a pixel electrode 151 connecting the data line 131 to the n-type impurity region 136 of the third concentration of the semiconductor film 106. The pixel portion also has a gate wiring 152 connected to a second shaped electrode 129 which functions as a gate electrode, although not shown in the figure.

A top view of the pixel portion 206 is shown in FIG. 5. The top view of FIG. 5 shows one dot substantially, and uses symbols common to that of FIG. 4. The cross-sectional structure taken along the line A-A 'in FIG. 5 corresponds to FIG. 4. In the pixel structure of FIG. 5, gate wirings and gate electrodes are formed on another layer so that the gate wiring overlaps with the semiconductor film and has an additional function as a light-shielding film. The edge of the pixel electrode is positioned to overlap with the source wiring to shield the gap between the pixel electrodes from light. This structure eliminates the need to form a light shielding film (black matrix). As a result, the aperture ratio is improved compared to the prior art.

As described above, the present invention makes it possible to form an n-channel TFT having an LDD overlapping with the gate electrode and an n-channel TFT having an LDD not overlapping with the gate electrode on the same substrate. The two types of TFTs are arranged separately in correspondence with circuits of different operating conditions. For example, one TFT is arranged in the driver circuit portion and the other TFT is arranged in the pixel portion. This is premised on the p-channel TFT having a single drain structure.

6 is a circuit block diagram illustrating an example of a circuit structure of an active matrix substrate. The substrate shown in Fig. 6 has a pixel portion 601 composed of TFTs, a data signal line driver circuit 602, and a scan signal line driver circuit 606.

The data signal line driver circuit 602 is composed of a shift register 603, latches 604, 605, buffer circuits, and other circuits. The clock signal and the start signal are input to the shift register 603. The digital data signal and the latch signal are input to the latch. The scan signal line driver circuit 606 also consists of a shift register, a buffer circuit, and other circuits. The pixel portion 601 can have any number of pixels. If the display device targets the XGA level, the pixel portion should have 1024 x 768 pixels.

Active matrix substrates can be used to fabricate active matrix driven display devices. Since the active matrix substrate of this embodiment has a pixel electrode formed of a light reflecting material, a reflective liquid crystal display device can be made. As well as the liquid crystal display device, the light emitting device in which the organic light emitting device is used in the pixel portion can be manufactured from the active matrix substrate. In this way, an active matrix substrate for a reflective display device is obtained.

Example 2

Another embodiment of the present invention is described with reference to FIGS. 7A to 10. This embodiment also provides a description of a method of simultaneously forming TFTs of a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driving circuit located near the pixel portion on the same substrate. The description of the substrate, the insulating film, the semiconductor film, and the conductive film in the first embodiment will be described with reference to the substrate 301, the first insulating films 302 and 303, the semiconductor films 304 to 307, and the second insulating film 308 of FIG. 7A. , First conductive film 309 and second conductive film 310.

In FIG. 7B, masks 311 and 312 are formed. The mask 311 covers the driving circuit portion, while the mask 312 covers the pixel portion. With a mask covering the pixel and the driving circuit, a first etching process is performed to form the first electrode 313 and the first wirings 314 and 315 (the electrodes are formed of the first conductive film 313a and the first electrode). 2 conductive film 313b, the wiring 314 is composed of the first conductive film 314a and the second conductive film 314b, and the wiring 315 is formed of the first conductive film 315a and the second conductive film. Film 315b). Etching conditions are the same as in the first etching treatment of the first embodiment. Next, the semiconductor films 306 and 307 are doped with phosphorus as an impurity in the first doping process by ion doping to form the n-type impurity regions 316 and 360 of the first concentration. The n-type impurity regions of the first concentration each have a phosphorus concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ .

The masks 311 and 312 are removed, and then a mask 317 covering the first shaped electrode 313 and the first shaped wirings 314 and 315 is formed as shown in FIG. 8A. In addition, the masks 318 to 320 are formed in the driving circuit portion to form the electrodes 321 to 323 of the first shape in the driving circuit portion through the second etching process. The second etching treatment is set to the same conditions as the first etching treatment conditions of this embodiment.

The second etching process is followed by the third etching process shown in Fig. 8B. The third etching treatment is for selectively etching the W film formed of the second conductive film. As a result, second-shaped electrodes 324 to 326 having protrusions of the first conductive films 324a to 326a are formed. The etching conditions in the third etching treatment are the same as the etching conditions in the second etching treatment of Example 1. FIG.

The second shaped electrodes 324 and 325 are used as masks in the second doping process, using the film thickness difference between the first conductive films 324a and 325a and the second conductive films 324b and 325b. As a result, the semiconductor films 304 and 305 are doped with phosphorus to form n-type impurity regions. The second doping treatment uses 5% PH ₃ diluted with hydrogen, sets the dose to 1.6 x 10 ¹⁴ atoms / cm ^3, and sets the acceleration voltage to 100 keV. This makes it possible to form the n-type impurity regions 330 and 331 of the second concentration and the n-type impurity regions 327 and 328 of the third concentration by one doping. The n-type impurity regions 330 and 331 of the second concentration are positioned to overlap the electrode of the first shape, and have a phosphorus concentration of 1 x 10 ¹⁶ to 1 x 10 ¹⁷ atoms / cm ³ due to the presence of the first conductive film. The n-type impurity regions 327 and 328 of the third concentration are formed in the outer regions of the electrodes of the second shape, and have a phosphorus concentration of 1 x 10 ²⁰ to 1 x 10 ²¹ atoms / cm ³ . An n-type impurity region 329 having a third concentration is formed in the semiconductor film 306.

Thereafter, masks 332 and 333 are formed as shown in FIG. 9A to dope the semiconductor film 304 with boron through a third doping process. The resulting impurity regions are the p-type impurity region 335 at the fourth concentration and the p-type impurity region 334 at the fifth concentration. The p-type impurity region 336 of the fifth concentration is formed in the semiconductor film 307.

The steps that follow are the same as those of Example 1. A third insulating film 337 is formed, and the impurities used to dope the semiconductor film are activated. Subsequently, a fourth insulating film 338 is formed as shown in FIG. 10, and heat treatment is performed at 410 ° C. to hydrogenate the semiconductor film. Next, a fifth insulating film 339 is formed on the fourth insulating film 338 with an organic insulating material. Subsequently, a contact hole is formed by an etching process. The wirings 340 to 343, the pixel electrode 345, the gate line 346, and the wirings 344 and 347 are formed.

Thus, the pixel portion 406 having the driver circuit 405 having the p-channel TFT 400 and the first n-channel TFT 401 and the second n-channel TFT 403 and the capacitor portion 404. ) Is formed on the same substrate. The capacitor portion 404 is composed of a semiconductor film 307, a part of the second insulating film 361, and a capacitance wiring 314 having a first shape.

The p-channel TFT 400 of the driving circuit 405 is an impurity region 332 of a fourth conductivity type of another conductivity type positioned so as to overlap the channel forming region 348 and the second electrode 324 acting as a gate electrode. And an impurity region 333 of a fifth concentration of another conductivity type which is located outside the second electrode 324.

The first n-channel TFT 401 has a channel formation region 349 and an impurity region (LDD region) of one conductivity type at a second concentration overlapping with the second shape electrode 325 serving as a gate electrode. ) And an impurity region 328 of one conductivity type at a third concentration functioning as a source region or a drain region. The LDD length in the channel length direction is 0.5 to 2.5 mu m, preferably 1.5 mu m. This LDD structure is for preventing TFT deterioration mainly caused by the hot carrier effect. N-channel TFTs and p-channel TFTs are used to form shift register circuits, buffer circuits, level shifter circuits, latch circuits, and the like. The structure of the first n-channel TFT 401 is particularly suitable for a buffer circuit having a high driving voltage because it can prevent the degradation due to the hot carrier effect.

The second n-channel TFT 403 of the pixel portion 406 is an impurity region of one conductivity type at a first concentration formed outside the channel formation region 350 and the first shape electrode 313 acting as a gate electrode. 316 and an impurity region 329 of one conductivity type at a third concentration functioning as a source region or a drain region. An impurity region 336 of a fifth conductivity type of another conductivity type is formed in the semiconductor film 307 functioning as one of the electrodes of the capacitor portion 404.

As described above, the gate electrode of the driving circuit portion and the gate electrode of the pixel portion are configured differently in this embodiment to obtain TFTs having different LDD structures. The LDD overlapping with the gate electrode can be formed in a self-aligned manner with high accuracy without using a photo mask. Thus, an active matrix substrate for the reflective display device is obtained.

Example 3

This embodiment describes the structure of an active matrix substrate for a transmissive display device with reference to FIGS. 11A and 11B. 11A and 11B show the structure of the pixel portion 406 in the active matrix substrate formed in Embodiment 2. FIG. The second n-channel TFT 403 and capacitor portion 404 are obtained according to the second embodiment.

FIG. 11A illustrates a contact hole formed after the fourth insulating film 338 and the fifth insulating film 339 and the transparent electrode 370 patterned to a predetermined shape in the fifth insulating film 339. The transparent conductive film 370 is 100 nm thick. Indium oxide, tin oxide, zinc oxide, or a compound of these oxides can be used to form the transparent conductive film. The transparent conductive film 371 is formed in the terminal portion.

Next, as shown in FIG. 11B, not only the electrodes 373 and 374 connected to the transparent electrode 370, but also the gate line 375 and the connecting electrode 372 are formed. The electrodes 373, 374, 372 and the line 375 are formed in a stack composed of a titanium film of 100 nm thickness and an aluminum film of 300 nm thickness. The active matrix substrate is configured as above to make a transmissive display device. The structure of this embodiment can be applied to the active matrix substrate of the first embodiment.

Example 4

This embodiment describes a process of manufacturing an active matrix driving liquid crystal display device from the active matrix substrate obtained in Example 3. FIG. A description is given with reference to FIG. 12.

After the active matrix substrate in the state shown in Fig. 11B is obtained, an oriented film 383 is formed on the active matrix substrate, and rubbing treatment is performed. Although not shown in the drawings, a columnar spacer may be formed at a desired position by patterning an organic resin film such as an acrylic resin film before the directional film 383. The spacer is for maintaining the distance between the substrates. Instead of columnar spacers, circular spacers may be given over the entire surface of the substrate.

Next, a counter electrode 381 is formed on the counter substrate 380, a directional film 382 is formed on the electrode, and polishing is performed. The counter electrode 381 is formed of ITO. The opposing substrate is then bonded using a sealing agent (not shown) to the active matrix substrate on which the pixel portion and the driving circuit are formed. The encapsulant has a filler mixed therein, and the filler maintains a distance between the two substrates while being bonded with the space. Liquid crystal material 385 is then injected between the substrates, and an end-sealing agent is used to fully seal the substrate. As the material 385, a known liquid crystal material can be used.

Thus, the active matrix drive liquid crystal display device shown in FIG. 12 is completed. In the example shown here, the transmissive active matrix substrate prepared in Example 3 is used, but the reflective active matrix substrate prepared in Examples 1 or 2 can also make a liquid crystal display device.

Example 5

Fig. 13 shows a structural example of a pixel portion in a light emitting device of an active matrix driving method to which the present invention is applied. The n-channel TFT 203 and the p-channel TFT 200 of the pixel portion 450 are manufactured according to the processing of the first embodiment. The surface of the fifth insulating film 501 is densified by plasma treatment using nitrogen or an inert gas. Typically, argon plasma treatment is used and the compactness is achieved by forming a very thin film mainly on the surface, which contains carbon. Then, contact holes are formed to form wiring. Titanium, aluminum, etc. are used as wiring.

In the pixel portion 450, the data line 502 is connected to the source side of the n-channel TFT 203, and the wiring 503 on the drain side is connected to the gate electrode of the n-channel TFT 203. The source side of the p-channel TFT 200 is connected to the power supply wiring 505 while the electrode 504 on the drain side is connected to the anode of the light emitting element 451.

The light emitting device in this embodiment has an organic light emitting device arranged to form a matrix. The organic light emitting device 451 is comprised of an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The anode 506 is formed from ITO after the wiring is formed. The organic compound layer includes a hole transport material with higher hole mobility, an electron transport material with higher electron mobility, a light emitting material, and a combination of others. These materials are formed in layers or mixed into one.

The organic compound materials all make thin films of about 100 nm. Therefore, the surface of the ITO film for forming the anode should be well leveled. If the surface is worst badly leveled, this may cause a short circuit with the cathode formed in the organic compound layer. The short circuit can be prevented by other measurements, ie by forming an insulating layer 508 1-5 nm thick. The insulating layer 508 is formed of polyimide, polyimideamide, polyamide, acrylic, or the like.

The cathode 510 is formed of an alkali metal such as MgAg or LiF or an alkaline earth metal. Details of the structure of the organic compound layer 509 may be freely set.

The organic compound layer 509 and cathode 510 may not accept wet treatment (chemical etching, cleaning, or similar other treatment). Therefore, a partition wall layer 507 is formed of the photosensitive resin material in the organic insulating film 501 at the boundary of the anode 506. The edge of the anode 506 is covered with the partition wall layer 507. In particular, a negative resist is applied and heated to provide a partition wall layer 507 1 to 2 μm thick. Alternatively, the dividing wall layer is formed of photosensitive acrylic or photosensitive polyimide.

As the cathode 510, a material containing magnesium (Mg), lithium (Li), or calcium (Ca) having a low work function is used. Preferably, the electrode is formed of MgAg (a material obtained by mixing Mg and Ag in a ratio of Mg: Ag: 10: 1). Examples of other electrodes usable as cathode 510 include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes. In the cathode, the insulating film 511, which is a silicon nitride film or DLC film, is formed to have a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film may be formed by plasma CVD and may well cover the edge of the partition wall layer 507 even when formed at 100 ° C. or lower. The internal stress of the DLC film can be relaxed by mixing a small amount of argon, thus allowing the film to act as a protective film. The DLC film is an excellent gas barrier not only for oxygen but also for CO, CO ₂ , and H ₂ O, and thus is suitable for the insulating film 51 used as the barrier film.

In Fig. 13, the n-channel TFT 203 used for switching has a multi-gate structure, while the p-channel TFT 200 used for current control has an LDD overlapping with the gate electrode. The present invention can form TFTs of different LDD structures by the same process. In the example shown in Fig. 13, the present invention is preferably applied to a light emitting device, in which TFTs having different LDD structures are formed in the pixel portion to serve different functions (n-channel TFTs having a low OFF current for switching) 203) and p-channel TFT 200 resistant to hot carrier injection for current control. As a result, a very reliable light emitting device (that is, a high performance light emitting device) having an excellent image display function can be obtained.

FIG. 14 is a diagram showing the structure of a light emitting device having the pixel portion 450 and the driving circuit portion 460 described above. The organic resin 511 is provided to the insulating film 511 formed in the pixel portion 450 to fill the space between the insulating film and the substrate 512. Thus, the device is sealed. Enhancing the sealability by providing a sealing member near the edge further improves. A flexible printed circuit (FPC) is attached to the terminal portion 453.

The perspective view of FIG. 15 is now used to describe the structure of the active matrix self-emissive device of this embodiment. The active matrix drive light emitting device of this embodiment has a pixel portion 602, a signal line drive circuit 603, and a data line drive circuit 604 on a glass substrate 601. The switching TFT 605 of the pixel portion is an n-channel TFT and is placed at the intersection of the gate wiring 606 and the source wiring 607. The gate wiring is connected to the gate side driving circuit 603 and the source wiring is connected to the source side driving circuit 604. The drain region of the switching TFT 605 is connected to the gate of the current control TFT 608.

The data line side of the current control TFT 608 is connected to the power supply line 609. In the structure of this embodiment, a ground electric potential (earth electric potential) is given to the power supply line 609. The drain region of the current control TFT 608 is connected to the organic light emitting device 610. A predetermined voltage (10 to 12 V in this embodiment) is applied to the cathode of the organic light emitting device 610.

The FPC 611, which operates as an external input / output terminal, includes input / output wiring (connecting wiring) 612 and 613 for transmitting signals to the driving circuit and input / output wiring 614 connected to the power supply line 609. Is provided. As described above, the TFT and the organic light emitting device are combined to constitute a pixel portion of the light emitting device.

Example 6

16A to 16E, an example of forming the semiconductor film used in the first or second embodiments will be described. The method described in FIGS. 16A-16E includes gettering after the entire surface of the semiconductor film having an amorphous structure is doped with a metal element having a catalytic function for crystallization.

In FIG. 16A, the substrate 701 is preferably, but not limited to, barium borosilicate glass, alumino borosilicate glass, or quartz. The first insulating film is formed on the surface of the substrate 701. The first insulating film was formed of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD at a thickness of 50 nm and SiH ₄ and N ₂ O by plasma CVD at a thickness of 100 nm. And a second silicon oxynitride film 703 formed. The first insulating film is provided to prevent the alkali metal contained in the glass substrate from being diffused into and formed on the semiconductor film. If quartz is used to form the substrate, the first insulating film can be omitted.

A semiconductor material mainly containing silicon is used as the semiconductor film 704 having an amorphous structure and formed in the first insulating film. Typically, the semiconductor film 704 is an amorphous silicon film or an amorphous silicon germanium film formed to a thickness of 10 to 100 nm by plasma CVD, reduced pressure CVD, or sputtering. In order to obtain satisfactory quality crystals, impurity concentrations such as oxygen and nitrogen contained in the semiconductor film 704 having an amorphous structure should be reduced to 5 x 10 ¹⁸ atoms / cm ³ or less. These impurities interfere with the crystallization of the amorphous semiconductor and, after crystallization, increase the density of trap centers and recombination centers. Therefore, it is desirable to use ultra-pure CVD apparatuses equipped with a mirror finish (field polishing treatment) reaction chamber and an oil-free vacuum exhaust system, as well as to use high purity material gases.

Next, the surface of the semiconductor film 704 having an amorphous structure is doped with a metal element having a catalytic effect of accelerating crystallization. Examples of metal elements having a catalytic effect of accelerating crystallization of the semiconductor film include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), Iridium (Ir), platinum (Pt), copper (Cu), and gold (Au). One or more kinds of metal elements selected from above may be used. Typically, nickel is selected and a nickel acetate solution comprising 1-100 ppm nickel by weight is applied to the spinner to form the catalyst-containing layer 705. In order to ensure that the solution is well applied, surface treatment is performed on the semiconductor film 704 having an amorphous structure. Surface treatment includes forming a very thin oxide film from an aqueous solution containing ozone, etching the oxide film with a mixture of hydrofluoric acid and aqueous hydrogen peroxide solution to form a clean surface, and again forming a very thin oxide film from a solution containing ozone. . Since the surface of a semiconductor film such as a silicon film is inherently weak in water, a nickel acetate solution can be uniformly applied by forming an oxide film in this manner.

The method of forming the catalyst-containing layer 705 is not limited thereto, and sputtering, evaporation, plasma treatment, or the like may be used instead. The catalyst-containing layer 705 may be formed before the semiconductor film 704 having an amorphous structure. In other words, it may be formed on the first insulating film.

While maintaining the semiconductor film 704 having an amorphous structure in contact with the catalyst-containing layer 705, heat treatment for crystallization is performed. Furnace annealing using an electric furnace, or high speed thermal annealing (hereinafter rapid thermal) using halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. annealing) is used for the heat treatment. In view of productivity, RTA is advantageous.

If RTA is selected, the lamp light source for heating is turned on for 1 to 60 seconds, preferably for 30 to 60 seconds, and repeated 1 to 10 times, preferably 2 to 6 times. The intensity of the light emitted from the lamp light source can be arbitrarily set as long as the semiconductor film is heated to reach 600 to 1000 ° C, preferably 650 to 750 ° C. When the temperature reaches its height, the semiconductor film is heated instantaneously and the substrate 700 is not deformed. Thus, the semiconductor film having the amorphous structure is crystallized to obtain the semiconductor film 706 having the crystal structure shown in Fig. 16B. Crystallization by this treatment takes place only when a catalyst-containing layer is provided.

If furnace annealing is used instead, heat treatment at 500 ° C. is performed for 1 hour, so that hydrogen contained in the semiconductor film 704 having an amorphous structure is released before the heat treatment for crystallization. Subsequently, the substrate receives heat treatment of the electric furnace in a nitrogen atmosphere at 550 to 600 ° C., preferably 580 ° C., for 4 hours to crystallize the semiconductor film. Thus, a semiconductor film 706 as shown in Fig. 16B having a crystal structure is formed.

It is effective to irradiate the laser light to the semiconductor film 706 having the crystal structure in order to increase the crystallization ratio (the ratio of the crystal component to the total volume of the film) and to protect the defects remaining in the crystal grains. Examples of laser light that can be used include excimer laser light having a wavelength of 400 nm or less and second or third harmonics of YAG laser. In any case, pulsed laser light having a repetition frequency of 10 to 1000 kHz is used, and 100 to 400 mJ / cm by the optical system to irradiate the semiconductor film 706 having the crystal structure at an overlap ratio of 90 to 95%. ^Are collected in ^two beams.

The semiconductor film 706 having the crystal structure obtained as described above has the remaining catalytic element (here, nickel). Although the catalyst elements are not evenly distributed in the membrane, the concentration is on average 1 x 10 ¹⁹ atoms / cm ³ or more. The semiconductor film in which the catalytic element remains can form a TFT and other semiconductor elements, but it is preferable to remove the remaining catalytic element by gettering according to the following method.

First, as shown in FIG. 16C, a thin barrier layer 707 is formed on the surface of a semiconductor film 706 having a crystal structure. The thickness of the barrier layer is not particularly limited. A simple way to obtain the barrier layer is to treat the surface with an aqueous ozone solution to form chemical oxides. Chemical oxides can also be formed when the aqueous hydrogen peroxide solution is treated with an aqueous solution mixed with sulfuric acid, hydrochloric acid, or nitric acid. Other available methods include plasma treatment in an oxidizing atmosphere and oxidation treatment with ozone generated through UV irradiation in an atmosphere containing oxygen. Alternatively, a thin oxide film formed by heating in a clean oven until 200 to 350 ° C. may be used as the barrier layer. An oxide film formed by plasma CVD, sputtering, or evaporation to a thickness of 1 to 5 nm may also be used as the barrier layer.

In the barrier layer, the semiconductor film 708 is formed to have a thickness of 25 to 250 nm. The semiconductor film 708 is an amorphous silicon film typically containing 0.01 to 20 atomic% argon formed by sputtering using argon. The semiconductor film 708 to be removed later is preferably a low density film in order to increase the selective ratio with respect to the semiconductor film 706 having a crystal structure in etching. When an amorphous silicon film is doped with a rare gas element and has a rare gas element therein, a gettering site is obtained.

One or more kinds of elements selected from the group consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used as rare gas elements. The present invention is characterized in that a rare gas element is used as an ion source to form a gettering site, and the rare gas element is injected into the semiconductor film by ion doping or ion implantation. There are two reasons for implanting ions of rare gas elements. One is to form a dangling bond by implantation so that the semiconductor film is distorted. The other is to distort by implanting ions into the lattice cells. Both objectives are accomplished by implanting ions of inert gas. In particular, the latter works well now when an element with a larger atomic radius than silicon is used, such as argon (Ar), krypton (Kr), or xenon (Xe).

To ensure that gettering is carried out thoroughly, heat treatment is required at this point. The heat treatment is done by furnace annealing or RTA. If furnace annealing is selected, the heat treatment is carried out in a nitrogen atmosphere at 450-600 ° C. for 0.5-12 hours. If RTA is selected, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and repeated 1 to 10 times, preferably 2 to 6 times. The intensity of light emitted from the lamp light source can be arbitrarily set as long as the semiconductor film is heated to reach 600 to 1000 ° C, preferably 700 to 750 ° C.

During gettering, the catalytic elements in the gettering region (trap site) are released by thermal energy and are transferred to the gettering site through diffusion. Thus, gettering relies on processing temperature and gettering processing at higher temperatures at shorter time periods. In Fig. 16E, the distance traveled by the catalytic element during gettering is approximately equal to the thickness of the semiconductor film, so that the gettering of the present invention is completed within a relatively short time period.

This heat treatment does not crystallize the semiconductor film 708 containing the rare gas element at a concentration of 1 × 10 ²⁰ atoms / cm ³ or more. This is assumed because the rare gas is not recharged in the above processing temperature range and the remaining elements interfere with the crystallization of the semiconductor film.

After the gettering step is finished, the amorphous semiconductor film 708 is removed by selective etching. Etching methods used may be dry etching with ClF ₃ without plasma, or wet etching with hydrazine or alkaline solutions such as aqueous solutions containing (CH ₃ ) ₄ NOH (tetraethyl ammonium hydroxide). have. Barrier layer 707 acts as an etch stopper at this point. Thereafter, the barrier layer 707 is removed using hydrofluoric acid.

In this way, a semiconductor film 710 having a crystal structure in which the concentration of the catalytic element is reduced to 1 x 10 ¹⁷ atoms / cm ³ or less is obtained as shown in Fig. 16E. The semiconductor film 710 having the crystal structure thus formed is in the form of a thin rod crystal or a thin and flat rod crystal due to the effect of the catalytic element. Macroscopically, each crystal grows with a specific orientation. The semiconductor film 710 formed according to the present embodiment to have a crystal structure may be applied to the semiconductor film of Example 1 or 2.

Example 7

17A to 17C, another method for gettering the catalytic element remaining in the semiconductor film 706 of Example 8 having a crystal structure will be described. A silicon oxide film is formed as a mask in the semiconductor film 706 having a crystal structure with a thickness of 150 nm. After the resist mask 712 is formed, the silicon oxide film is etched to obtain a mask insulating film 711. Subsequently, the rare gas element, the rare gas element and phosphorus, or phosphorus are implanted into the semiconductor film 706 having a crystal structure by ion doping to form the gettering site 713.

Then, as shown in Fig. 17B, heat treatment is performed in a nitrogen atmosphere of 450 to 600 DEG C for 0.5 to 12 hours by furnace annealing. Through this heat treatment, the catalytic element remaining in the semiconductor film 706 having the crystal structure is moved to the gettering site 713, where it is collected.

The mask insulating film 711 and the gettering site are then removed by etching to obtain a semiconductor film 710 having a crystal structure. The semiconductor film 710 formed according to the present embodiment to have a crystal structure may be applied to the semiconductor film of Example 1 or 2.

Example 8

As the first insulating film formed on the substrate 710 of the sixth embodiment, a silicon nitride film having a thickness of 1 to 10 nm may be used. The film is called the first insulating film 720. In Fig. 29, a first insulating film 720 is used, and a semiconductor film 706, a barrier layer 707, a semiconductor film 708, and a semiconductor film doped with a rare gas element having a crystal structure formed in accordance with the sixth embodiment. 709 is stacked to receive a heat treatment for gettering. Catalyst elements such as nickel are inherently surrounded by or surrounded by oxygen. Therefore, using the silicon nitride film as the first insulating film facilitates the movement of the catalytic element from the semiconductor film 706 having the crystal structure to the semiconductor film 708 or the semiconductor film 709 doped with the rare gas element.

Example 9

As liquid crystal television receivers have become more common and screen sizes have become larger, the wiring delay problem in data lines and gate lines can no longer be ignored. For example, the pixel structure shown in Embodiment 1 can provide a higher aperture ratio on the one hand, but on the other hand the screen size increases because the same material is used to form the data lines and gate electrodes. There is a need to address the problem of wiring delays.

When the display device has a pixel density of VGA level, there are 480 gate wiring and 640 source wiring, and in the case of XGA level, there are 768 gate wiring and 1024 source wiring. For the screen size of the display area, a 13 inch display measures 340 mm diagonally, but this is 460 mm for an 18 inch display. This embodiment provides a method of solving the delay problem and minimizing the area required for wiring in such a display device.

The TFT gate electrode of this embodiment is formed by stacking at least two types of conductive films as in Embodiment Mode 1 or Embodiment 1. Al and Cu are preferred as low resistance materials, and also have high conductivity. However, Al and Cu are weak against heat and corrosion and must be overcome to some extent.

In particular, a countermeasure is to use a metal nitrate material such as tantalum nitride and titanium nitride or a material having a high melting point such as Mo and W as a first conductive film in contact with the gate insulating film, and to prevent diffusion of Al and Cu. It includes the use of materials that can act as a barrier. The second conductive film is formed of Al or Cu, and the third conductive film is formed using Ti or W. This is to lower the contact resistance with the wiring formed on the conductive film and to protect Al or Cu which is easily oxidized.

18 shows an example in which a W film is used as a first conductive film, an Al film is used as a second conductive film, and a Ti film is used as a third conductive film to form a gate electrode, a data line, and a capacitance line. The driving circuit portion 205 and the pixel portion 206 are constructed according to the first embodiment.

In the first etching treatment, when an ICP etching apparatus is used, BCl ₃ , Cl ₂ , and O ₂ are used as etching gases, the flow ratio is set to 65:10:10, and the pressure is set to 1.2 Pa. High frequency power is applied to the substrate side to be biased to a substantially negative value. Under these conditions, the Al film is etched and the etching gas changes to CF ₄ , Cl ₂ , and O ₂ (flow ratio is set to 25:25:10) to etch the W film.

In the second etching treatment, BCl ₃ and Cl ₂ are used as the etching gas, the high frequency power is applied to the substrate side such that the flow ratio is set to 20:60 and biased to a substantially negative value. As a result, the Al film and the Ti film are selectively etched to form the second shaped electrodes 127 to 129 and the second shaped wirings 130 to 132 shown in FIG. 18 (the electrodes and the wiring are first conductive). Films 127e to 132e, second conductive films 127f to 132f, and third conductive films 127g to 132g).

In Fig. 18, the wiring resistance is sufficiently low by forming the data line 131 and the gate line from Al. Thus, the substrate can be applied to display devices having a pixel portion (screen size) of 4 inches or more. On the other hand, if the current density of the wiring is to be increased as in the power supply line of the light emitting device shown in Example 5, Cu is suitable for the wiring. Cu wiring is characterized by having a higher resistance to electrical movement than Al wiring.

Example 10

The first n-channel TFT shown in Examples 1 or 2 is doped with a semiconductor film acting as a channel forming region with an element (preferably phosphorus) or a group 13 element (preferably boron) belonging to group 15 in the periodic table. It may be an enhancement type TFT or a depression type TFT. When the n-channel TFTs are combined to constitute an NMOS circuit, the combination of the two enhancement TFTs provides the EEMOS circuit, and the combination of the enhancement TFT and the degradation TFT provides the EDMOS circuit.

An example of an EEMOS circuit is shown in FIG. 19A, and an example of an EDMOS circuit is shown in FIG. 19B. In Fig. 19A, (31, 32) both represent an enhanced n-channel TFT (hereinafter referred to as E NTFT). In Fig. 19B, reference numeral 33 denotes an E NTFT, and reference numeral 34 denotes a degradable n-channel TFT (hereinafter referred to as D NTFT). 19A and 19B, VDH represents a power supply line (positive power supply line) to which a positive voltage is applied, and VDL represents a power supply line (negative power supply line) to which a negative voltage is applied. The negative power supply line may be a power supply line (ground power supply line) of ground potential.

20A and 20B show examples of shift registers manufactured from the EEMOS circuit shown in FIG. 19A or from the EDMOS circuit shown in FIG. 19B. 20A and 20B, 40 and 41 represent flip-flop circuits. (42, 43) represents E NTFT. The gate of the E NTFT 42 receives the clock signal CL, and the gate of the E NTFT 43 receives the clock signal CL ⁻ having an inverted polarity. The inverter is represented by 44 and uses the EEMOS circuit shown in FIG. 19A or the EDMOS circuit shown in FIG. 19B, as shown in FIG. 20B. Thus, it is possible to use n-channel TFTs for all the TFTs in the driving circuit of the liquid crystal display device.

Example 11

This embodiment provides an example of a circuit structure for an active matrix drive display device. In the present embodiment, an example in which both the source side driving circuit and the gate side driving circuit are both composed of the E-type NTFT of the tenth embodiment will be described. The description is given with reference to FIGS. 21 through 23. This embodiment uses a decoder composed of n-channel TFTs instead of a shift register.

Fig. 24 shows an example of the gate side driving circuit. In Fig. 25, reference numeral 1000 denotes a decoder of the gate side driver circuit, and 1001 denotes a buffer unit of the gate side driver circuit. The buffer unit refers to a portion in which a plurality of buffers (buffer amplifiers) are integrated. A buffer is a circuit that is driven without affecting downstream from upstream.

First, the gate side decoder 1000 is described. An input signal line (referred to as a selection line) of the decoder 1000 is represented by 1002. Among lines 1002, here, lines A1, A ^- 1 (signals obtained by inverting the polarity of A1), A2, A ^- 2 (signals obtained by inverting the polarity of A2), ..., An, A ^- n ( Signal obtained by inverting the polarity of An) is shown. For simplicity, 2n selection lines are arranged. The number of selection lines is determined by the number of columns of gate wirings output from the gate side driver circuit. For example, if the display device has a pixel portion capable of VGA level display, since the number of gate wirings is 480, a selection line corresponding to 9 bits (n = 9), that is, 18 selection lines in total are required. Select line 1002 transfers the signal shown in the timing diagram of FIG. As shown in Figure 22, when a frequency of A1 is given by 1, a frequency of A2 is His times ^2-1, the frequency of A3 is his ^2-2 times, and a frequency of An is His 2 ^{- (n-1)} It is a ship.

Reference symbol 1003a denotes a first stage NAND circuit (also referred to as a NAND cell), 1003b denotes a second stage NAND circuit, and 1003c denotes an nth stage NAND circuit. The number of NAND circuits required corresponds to the number of gate wirings, and n NAND circuits are required here. Briefly, the decoder 1000 of the present invention is composed of a plurality of NAND circuits.

Each NAND circuit 1003a to 1003c has a combination of n-channel TFTs 1004 to 1009. In practice, 2n TFTs are used for each NAND circuit 1003. The n-channel TFTs 1004 to 1009 each have a gate connected to one of the selection lines 1002 (A1, A ^- 1, A2, A ^- 2, ..., An, A ^- n).

In the NAND circuit 1003a, the n-channel TFTs 1004 to 1006 each having a gate connected to one of the lines A1, A2, ..., An (these lines are called positive select lines) are in parallel with each other. And a negative power supply line (V _DL ) 1010 that is a common source and an output line 1011 that is a common drain. N-channel TFTs 1007 to 1009 each having a gate connected to one of lines A ^- 1, A ^- 2, ..., A ^- n (these lines are called negative select lines) are connected in series with each other N-channel TFT 1009 located at the end of the circuit has a source connected to the positive power supply line (V _DH ) 1012, while n-channel TFT 1007 located at the other end of the circuit. Has a drain connected to the output line 1011.

As described above, each NAND circuit of the present invention includes n n-channel TFTs connected in parallel with n n-channel TFTs connected in series. However, the combination of the n-channel TFT and the select line varies depending on the circuit in the n NAND circuits 1003a to 1003c. In other words, only one output line 1011 is selected at a time, and the selection line 1002 receives a signal starting at the end and selecting the output lines 1011 one by one.

The buffer unit 1001 is composed of a plurality of buffers 1013a to 1013c, respectively, in accordance with the NAND circuits 1003a to 1003c. The buffers 1013a to 1013c may all be configured in the same way.

Each buffer 1013a to 1013c is composed of n-channel TFTs 1014 to 1016. The output line 1011 from the decoder is input to the gate of the n-channel TFT 1014 (first n-channel TFT). The n-channel TFT 1014 uses a positive power supply line (V _DH ) 1017 as a source, and uses a gate wiring 1018 that reaches the pixel portion as a drain. The n-channel TFT 1015 (second n-channel TFT) uses a positive power supply line (V _DH ) 1017 as a gate and a negative power supply line (V _DL ) 1019 as a source. In addition, the gate wiring 1018 which always remains ON as a drain is used.

In other words, each buffer 1013a to 1013c of the present invention is connected in series with a first n-channel TFT (n-channel TFT 1014), and a first n-channel TFT, and is connected in series with the first n-channel TFT. A second n-channel TFT (n-channel TFT 1015) using the drain of the TFT as a gate is provided.

The n-channel TFT 1016 (third n-channel TFT) uses a reset signal line (Reset) as a gate, a negative power supply line (V _DL ) 1019 as a source, and a gate wiring as a drain. (1018) is used. The negative power line V _DL 1019 may be a ground power line GND.

The channel width of the n-channel TFT 1015 (W1) and the channel width of the n-channel TFT 1014 (W2) satisfy the relationship W1 <W2. The channel width refers to the length of the channel formation region in a direction perpendicular to the channel length.

The buffer 1013a operates as follows. First, while a negative voltage is applied to the output line 1011, the n-channel TFT 1014 is in the OFF state (the channel is not established). On the other hand, since the n-channel TFT 1015 is always in the ON state (the state in which the channel is established), the voltage of the negative power supply line 1019 is applied to the gate wiring 1018.

When a positive voltage is applied to the output line 1011, the n-channel TFT 1014 is turned on. At this time, the potential of the gate wiring 1018 is affected by the output of the n-channel TFT 1014 side because the channel width of the n-channel TFT 1014 is larger than the channel width of the n-channel TFT 1015. . As a result, the voltage of the positive power supply line 1017 is applied to the gate wiring 1018. Thus, the gate wiring 1018 outputs a positive voltage (a voltage for turning on the n-channel TFT used as the switching element of the pixel) when a positive voltage is applied to the output line 1011. On the other hand, when a negative voltage is applied to the output line 1011, the gate wiring 1018 always outputs a negative voltage (a voltage for turning off the n-channel TFT used as the switching element of the pixel).

The n-channel TFT 1016 is used as a reset switch for forcibly lowering the positive voltage applied to the gate wiring 1018 to a negative voltage. In particular, the n-channel TFT 1016 inputs a reset signal when the selection period of the gate wiring 1018 ends so that a negative voltage is applied to the gate wiring 1018. However, the n-channel TFT 1016 can be omitted.

The gate side driving circuit operating as described above selects the gate wirings one by one. Next, the structure of the source side driving circuit is shown in FIG. The source side driving circuit shown in FIG. 26 includes a decoder 1021, a latch 1022, and a buffer unit 1023. Since the structures of the decoder 1021 and the buffer unit 1023 are the same as those of the decoder and the buffer unit of the gate side driving circuit, the description thereof is omitted here.

In the case of the source side driving circuit of FIG. 23, the latch 1022 is composed of a first stage latch 1024 and a second stage latch 1025. The first stage latch 1024 and the second stage latch 1025 each have a plurality of basic units 1027 composed of m n-channel TFTs 1026a to 1026c. The output line 1028 from the decoder 1021 is input to the gates of the m n-channel TFTs 1026a to 1026c constituting each base unit 1027. The symbol m represents an arbitrary integer.

If the display device has a VGA level display function, for example, there are 640 source wires. When m = 1, the number of NAND circuits required is also 640, requiring 20 select lines (corresponding to 10 bits). When m = 8, the required NAND circuit is 80, and 14 select lines (corresponding to 7 bits) are required. Briefly, the number of NAND circuits required is M / m when the number of source wirings is M.

The sources of the n-channel TFTs 1026a to 1026c are connected to the video signal lines V1, V2, ..., Vk 1029, respectively. Therefore, when a positive voltage is applied to the output line 1028, the n-channel TFTs 1026a to 1026c are turned ON once, and a video signal associated with each TFT is input. The input video signal is retained in the capacitors 1030a to 1030c respectively connected to the n-channel TFTs 1026a to 1026c.

The second stage latch 1025 has a plurality of base units 1027b. Each basic unit 1027b is composed of m n-channel TFTs 1031a to 1031c. Since the gates of the n-channel TFTs 1031a to 1031c are all connected to the latch signal line 1032, the n-channel TFTs 1031a to 1031c are turned on once when a negative voltage is applied to the latch signal line 1032. .

As a result, the signal held at the capacitors 1030a to 1030c is now held by the capacitors 1033a to 1033c respectively connected to the n-channel TFTs 1031a to 1031c. At the same time, the signals held in the capacitors 1030a to 1030c are output to the buffer unit 1023. The signal is then output to the source wiring 1034 through the buffer as described in FIG. The source side driving circuits operating as described above select source wirings one by one.

As described above, the pixel portion and the driving circuit can be composed of both n-channel TFTs by making the gate-side driving circuit and the source-side driving circuit only with the n-channel TFT. The structure of this embodiment can be applied to the driving circuit of the active matrix substrate in the first or second embodiment.

Example 12

In this embodiment, a specific example of the circuit structure in the active matrix drive display device is described. In particular, this embodiment is a case where the p-channel TFT described in Embodiment 1 or 2 is used in the source side driver circuit and the gate side driver circuit. Decoder using p-channel TFT is replaced with a general shift register. 24 illustrates an example of the gate side driving circuit.

In Fig. 24, reference numeral 1200 denotes a decoder of the gate side driver circuit, and 1201 denotes a buffer section of the gate side driver circuit. Here, the buffer section refers to a portion in which a plurality of buffers (buffer amplifiers) are integrated. Also, a buffer refers to a circuit that can represent a drive function without providing the adverse effect of the stage following from the previous stage.

The gate side decoder 1200 is now described. Reference numeral 1202 denotes an input signal line (hereinafter referred to as a selection line) of the decoder 1200, and more specifically A1, A ^- 1 (signal having an inverted polarity with respect to A1), A2, A ^- 2 ( Signal with polarity reversed for A2), ..., An, and A ^- n (signal with polarity reversed for An). In other words, it can be considered that 2n select lines are arranged.

The number of selection lines is determined based on the number of gate wirings output from the gate side driving circuit. For example, if a pixel section for a VGA display is provided, 480 gate wires are required, requiring a total of 18 select lines to be provided for 9 bits (corresponding to the case where n = 9). Select line 1202 transmits the signals shown in the timing diagram of FIG. As shown in FIG. 25, assuming that the frequency of A1 is normalized to 1, the frequency of A2 may be represented by 2 ⁻¹ , the frequency of A3 may be represented by 2 ⁻² , and the frequency of An is 2. It may be represented ^by-(n-1) .

Reference numeral 1203a denotes a first stage NAND circuit (referred to as a NAND cell), and 1203b and 1203c denote NAND circuits of a second stage and an nth stage, respectively. The required number of NAND circuits is equal to the number of gate wirings, specifically n NAND circuits are required here. In other words, the decoder 1200 according to the present invention is composed of a plurality of NAND circuits.

In each NAND circuit 1203a to 1203c, p-channel TFTs 1204 to 1209 are combined to form a NAND circuit. In practice, 2n TFTs are used in each NAND circuit 1203. Moreover, the gate of each p-channel TFT 1204 to 1209 is connected to one of the selection lines 1202 (A1, A ^- 1, A2, A ^- 2, ..., An, A ^- n).

In this case, in the NAND circuit 1203a, the p-channel TFTs 1204 to 1206 each having a gate connected to any one of A1, A2, ..., An (referred to as positive selection lines) are parallel to each other. It is connected to the positive power supply wiring (V _DH ) 1210 which is also a common source, and is connected to the output line 1200 with a common drain. On the other hand, the remaining p-channel TFTs 1207 to 1209, each having a gate connected to any of A ^- 1, A ^- 2, ..., A ^- n (called a negative select line), are connected in series with each other. A source of the p-channel TFT 1209 located at one end of the circuit is connected to the negative power supply wiring (V _DL ) 1212 and a p-channel TFT (located at the other end of the circuit). The drain of 1207 is connected to the output line 1211.

As described above, the NAND circuit according to the present invention has n n TFTs of one conductive type (p-channel TFT in this case) connected in series and another n of one conductive type (p-channel TFT in this case) connected in parallel. Includes three TFTs. It should be noted that in the n NAND circuits 1203a to 1203c, all combinations between the p-channel TFT and the select line are different from each other. In other words, the output line 1211 is configured such that only one of them is selected, and a signal is input to the selection line 1202 such that the output line 1211 is sequentially selected from one side.

Subsequently, the buffer 1201 is composed of a plurality of buffers 1213a to 1213c to correspond to the NAND circuits 1203a to 1203c, respectively. Note that the buffers 1213a to 1213c may have the same structure.

Further, the buffers 1213a to 1213c are formed of p-channel TFTs 1214 to 1216 which are one conductivity type TFTs. The output line 1211 from the decoder is input to the gate of the corresponding p-channel TFT 1214 (the first TFT of one conductivity type). The p-channel TFT 1214 uses ground power source wiring (GND) 1217 as a source and a gate wiring 1218 as a drain. Further, the p-channel TFT 1215 (second conductive second TFT) uses a ground power source line 1217 as a gate and a positive power source line (V _DH ) 1219 as a source. The gate wiring 1218 which always maintains an ON state as a drain is used.

In other words, each of the buffers 1213a to 1213c according to the present invention includes a first conductive TFT (p-channel TFT 1214) of one conductivity type, and is also connected in series to the first TFT of one conductivity type. And a second conductive TFT (p-channel TFT 1215) that uses a gate of the first conductive TFT that is used as a drain.

Further, the p-channel TFT 1216 (third TFT of one conductivity type) uses a reset signal line Reset as a gate, a positive power source line 1219 as a source, and a gate wiring as a drain. (1218) is used. It should be noted that the ground power source line 1217 may be replaced with a negative power source line (a power source line for providing a voltage for causing the p-channel TFT used as the switching element of the pixel to be turned ON).

In this case, the channel width (represented by W1) of the p-channel TFT 1215 and the channel width (represented by W2) of the p-channel TFT 1214 satisfy the relationship of W1 <W2. The channel width refers to the length of the channel formation region measured in the direction perpendicular to the channel length.

The buffer 1213a operates as follows. During the time period in which a positive voltage is being applied to the output line 1211, the p-channel TFT 1214 is in an OFF state (i.e., that channel is not formed). On the other hand, since the p-channel TFT 1215 is always in the ON state (that is, the channel is formed), the voltage of the positive power source line 1219 is applied to the gate wiring 1218.

On the other hand, when a negative voltage is applied to the output line 1211, the p-channel TFT 1214 is turned ON. In this case, since the channel width of the p-channel TFT 1214 is wider than that of the p-channel TFT 1215, the potential of the gate wiring 1218 is attracted by the output on the side of the p-channel TFT 1214. Thus, the potential of the ground power source line 1217 is applied to the gate wiring 1218.

Thus, the gate wiring 1218 outputs a negative voltage when a negative voltage is being applied to the output line 1211 (which causes the p-channel TFT to be used as the switching element of the pixel to be in an ON state), and a positive voltage. When it is applied to this output line 1211, it always outputs a positive voltage (so that the p-channel TFT to be used as the switching element of the pixel is turned off).

The p-channel TFT 1216 is used as a reset switch for causing the gate wiring 1218 to which a negative voltage is applied to be pulled up to a positive voltage. That is, after the selection period of the gate wiring 1218 is completed, the reset signal is input so that a positive voltage is applied to the gate wiring 1218. It should be noted that the p-channel TFT 1216 can be omitted.

As the gate side driving circuit operating in the above-described manner, the gate wiring is selectively selected. At this time, the structure of the source side driving circuit is shown in FIG. The source side driving circuit as shown in FIG. 26 includes a decoder 1301, a latch 1302, and a buffer 1303. Since the decoder 1301 and the buffer 1303 each have the same structure as that of the gate side driver circuit, description thereof is omitted here.

In the case of the source side driving circuit shown in FIG. 25, the latch 1302 is composed of a first stage latch 1304 and a second stage latch 1305. Each of the first stage latch 1304 and the second stage latch 1305 includes a plurality of basic units 1307, which are each composed of m p-channel TFTs 1306a to 1306c. The output line 1308 from the decoder 1301 is input to each gate of the m p-channel TFTs 1306a to 1306c forming the base unit 1307. Note that the number m is any integer.

For example, for a VGA display, the number of source wires is 640. If m = 1, the number of NAND circuits required to be provided is also 640, and 20 select lines (corresponding to 10 bits) are required to be provided. However, on the other hand, when m = 8, the required number of NAND circuits is 80, and the required number of select lines is 14 (corresponding to 7 bits). That is, assuming that the number of source wirings is M, the number of required NAND circuits may be expressed in M / m.

The sources of the p-channel TFTs 1306a to 1306c are connected to the video signal lines V1, V2, ..., Vk 1309, respectively. That is, when a negative voltage is applied to the output line 1308, all of the p-channel TFTs 1306a to 1306c are turned on at the same time, so that the video signals are respectively directed to the corresponding p-channel TFTs 1306a to 1306c. Is taken. The video signal thus obtained is held in capacitors 1310a to 1310c connected thereto, respectively.

Moreover, the second stage latch 1305 also includes a plurality of basic units 1307b each composed of m p-channel TFTs 1311a to 1311c. Since all gates of the p-channel TFTs 1311a to 1311c are connected to the latch signal line 1312, when a negative voltage is applied to the latch signal line 1312, all the p-channel TFTs 1311a to 1311c are ON simultaneously. It becomes

As a result, the signals held in the capacitors 1310a through 1310c are held in the capacitors 1313a through 1313c connected to the p-channel TFTs 1311a through 1311c, respectively, and are simultaneously output to the buffer 1303. Subsequently, as described with reference to FIG. 24, these signals are output to the source wiring 1314 through the buffer. As the source side driving circuit operating in the above-described manner, the source wiring is sequentially selected.

As described above, by configuring the gate side driver circuit and the source side driver circuit with only the p-channel TFT, all the pixel sections and the driver circuit can be formed entirely of the p-channel TFT. Therefore, when manufacturing an active matrix type display device, the manufacturing yield and throughput of the TFT step can be significantly improved, thereby providing a reduced manufacturing cost. The structure of this embodiment can be applied to the driving circuit of the active matrix substrate in the first or second embodiment.

Example 13

Various semiconductor devices can be manufactured using the present invention. The following may be given as an example of such an electronic device: a video camera; digital camera; Goggle type display (head mounted display); Automotive navigation devices; Audio playback devices (such as automotive audio systems, audio compo systems); Laptop personal computer; Game equipment; Portable information terminals (such as mobile computers, mobile phones, mobile gaming equipment, or electronic books); And a video reproducing device provided with a recording medium. Examples of such semiconductor devices are shown in FIGS. 27 and 28.

27A illustrates a monitor, such as a desktop personal computer, and includes a frame 3301, a support table 3302, a display portion 3303, and the like. The display portion 3303 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. 8. Another integrated circuit can be formed by applying the TFT of the present invention. The monitor of a desktop personal computer can be completed using the present invention.

27B illustrates a video camera including a main body 3311, a display portion 3312, an audio input portion 3313, an operation switch 3314, a battery 3315, an image receiving portion 3316, and the like. The display portion 3312 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. 8. Another integrated circuit can be formed by applying the TFT of the present invention. Video cameras can be completed using the present invention.

27C shows a portion of the head-mounted display (right half) including the main body 3321, signal cable 3322, head mount band 3323, screen portion 3324, optical system 3325, display 3326, etc. Part). The display portion 3326 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. Another integrated circuit can be formed by applying the TFT of the present invention. Head-mounted displays can be completed using the present invention.

FIG. 27D illustrates a video reproducing apparatus (more specifically, a DVD reproducing apparatus) including a recording medium, which includes a main body 3331, a recording medium (DVD, etc.) 3332, an operation switch 3333, and a display portion ( a) 3334, another display portion (b) 3335, and the like. Display portion (a) 3334 is mainly used to display image information, and display portion (b) 3335 is mainly used to display character information. The display portions 3334 and 3335 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. Another integrated circuit can be formed by applying the TFT of the present invention. An image reproducing apparatus can be completed using the present invention.

27E illustrates a goggle display (head-mounted display) that includes a main body 3331, a display portion 3332, and an arm portion 3431. The display portion 3332 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. 8. Another integrated circuit can be formed by applying the TFT of the present invention. Goggle displays can be completed using the present invention.

27F illustrates a laptop personal computer that includes a main body 3331, a frame 3332, a display portion 3535, a keyboard 3354, and the like. The display portion 3353 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. Another integrated circuit can be formed by applying the TFT of the present invention. Laptop personal computers can be completed using the present invention.

FIG. 28A illustrates a portable telephone including a display panel 2701, an operation panel 2702, and a connecting portion 2703. The display panel 2701 is composed of a liquid crystal display device, a display device 2704 typical of the EL display device, a sound output portion 2705, and an antenna 2709. The operation panel 2702 includes an operation key 2706, a power switch 2702, and a sound input portion 2708. The display portion 2704 may be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. 8. Another integrated circuit can be formed by applying the TFT of the present invention. The portable telephone can be completed using the present invention.

28B also illustrates a sound reproduction device, specifically car audio equipment, which includes a main body 3411, a display portion 3412, and operation switches 3413 and 3414. The display portion 3412 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. 8. Another integrated circuit can be formed by applying the TFT of the present invention. The sound reproducing device can be completed using the present invention.

28C shows main body 3501, display portion (A) 3502, view finder portion 3503, operation switch 3504, display portion (B) 3505, and battery 3506. A digital camera will be described. The display portions 3502 and 3505 can be applied to the light emitting device shown in FIG. 9 or the active matrix drive liquid crystal display device shown in FIG. Another integrated circuit can be formed by applying the TFT of the present invention. Digital cameras can be completed using the present invention.

As described above, the present invention can be variously applied to a wide range of electronic devices in all fields. The electronic device of this embodiment may use any of the configurations shown in Embodiments 1 to 12. As described above, the present invention can form n-channel TFTs and p-channel TFTs of different LDD structures on the same substrate by the same processing. The obtained active matrix substrate can be used to manufacture a display device having a light emitting layer on the same substrate, or a liquid crystal display device.

By reducing the number of photo masks, productivity is improved. In addition, the present invention can simultaneously improve the reliability and performance characteristics of the active matrix substrate by optimizing the LDD structure of the n-channel TFT as described above.

Claims (10)

In a display device: A pixel portion and a gate driving circuit formed on an insulating surface, The pixel portion includes a first thin film transistor of one conductivity type, The gate driving circuit includes a decoder including a plurality of NAND circuits each including a plurality of second thin film transistors of the one conductivity type, At least two of the plurality of second thin film transistors of the one conductivity type are connected in series, At least two other of the plurality of second thin film transistors are connected in parallel to each other, Each of the first thin film transistor and the plurality of second thin film transistors, A semiconductor island comprising a source region, a drain region, and a channel region disposed between the source region and the drain region on the insulating surface; An insulating film on the semiconductor island; A first conductive film provided over the insulating film; And A second conductive film on the first conductive film, An edge of the first conductive film extends beyond an edge of the second conductive film, The first conductive film and the second conductive film have a tapered shape, The insulating film has a first portion covered with the first conductive film and a second portion not covered with the first conductive film, And the thickness of the second portion is thinner than the thickness of the first portion. In a display device: A pixel portion and a gate driving circuit formed on an insulating surface, The pixel portion includes a first thin film transistor of one conductivity type, The gate driving circuit includes a decoder including a plurality of NAND circuits each including a plurality of second thin film transistors of the one conductivity type, At least two of the plurality of second thin film transistors of the one conductivity type are connected in series, At least two other of the plurality of second thin film transistors are connected in parallel to each other, Each of the first thin film transistor and the plurality of second thin film transistors, A semiconductor island comprising a source region, a drain region, and a channel region disposed between the source region and the drain region on the insulating surface; An insulating film on the semiconductor island; A nitride film provided over the insulating film; And A conductive film on the nitride film, An edge of the nitride film extends beyond an edge of the conductive film, The nitride film and the conductive film have a tapered shape, The insulating film has a first portion covered with the nitride film and a second portion not covered with the nitride film, And the thickness of the second portion is thinner than the thickness of the first portion. In a display device: A pixel portion and a gate driving circuit formed on an insulating surface, The pixel portion includes a first thin film transistor of one conductivity type, The gate driving circuit includes a decoder including a plurality of NAND circuits each including a plurality of second thin film transistors of the one conductivity type, At least two of the plurality of second thin film transistors of the one conductivity type are connected in series, At least two other of the plurality of second thin film transistors are connected in parallel to each other, Each of the first thin film transistor and the plurality of second thin film transistors, A semiconductor island comprising a source region, a drain region, and a channel region disposed between the source region and the drain region on the insulating surface; An insulating film on the semiconductor island; A first conductive film provided over the insulating film; And A second conductive film on the first conductive film, An edge of the first conductive film extends beyond an edge of the second conductive film, The first conductive film and the second conductive film has a tapered shape, The insulating film has a first portion covered with the first conductive film and a second portion not covered with the first conductive film, The thickness of the second portion is thinner than the thickness of the first portion, The thickness of the second portion is thicker than the thickness of the semiconductor island, And the thickness of the semiconductor island is thicker than the first conductive film. In a display device: A pixel portion and a gate driving circuit formed on an insulating surface, The pixel portion includes a first thin film transistor of one conductivity type, The gate driving circuit includes a decoder including a plurality of NAND circuits each including a plurality of second thin film transistors of the one conductivity type, At least two of the plurality of second thin film transistors of the one conductivity type are connected in series, At least two other of the plurality of second thin film transistors are connected in parallel to each other, Each of the first thin film transistor and the plurality of second thin film transistors, A semiconductor island comprising a source region, a drain region, and a channel region disposed between the source region and the drain region on the insulating surface; An insulating film on the semiconductor island; A first conductive film provided over the insulating film; A second conductive film on the first conductive film; And A pixel electrode electrically connected to one of the source region and the drain region, An edge of the first conductive film extends beyond an edge of the second conductive film, The first conductive film and the second conductive film has a tapered shape, The insulating film has a first portion covered with the first conductive film and a second portion not covered with the first conductive film, And the thickness of the second portion is thinner than the thickness of the first portion. The method according to any one of claims 1 to 4, Wherein said one conductivity type is p-type. The method according to any one of claims 1 to 4, And said one conductivity type is n type. The method according to any one of claims 1, 3, or 4, And the first conductive film comprises TaN. The method according to any one of claims 1, 3, or 4, The thickness of the said 1st conductive film is a display device of 15 nm-300 nm. The method of claim 4, wherein And the pixel electrode comprises at least one material selected from the group consisting of indium oxide, tin oxide, and zinc oxide. delete

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