KR100907430B1 - Method of analyzing circuit model by reduction - Google Patents

Abstract

A circuit model reduction analysis method is described. The circuit model comprises at least an independent current source model, a resistance model and a capacitance model, and the circuit model also constitutes a single resistance / capacitance (RC) tree network including independent current sources. The circuit model reduction analysis method includes selecting a node to be removed using resistance connection information; And comparing the conductance of the capacitance for a given time step with the total conductance of the node. Moreover, the circuit model reduction analysis method removes selected nodes and maintains the RC element as an adjacent node that maintains the accuracy of the node voltage of the circuit reduced to the accuracy order used for the elementary perturbation of the corresponding circuit equation. And an independent current source. In addition, an efficient method for handling independent current sources during reduction is provided.

Circuit Reduction, Circuit Analysis, Circuit Models, Independent Current Source Models, Resistance Models, Capacitance Models, Tree Networks

Description

{Method of analyzing circuit model by reduction}

The present invention relates to a circuit model reduction analysis method, and more particularly, to a method for efficiently miniaturizing a circuit model including a large number of linear floating resistors, grounded capacitance, and a large number of independent current sources.

More specifically, the present invention compares the node voltage of the reduced circuit with the corresponding node voltage of the existing circuit before shrinking, satisfies the same relative accuracy, and reduces and reduces the circuit of the circuit including the RC tree network and the current source. By using an efficient method in the process, it is possible to effectively reduce the large-scale circuit with a large number of nodes, and to reduce the time required for analyzing the power noise of the chip, which is becoming increasingly serious, and to reduce the design time of the semiconductor chip. A circuit model reduction analysis method.

In recent years, there is an increasing demand for the design of high performance and low power consumption ultra large scale integrated circuits (VLSIs). High performance is achieved by technology scaling, increased functionality and competitive design. On the other hand, a common technique used to achieve low power designs is to reduce the supply voltage. This makes sense because the chip power P is proportional to the square of the supply voltage Vdd. Thus, the demand for high performance and low power consumption has made current VLSI designs to be characterized by reduced shape size, increased functionality and lower supply voltage.

Increasing chip functionality requires a large distribution network. On the other hand, lower supply voltages can cause chip failure, making the voltage changes across the distribution network very important. In order to provide the ideal supply voltage to each functional block in the chip, there must be no loss in the grid itself. However, the actual power grid is made up of many small parasitic RC elements that prevent the transfer of the ideal voltage value to the functional block. Voltage drop (IR-drop) is the voltage variation caused by this parasitic RC element. IR-drop analysis has become an indispensable step in the design verification of VLSI designs.

The interpretation of the IR-drop includes parasitic RC elements and functional blocks. However, it is not possible to simulate the circuit using a transistor-level simulator. Thus, the functional block is further modeled as an independent current source. However, because of the large size of the circuit, it is difficult to analyze the circuit modeled with the transistor-level simulator. Therefore, it is important to reduce the circuit before the circuit analysis.

Circuit model reduction analysis is to reduce the size of the circuit to reduce the complexity of analyzing large circuits. A good way is to reduce it to as small a circuit as possible while maintaining the given accuracy as possible. A feasible reduction analysis method is a reduction analysis method that derives a reduction circuit composed of RC elements with independent current sources.

The distribution network consists of an RC tree network with a number of independent current sources modeled as functional blocks. Previously, we have described circuit model reduction analysis for circuits with only RC elements. Moreover, there was no node selection method for error control during the shrinking of the circuit. Therefore, it is important to propose a new reduction analysis method that can handle circuits consisting of RC tree networks with multiple independent current sources that require sustained accuracy and high reduction ratios.

It is an object of the present invention to provide a method for efficiently reducing and analyzing a circuit model including a large RC float network composed of a large linear floating resistance, a grounded capacitance, and a large independent current source.

Another technical problem to be solved by the present invention is to compare the node voltage of the reduced circuit with the corresponding node voltage of the existing circuit before shrinking, satisfying the same relative accuracy, and generating the reduced and reduced circuit of the circuit including the RC tree network and the current source. By using an efficient method in this process, it is possible to effectively reduce the large-scale circuit with a large number of nodes, and to reduce the time required for analyzing the power noise of the chip, which is becoming increasingly serious, and to reduce the design time of the semiconductor chip. Another purpose is to provide an efficient circuit model reduction analysis method.

According to one aspect of the present invention, there is provided a circuit model reduction analysis method for achieving the above technical problem, comprising: inputting information on an original circuit configuration including a circuit net list having an independent current source and a node state; Selecting a node to be removed; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, inputting information about the original circuit configuration including the circuit net list having the independent current source and node status and the node to be removed. Preprocessing the circuit netlist with an independent current source between the selecting steps, wherein the preprocessing step further comprises preprocessing the circuit netlist for error control and a high reduction ratio. A circuit model reduction analysis method further comprises input processing of an RC net list having current source and node information.

According to another aspect of the present invention, there is provided a circuit model reduction analysis method for achieving the above-described technical problem, the method comprising: inputting information about an original circuit configuration including a circuit net list having independent current sources and node states; Selecting a node to be; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, inputting information about the original circuit configuration including the circuit net list having the independent current source and node status and the node to be removed. Preprocessing the circuit netlist with an independent current source between the selecting steps, wherein the preprocessing step further comprises preprocessing the circuit netlist for error control and a high reduction ratio. The circuit model reduction analysis method further comprises the calculation of the effective conductance of the capacitance with respect to the time step.

According to still another aspect of the present invention, there is provided a circuit model reduction analysis method for achieving the above-described technical problem, the method comprising: inputting information on an original circuit configuration including a circuit net list having independent current sources and node states; Selecting a node to be removed; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, inputting information about the original circuit configuration including the circuit net list having the independent current source and node status and the node to be removed. Preprocessing the circuit netlist with an independent current source between the selecting steps, wherein the preprocessing step further comprises preprocessing the circuit netlist for error control and a high reduction ratio. The circuit model reduction analysis method further comprises the calculation of the resistance of the node.

Preferably, the node selection step further comprises sorting the nodes in order of resistance.

Preferably, the node selection step further comprises determining removal of the node by comparing the inductance value of the capacitance with the sum of the inductances of the nodes.

Preferably, the node removing step further comprises generating a resistance between each node adjacent to the removed node.

Advantageously, removing said node further comprises generating grounded capacitance to each node adjacent to said removed node.

Preferably, the node removing step further comprises generating an independent current source to each node adjacent to the removed node.

As described above, the present invention provides a method for efficiently miniaturizing a circuit model comprising a large linear floating resistor, a grounded capacitance RC tree network, and a large number of independent current sources. In addition, the present invention compares the node voltage of the reduced circuit with the corresponding node voltage of the existing circuit before the reduction, satisfies the same relative accuracy, and in the process of reducing and reducing the circuit including the RC tree network and the current source. By using an efficient method, we can effectively reduce the large-scale circuit with a large number of nodes, and reduce the time required for analyzing the power noise of the chip, which is becoming more and more serious, and the semiconductor chip design time.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a method for reducing the circuit model according to an embodiment of the present invention, and a computer-readable medium.

Distribution in the VLSI circuit is performed from the top level metal layer of the entire distribution network 100. As shown in FIG. 1, the top level metal layer is brought down into the package through the interlayer vias 101 and finally to the active device 102. The metal wires 103 and vias 101 are modeled as linear, time invariant, and passive circuitry consisting of resistive, capacitive, and non-inductive elements. Networks for modern VLSI circuits, such as microprocessors, can typically include millions of nodes and tens of millions of electrical components. As for power and drain, their models can be quite complex. However, large size power grids make it inadequate to include anything other than the simplest model for power and drain. Therefore, the power supply is modeled as a simple constant voltage source, and the power drain is modeled as an independent time varying current source. Thus, as shown in FIG. 2, a given VLSI system is usually modeled as an RC tree network 200, and has an independently grounded current source (floating linear resistor 211, grounded linear capacitor 210, and logic gates). 213). The constant DC constant voltage source 212 can be converted into a constant ground resistance equivalent to a constant DC constant current source. In an embodiment, a PWL (PieceWise Linear) current source is used as an independent current source. The operation of the modeled system is represented by Equation 1 as a system of ordinary differential equations.

Where G is the conductance matrix, C is the diagonal capacitance matrix, x (t) is the node voltage, and u (t) is the independent current source. The differential system then converts to a linear algebra at each point in time using the backward Euler method with a time step "h" determined by the maximum frequency component.

이고

이다. x(t)에 대해서 수학식 2의 해를 구하는 경우 복잡도는 시스템의 차원과 함께 초선형적으로(super-linearly) 증가한다. 그래서, 해석을 실시하기 전에, RC 트리 네트워크의 크기를 축소하는 것이 중요하다. 수학식 2에서의 행렬 A를 다음의 수학식 3과 같이 확장시킬 수 있다.here,

ego

to be. When solving Equation 2 for x (t), the complexity increases super-linearly with the dimensions of the system. Therefore, before performing the analysis, it is important to reduce the size of the RC tree network. The matrix A in Equation 2 may be extended as in Equation 3 below.

Where matrix A is a symmetrical, diagonally dominant M-matrix. If node N is to show a node to be removed to reduce the circuit, the circuit equation (3) can be rewritten as shown in the following equation (4).

이다. 그 다음, 수학식의 축소된 시 스템은 다음 수학식 5와 같이 주어진다.here,

to be. Then, the reduced system of Equation is given by Equation 5 below.

이고

이다.here,

ego

to be.

와

는 노드 N이 제거될 때 발생하는

와

로부터

와

로의 변화를 각각 나타낸다고 하면, 상기 수학식 5로부터 This is called,

Wow

Occurs when node N is removed

Wow

from

Wow

Suppose that changes in are respectively represented by

와

는 다음 수학식 6과 수학식 7처럼 주어진다.

Wow

Is given by the following equations (6) and (7).

이다. 상기 수학식 6과 7은 C_N≠0이라면, 상응하는 축소된 수학식 시스템, 즉 수학식 5가 RC 트리 네트워크로서 실현될 수 없다는 것을 나타낸다. 그러나, 실제 회로의 대부분의 노드는 접지된 커패시턴스를 구비하고, 다수 응용예에서 감소되는 RC 트리 네트워크를 획득하는 것은 중요하 다. 그래서, C_N≠0 인 경우, 노드 N이 아래 수학식 8의 부등식을 만족시킨다면, 제안된 방법은

을 섭동시킴으로써 수학식 시스템을 실현 가능하게 한다. here,

to be. Equations 6 and 7 indicate that if C _N ≠ 0, the corresponding reduced equation system, i.e., equation 5, cannot be realized as an RC tree network. However, most nodes in an actual circuit have grounded capacitance, and in many applications it is important to obtain a reduced RC tree network. So, if C _N ≠ 0, if node N satisfies the inequality of Equation 8 below, the proposed method

By perturbing the equation system can be realized.

과 비교하여 만일

의 영향이 주어진 h에 대한 ε보다 크면, 수학식 8의 부등식이 만족되지 않는다. 수학식 8의 조건은 제안된 방법의 오차 해석을 위해 사용된다.In Equation 8, ε is the relative error range given by the user for node removal. If Equation 8 is not satisfied, the proposed method does not remove node N. Furthermore,

In comparison with

If the influence of is greater than ε for a given h, the inequality of Equation 8 is not satisfied. The condition of Equation 8 is used for the error analysis of the proposed method.

이 노드 N이 제거될 때 섭동된

을 나타낸다고 하면, 제안된 방법은

에 대하여 수학식 9를 사용한다. 이는 축소된 시스템이 차후 설명되는 바와 같이 실현되도록 한다.

Perturbed when this node N was removed

The proposed method

Equation 9 is used. This allows the reduced system to be realized as described later.

을

으로 치환하면 수학식 10을 얻게 된다.In equation (6)

of

Substituting by gives Equation 10.

라 할 때, 수학식 10의 시스템을 실현시키기 위하여, 수학식 10의 두번째 항을 제거함으로써 양의 커패시티브 성분을 제거할 필요가 있다. 섭동된

의

에 대하여 수학식 11을 얻을 수 있다.

In order to realize the system of Equation 10, it is necessary to remove the positive capacitive component by removing the second term of Equation 10. Perturbed

of

Equation 11 can be obtained for.

을

으로 치환하면

을 얻는다. 이 과정을 통하여 수학식 10으로부터 제거된 커패시티브 성분을

에 가산하여, 대각선 방향의 지배적인 부분을 가능한 많게 유지시킨다. 따라서,

는 다음 수학식 12와 같이 주어진다.In equation (7)

of

Substitute with

Get Through this process, the capacitive component removed from Equation 10

In addition, keep the dominant part in the diagonal direction as much as possible. therefore,

Is given by Equation 12 below.

이기 때문에, 상기 수학식 12는 수학식 13으로 재작성된다.About the RC Tree Network

Because of this, Equation 12 is rewritten as Equation 13.

이 부성 컨덕턴스 항인

을 포함할 때,

은

을 포함한다. 그래서

의

은

을 계산할 때 상쇄되어,

을 실현가능하게 한다. 마찬가지로, 노드 i에 다음 수학식 14와 같이 링크된 등가 전류원인 새로운

을 얻을 수 있다.

This paternal conductance

When including

silver

It includes. so

of

silver

Offset when calculating

Make it possible. Similarly, a new equivalent current source linked to node i as

Can be obtained.

은 또한 대각적으로 지배적인 M-행렬임을 관찰할 수 있으며, 따라서, 주어진 RC 트리 네트워크를 한 번 이상 반복하여 축소하는 것은 가능하다. 축소되는 회로의 노드 i의 전압은 수학식 15a에 의해 결정된다. 노드 전압의 상대 오차를 수학식 15b로 정의 한다.All nodes that satisfy Equation 8 can be removed together unless they are directly connected to one linear resistor. Finally, the circuit elements can be deduced by observing each term in equations (11), (13), and (14). Moreover, the matrix of reduction circuits

Can also be observed to be the diagonally dominant M-matrix, so it is possible to iteratively reduce a given RC tree network one or more times. The voltage at node i of the circuit to be reduced is determined by equation (15a). The relative error of the node voltage is defined by Equation 15b.

의 조사는

과

의 정확도의 심사를 요하게 된다. 대각선 지배 M행렬의 입력 방식의 섭동 이론은

에 대한

의 정확도가

에 대한

의 정확도와 동일한 차수로 주어짐을 알 수 있다.

의 정확도를 조사하기 위하여, 오프-대각선 항과 및 대각선 지배 부분을 조사할 필요가 있다.

에 대한

의 오프-대각선 항의 상대 오차는 다음 수학식 16으로 표시된다.

Investigation of

and

This will require a review of the accuracy. Perturbation theory of diagonally governing M matrix input method

For

The accuracy of

For

It can be seen that the order of magnitude equal to the accuracy of.

In order to investigate the accuracy of, it is necessary to examine the off-diagonal terms and the diagonal governing portion.

For

The relative error of the off-diagonal term of is expressed by the following equation.

Hereinafter, the relative error of the diagonal dominant portion is derived as in Equations 17a and 17b.

The relative error of the diagonal dominant portion is represented by equation (18).

에 대한

의 상대 오차는 ε에 의해 범위가 제한된다. 유사한 방법으로,

의 상대 오차는 ε보다 더 크지 않다고 쉽게 결론 지을 수 있다. 두 항의 곱의 상대 오차는 각 항의 상대 오차의 합이므로, 노드 전압의 상대 오차는 다음 수학식 19로 나타내어 진다.From the perturbation theory of the input method for the diagonally dominant M-matrix, in equations (16) and (18),

For

The relative error of is bounded by ε. In a similar way,

It can be easily concluded that the relative error of is not greater than ε. Since the relative error of the product of the two terms is the sum of the relative errors of each term, the relative error of the node voltage is represented by the following equation (19).

Equation 19 shows that the accuracy of the node voltage of the reduction circuit is determined by ε. From Equations 15b and 19, the following Equation 20 can be derived for the case where a given circuit is reduced more than once, where n is the number of repeated reductions.

For a small ε, the relative error range of the node voltage is given by Equation 21, which shows a linear increase in the relative error range with the number of repeated reductions.

Computer programs typically read out circuit models in the form of net lists. In this embodiment, the most widely used expressions are used for independent current sources and PWL current sources. A typical PWL current source includes several parameters to describe its behavior, such as initial delay, number of iterations, multiple time points and corresponding current values. However, the proposed invention uses symbol information and one relative current scaling factor value for the PWL current source during circuit reduction. This will significantly reduce the memory requirements for current source operation, which may cause problems if one circuit contains millions of current sources.

2 is a schematic diagram of a power grid model applied to the present invention. To indicate whether a node is left by the user, the node state of the circuit is needed. In certain embodiments, both nodes of some circuit elements may be configured as retained nodes. This circuit element does not belong to any kind of elements 210, 211, 212, and 213, and even if it belongs, occupies a very small part of the entire circuit.

4 is a flowchart of a node selection method 400 applied to the present invention. That is, FIG. 4 shows that some nodes can be removed and some nodes are non-removable nodes before applying the reduction method proposed in the present invention, and so that the relative error of the reduced circuit can be kept within a certain range while selecting a large number of nodes that can be removed. This is a flow chart. In FIG. 4, the first incoming information is the information and connection information of each element of the circuit and the state information of the nodes, that is, the nodes that must be predetermined by the user. And finally what we get is the removable nodes labeled "R" and the nodes to leave are the information labeled "K". All nodes in the circuit should proceed with this determination.

The nodes not belonging to the case mentioned in FIG. 2 among those shown in FIG. 4 are set as undefined nodes before performing the node selection procedure. All nodes that satisfy Equation 8 representing the removal range of step 402 of FIG. 4 may be removed together unless they are directly connected through one linear resistor.

First, as shown in step 401 of FIG. 4, the nodes will be sorted in order of resistivity to select as many nodes as possible for each reduction. Then, it is further confirmed whether the sorted node satisfies Equation (8). If it satisfies Equation 8, the node is marked as removed node " R ", and adjacent nodes are marked as retained node " K " as shown in step 402 of FIG.

Step 402 displays the process of determining each node and finally dividing it into a removal node and remaining nodes.

The first judging step 402A is a node left from the beginning by the user. If it is designated as "F", it is a node that is left as a matter of course.

The second judging step 402B determines if the neighboring nodes are marked as "R" in consideration of the case where the neighboring nodes are selected first if it is not marked as "F" in step 402A. In step 402B, if the node has already been selected as the node to be removed by the node selection process, that is, if the neighboring nodes are marked as "R", the node is left as the node to be left in step 402D because the rule is determined not to be removed at once. K ".

The third decision step 402C determines if the node is out of the error range when the node is finally removed if both conditions are not satisfied. This criterion is judged by the judgment step "Are the removal range satisfied?" Shown in the figure. If the removal range is satisfied in step 402C, it is marked as "R" in step 402E, and if not satisfied, it is marked with "K" in step 402D. Step 402C is associated with equation (8).

That is, in step 402, a simple process of marking a node "K" in step 402D and a node "R" is shown in step 402D.

In step 403, it is determined whether the process has been completed for all the nodes of the circuit. If it is the end number of the sorted nodes in advance, it can be easily determined that all the nodes have been performed. If the entire node has not proceeded, steps 401 and 402 are performed.

3 is a flowchart of a circuit model reduction analysis method 300 according to the present invention. In FIG. 3, step 301 is a part for explaining a process of reading data indicating an input circuit by a program and inputting a netlist and node state information. For example, if the information of the circuit before reduction is in the SPICE format, which is a general format for displaying a lot of information, it is necessary to convert the data of the circuit into data determined by the internal algorithm in order to apply the reduction algorithm. In addition to data reflecting the circuit's own characteristics, node state information is separately input in case the user wants to leave specific nodes when used for reduction purposes. For example, you can mark "K" for the node you want to leave and "U" for other removable nodes, so this information will be read in the initial circuit information input step.

Step 302 of FIG. 3 is a step of selecting nodes to be removed, and the equation corresponding to step 302 is associated with Equation 8 used as a criterion for determining whether the node is removable in the node selection process. After all nodes have been retrieved by the node selection procedure 302 of FIG. 3, the number of nodes to be removed is known. In a particular embodiment, the reduction ratio defined as the ratio between the number of nodes before and after the reduction will be selected as one of the termination (termination) conditions. That is, the reduction procedure is stopped if the reduction ratio is too high, which means that it can no longer be reduced (step 305). Otherwise, the removing step 303 removes the selected node and generates a reduction circuit.

Operation steps in the removal step 303 of FIG. 3 will be described in detail below.

Equation corresponding to step 303 is associated with equations (13) and (14) that determine the values of the device when removing the nodes selected as removal nodes in step 302 and generating equivalent circuit elements around the removal node. For each removed node, first remove the resistance between the removed node and the adjacent node. And also remove the grounded capacitor at the removed node. The resistors will then be created among the adjacent nodes whose resistance value is given by Eq. Then, a new grounded capacitor is added to the adjacent node given by Eq. If there is a current source attached to the removed node, the calculated current scaling factor value and symbol name of the current source are stored in each adjacent node. The calculated current scaling factor value is determined by equation (14). If a current source with the same symbol name already exists at one of the adjacent nodes, the calculation is added to the term with the same symbol name. After completing the reduction for all nodes marked as removed nodes, the reduced circuit can be reduced again. The same procedure will be applied to the reduction circuit over and over until the termination condition is met.

Step 304 of FIG. 3 is a step of updating node information, which is necessary to repeatedly apply the circuit model reduction analysis method according to the present invention. As a result of the previous step, the values of the removed and lost nodes, the remaining nodes, and the devices connecting each node change. Therefore, necessary information is updated to reduce the newly obtained reduction circuit.

As shown in step 305 of FIG. 3, if the reduction is no longer possible, or if the number of repetitions exceeds the value given by the user, the reduction procedure stops. The RC net list will be generated directly from the final result of the reduction in step 306. A network file such as SPICE will be created after the completion of the current source operation. The final obtained current source is calculated using the current source name information and relative scaling factor values included in the final current source obtained through the reduction process. This can be achieved by comparing several different current sources and calculating the value for the new current source from the information of the current source to obtain a PWL independent current source connected to each node of the reduction circuit.

FIG. 5 is a waveform diagram illustrating a process of generating a piecewise linear (PWL) current source of a reduction circuit according to the present invention. Based on this information, the number of current sources, or the number of nodes to which the current source is attached, and the scaling factors for the current source in the reduction phase before the first reduction in several iterative reduction phases. Current sources must be configured.

The current source waveform of FIG. 5 is a waveform diagram 500 of the current source of FIG. 2, which is an exemplary diagram illustrating a process of generating a current source of a reduction circuit according to the present invention in detail. Waveform 501 is a waveform diagram of a current source finally obtained. And waveforms 502, 503, and 504 represent the waveforms of the current source of the circuit before reduction, and the coefficients 2, 0.4, and 0.6 of the current equation shown on the left are scaling factors for the current sources associated with waveform 501 of the final reduction circuit. )to be. Since the PWL type current source is selected, the starting point, the end point, and the peak points of each configured current source are added together to form the starting point, the end point, and the peak points forming a new current source.

That is, after the reduction process, the nodes of the circuit after reduction are composed of current sources 502, 503, 504 representing symbol names and current scaling factor values. In the present invention, a new current value for each time point is obtained by adding the contribution from each current source. If the time point is the same as the time point of the new current source, the contribution from each current source is obtained directly. Otherwise, the contribution is obtained by linear interpolation within the period to which the time point belongs at the time point of the new current source. Through the above process, a new PWL current source 501 is finally generated. In FIG. 5, Equation 14 is used to determine a scaling factor value of an associated current source in a reduction process.

A computer program product is any machine readable medium, such as EPROM, ROM, RAM, DRAM, disk storage, or tape, that writes computer readable code thereon so that when the computer reads and executes it, Command to perform the functions. The computer includes a computer program product that is loading program code, because the computer incorporates DRAM and / or disk memory that is recording the code. Computers implementing the circuit model reduction analysis method of the present invention will generally also incorporate a program product. This is because while the circuit model reduction analysis method is being performed, the code for the circuit model reduction analysis method is typically present in the computer's memory.

An apparatus for performing the circuit model reduction analysis method according to the present invention includes a memory system. This memory system incorporates one or more levels of main memory, cache, and disk storage subsystems. The memory system records one circuit model and a series of system readable instructions for instructing the processor to perform the steps of the method of FIG. 3 on the circuit model as described so far. In a particular embodiment the memory system is the memory of the digital computer and the processor is the processor of the digital computer.

1 is a schematic diagram showing a portion of a distribution network of an integrated circuit applied to the present invention.

2 is a schematic diagram of a power grid model applied to the present invention.

3 is a flowchart of a circuit model reduction analysis method according to the present invention.

4 is a flowchart illustrating a node selection method applied to the present invention.

5 is a waveform diagram illustrating a generation process of a piecewise linear (PWL) current source of a reduction circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

100 ... Distribution Network 101 ... Interlayer Buyer

102.Active element 103 ... Metal wire

200 ... RC Tree Network 210 ... Ground Linear Capacitors

211 ... Floating linear resistor 212 ... DC constant voltage source

213 ... Independent ground current source

Claims (8)

In the circuit model reduction analysis method, Inputting information about the original circuit configuration, including a circuit net list having independent current sources and node states; Selecting a node to be removed; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, Preprocessing the circuit net list with the independent current source between inputting information about the original circuit configuration including the circuit net list with the independent current source and node status and selecting the node to be removed. Include, The preprocessing step further includes preprocessing the circuit netlist for error control and a high reduction ratio, wherein the preprocessing step further comprises input processing of an RC netlist with independent current source and node information. How to interpret. In the circuit model reduction analysis method, Inputting information about the original circuit configuration, including a circuit net list having independent current sources and node states; Selecting a node to be removed; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, Preprocessing the circuit net list with the independent current source between inputting information about the original circuit configuration including the circuit net list with the independent current source and node status and selecting the node to be removed. Include, The preprocessing step further comprises preprocessing the circuit netlist for error control and a high reduction ratio, wherein the preprocessing step further comprises the calculation of the effective conductance of the capacitance for a given time step. . In the circuit model reduction analysis method, Inputting information about the original circuit configuration, including a circuit net list having independent current sources and node states; Selecting a node to be removed; Removing the selected node and creating a reduction circuit; Post-processing the reduced circuit net list from the intermediate data of the reduced circuit, Preprocessing the circuit net list with the independent current source between inputting information about the original circuit configuration including the circuit net list with the independent current source and node status and selecting the node to be removed. Include, And the preprocessing step further comprises preprocessing the circuit netlist for error control and a high reduction ratio, wherein the preprocessing step further comprises calculating a resistance of the node in the circuit. 4. A method as claimed in any preceding claim wherein the node selection step further comprises sorting the nodes in order of resistance. 4. The circuit model of claim 1, wherein the node selection step further comprises determining removal of the node by comparing the inductance value of the capacitance with the sum of the inductances of the nodes. Collapse interpretation method. 4. The method of any one of claims 1 to 3, wherein said node removing step further comprises generating a resistance between each node adjacent to the removed node. 4. The method of any one of the preceding claims, wherein removing the node further comprises generating grounded capacitance to each node adjacent to the removed node. 4. The method of any one of the preceding claims, wherein removing the node further comprises generating an independent current source to each node adjacent to the removed node.

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