KR100780767B1 - Clock input circuit - Google Patents

Abstract

According to an aspect of the present invention, there is provided an electronic device including: a first clock buffer unit for differentially amplifying an external clock signal and a first reference voltage signal to generate a first clock signal; A second clock buffer unit configured to differentially amplify the external clock signal and the second reference voltage signal to generate a second clock signal; And a driver unit generating an internal clock signal in response to the first clock signal and the second clock signal.

Clock Input Circuit, Differential Amplification, Delay Time, Duty Cycle

Description

Clock input circuit

1 is a circuit diagram of a conventional clock input circuit.

2 is a circuit diagram of a clock input circuit according to an embodiment of the present invention.

3 is a diagram illustrating a delay time and a duty cycle of an internal clock signal with respect to an external clock signal.

4 is a diagram illustrating a delay time of an internal clock signal with respect to a first reference voltage signal in the present invention and the conventional clock input circuit.

5 is a diagram illustrating a duty cycle of an internal clock signal with respect to a first reference voltage signal in the present invention and the conventional clock input circuit.

<Description of the symbols for the main parts of the drawings>

10: first clock buffer unit 20: second clock buffer unit

30: reference voltage generator 40: push-pull driver

P1-P6: PMOS transistor N1-N6: NMOS transistor

I1-I3: Inverter

The present invention relates to a clock input circuit, and more particularly, to a clock input circuit for minimizing a delay time between an external clock signal and an internal clock signal and a duty cycle variation of the internal clock signal.

1 is a circuit diagram of a clock input circuit of a conventional semiconductor device. Referring to FIG. 1, a conventional clock input circuit includes a PMOS transistor P1 and P2 operating as a current mirror, and a differential input signal using a first reference voltage signal VREF and an external clock signal CLK provided to a gate, respectively. NMOS transistors N1 and N2 for generating a clock signal CLKN, an NMOS transistor N3 for enabling the NMOS transistors N1 and N2 in response to an enable signal EN, and the clock. An inverter I1 for inverting the signal CLKN and generating the internal clock signal iCLK is provided.

When the NMOS transistor N3 is turned on by the enable signal EN, the NMOS transistors N1 and N2 respectively have the voltage level of the reference voltage signal Vref provided to the gate and the external clock signal CLK. The clock signal CLKN is generated by amplifying the difference in voltage levels. The clock signal CLKN is inverted through the inverter I1 to generate an internal clock signal iCLK having a digital voltage level.

However, since the conventional clock input circuit includes only a differential amplifier composed of NMOS transistors, as shown in FIG. 4, the external clock signal CLK and the internal clock are increased as the voltage level of the first reference voltage signal VREF increases. There is a problem that the delay time td between the signals iCLK is increased. In addition, as shown in FIG. 5, as the voltage level of the first reference voltage signal VREF increases, the duty cycle of the internal clock signal iCLK decreases, and the decrease in the duty cycle also increases. These problems are caused by the data set-up time and hold time related to the clock signal in the semiconductor chip sensitively reacting to the noise of the reference voltage signal VREF, resulting in a timing margin between the clock signal and various control signals in the semiconductor chip. It is caused by a decrease.

Accordingly, an object of the present invention is to provide a clock input circuit capable of minimizing a delay time between an external clock signal and an internal clock signal and a duty cycle variation of the internal clock signal.

In order to achieve the above technical problem, the present invention includes a first clock buffer unit for generating an first clock signal by differentially amplifying the external clock signal and the first reference voltage signal; A second clock buffer unit configured to differentially amplify the external clock signal and the second reference voltage signal to generate a second clock signal; And a driver unit generating an internal clock signal in response to the first clock signal and the second clock signal.

In the present invention, it is preferable that the first reference voltage signal is a first reference voltage signal set externally.

In the present invention, the second reference voltage signal is preferably generated from a bandgap reference voltage generator.

In the present invention, it is preferable that the rise time and fall time of the first clock signal and the second clock signal are determined according to the voltage level of the second reference voltage signal.

In an embodiment, the first clock buffer unit may include a pull-down device connected between a ground voltage and a first node and pull-down driving the first node in response to an enable signal; A first transistor coupled between the first node and a second node and turned on in response to the first reference voltage signal; A second transistor connected between the first node and an output node of the first clock signal and turned on in response to the external clock signal; And a third transistor and a fourth transistor sharing a gate at the second node, wherein the third transistor is connected between a power supply voltage and the second node, and the fourth transistor is a power supply voltage and the first clock signal. It is preferable to be connected between the output nodes of.

In the present invention, it is preferable that the pull-down element, the first transistor, and the second transistor are NMOS transistors, and the third and fourth transistors are PMOS transistors.

In an embodiment, the second clock buffer unit may include a pull-up device connected between a power supply voltage and a first node and configured to pull-up the first node in response to a signal buffering an enable signal; A first transistor coupled between the first node and a second node and turned on in response to the second reference voltage signal; A second transistor connected between the first node and an output node of the second clock signal and turned on in response to the external clock signal; And a third transistor and a fourth transistor sharing a gate at the second node, wherein the third transistor is connected between a ground voltage and the second node, and the fourth transistor is connected to a ground voltage and the second clock signal. It is preferable to be connected between the output nodes of.

In the present invention, it is preferable that the pull-up element and the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.

The driver device may further include: a pull-down device configured to pull-down the internal clock signal output terminal in response to the first clock signal; And a pull-up device configured to pull-up the internal clock signal output terminal in response to the second clock signal.

In an embodiment of the present invention, the driver unit may further include a latch unit connected to the internal clock signal output terminal to latch the internal clock signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are merely for illustrating the present invention, and the scope of protection of the present invention is not limited to these embodiments.

2 illustrates a clock input circuit according to an embodiment of the present invention.

As illustrated in FIG. 2, a clock input circuit according to an embodiment of the present invention may generate a first clock signal CLKN by differentially amplifying an external clock signal CLK and a first reference voltage signal VREF. A clock buffer unit 10; A second clock buffer unit 20 for differentially amplifying the external clock signal CLK and the second reference voltage signal VREFi to generate a second clock signal CLKP; A bandgap reference voltage generator 30 generating and outputting the second reference voltage signal VREFi; The driver unit 40 generates an internal clock signal iCLK in response to the first clock signal CLKN and the second clock signal CLKP.

Here, the first reference voltage signal VREF is a first reference voltage signal that is set externally, and a bandgap reference voltage generator that generates the second reference voltage signal VREFi is a reference that minimizes the temperature coefficient. As a circuit for generating a voltage, a circuit generally used in a semiconductor device.

The first clock buffer unit 10 is connected between the ground voltage VSS and the node a, and the first NMOS transistor N1 pull-down-drives the node a in response to the enable signal EN. A second NMOS transistor (N2) connected between the node (a) and the node (b) and turned on in response to the first reference voltage signal (VREF); A third NMOS transistor N3 connected between the node a and a node c outputting the first clock signal CLKN and turned on in response to the external clock signal CLK; A first PMOS transistor P1 and a second PMOS transistor P2 sharing a gate at node b, wherein the first PMOS transistor P1 includes a power supply voltage VDD and the node b. The second PMOS transistor P2 is connected between the power supply voltage VDD and the node c.

The second clock buffer unit 20 is connected between the power supply voltage VDD and the node d, and the enable signal EN pulls the node d in response to the signal buffered through the inverter I1. A third PMOS transistor P3 driving up-up, and a fourth PMOS transistor P4 connected between the node d and the node e and turned on in response to the second reference voltage signal VREFi. )Wow; A fifth PMOS transistor P5 connected between the node d and the node f at which the second clock signal CLKP is output and turned on in response to the external clock signal CLK, And a fourth NMOS transistor N4 and a fifth NMOS transistor N5 that share a gate at node e, wherein the fourth NMOS transistor N4 is connected to the node e and a ground voltage VSS. The fifth NMOS transistor N5 is connected between the ground voltage VSS and the node f.

The driver unit 40 may include a sixth NMOS transistor N6 for pull-down driving the node g from which the internal clock signal iCLK is output in response to the first clock signal CLKN, and the second A sixth PMOS transistor P6 for pull-up driving the node g in response to a clock signal CLKP, and a plurality of inverters connected to the node g to latch the internal clock signal iCLK And a latch portion 42 composed of (I2, I3).

The operation of the clock input circuit of the present invention having such a configuration will be described below with reference to FIG.

First, it is assumed that the voltage levels of the first reference voltage signal VREF and the second reference voltage signal VREFi are the same. When the first NMOS transistor N1 is turned on with the enable signal EN, the first clock buffer unit 10 drives the second and third NMOS transistors N3 and N4 to each gate. The applied first reference voltage signal VREF and the external clock signal CLK are differentially amplified. In this case, when the external clock signal CLK has a voltage level greater than that of the first reference voltage signal VREF, the first clock buffer unit 10 generates a low level first clock signal CLKN. .

In addition, when the third PMOS transistor P3 is turned on by the inverted enable signal ENB, the second clock buffer unit 20 operates the fourth and fifth PMOS transistors P4 and P5 to operate. The second reference voltage signal VREFi and the external clock signal CLK are differentially amplified. At this time, when the external clock signal CLK has a higher voltage level than the second reference voltage signal VREFi, the second clock signal CLKP having a low level is generated.

In addition, the driver 40 may have a low level first clock signal CLKN provided from the first clock buffer unit 10 and a low level second clock provided from the second clock buffer unit 20. The sixth NMOS transistor N6 is turned off by the signal CLKP, and the sixth PMOS transistor P6 is turned on. As a result, the driver unit 40 generates a high level internal clock signal iCLK through the node g.

On the other hand, when the external clock signal CLK has a lower voltage level than the first reference voltage signal VREF, the first clock buffer unit 10 generates the first clock signal CLKN having a high level. The second clock buffer unit 20 generates a high level second clock signal CLKP. Thus, the sixth PMOS transistor P6 of the driver unit 40 is turned off and the sixth NMOS transistor N6 is turned on. Accordingly, the low level internal clock signal iCLK is generated through the node g.

As described above, the second clock buffer unit 20 uses the second reference voltage signal VREFi as a reference voltage signal, wherein the second reference voltage signal VREFi is a bandgap reference voltage generator 30. Since the signal is generated inside the semiconductor, the noise is smaller than that of the reference voltage signal VREF provided from the outside. As a result, the second clock signal CLKP generated by the second clock buffer unit 20 operates irrespective of the change in the voltage level of the external reference voltage signal VREF, and the sixth PMOS transistor of the driver unit 40 is operated. Since the turn-on time of P6 is kept constant, the variation in delay time td of the generated internal clock signal iCLK becomes very small.

Meanwhile, the turn-on time of the sixth NMOS transistor N6 of the driver 40 depends on the rise time and the fall time of the first clock signal CLKN generated by the first clock buffer 10. The rise time and fall time of the first clock signal CLKN depend on the voltage level of the first reference voltage signal VREF. In addition, the turn-on time of the sixth NMOS transistor N6 is increased by the second clock signal CLKP through the node g to which the sixth PMOS transistor P6 and the sixth NMOS transistor N6 are connected. It also depends on time and fall time.

3 is a diagram illustrating a delay time and a duty cycle of an internal clock signal iCLK. The phase difference of the internal clock signal iCLK with respect to the external clock signal CLK is a delay time td of the internal clock signal iCLK. do. The duty cycle of the internal clock signal iCLK is expressed as PW / T x 100 [%]. At this time, T represents one period of the internal clock signal iCLK, and PW represents a high level section of the internal clock signal iCLK.

In order to minimize the variation in the delay time and the variation in the duty cycle of the internal clock signal iCLK, it is desirable to optimally design the voltage level of the second reference voltage signal VREFi through circuit simulation or semiconductor chip test. In order to increase the turn-on time of the sixth PMOS transistor P6 of the driver unit 40 and to minimize the variation in the duty cycle, the voltage level of the second reference voltage signal VREFi is changed to the first reference voltage signal. It is preferable to design so that it is slightly smaller than the voltage level of (VREF).

Since a latch composed of inverters I2 and I3 is connected to the node g, the node g does not float and maintains the internal clock signal iCLK at a low level or a high level.

4 illustrates a delay time of the internal clock signal iCLK with respect to the first reference voltage signal VREF. Referring to FIG. 4, in the conventional clock input circuit, the delay time increases as the voltage level of the external reference voltage signal VREF increases, whereas in the present invention, the voltage level of the first reference voltage signal VREF increases. As a result, the delay time of the internal clock signal iCLK does not change significantly. Accordingly, it can be seen that the clock input circuit of the present invention generates the internal clock signal iCLK having a delay time that is substantially independent of the variation amount of the first reference voltage signal VREF.

5 illustrates a duty cycle of the internal clock signal iCLK with respect to the first reference voltage signal VREF. Referring to FIG. 5, it can be seen that the duty cycle changes as the voltage level of the first reference voltage signal VREF changes. However, in the clock input circuit of the present invention, as the voltage level of the first reference voltage signal VREF changes, the amount of change in the duty cycle is small, but in the related art, the duty cycle according to the voltage level of the first reference voltage signal VREF This can be seen to change significantly.

As described above, the clock input circuit according to the present invention reduces the influence of noise included in the first reference voltage signal on the internal clock signal by using the reference voltage signal stably generated by the band gap inside the semiconductor device. The delay time between the external clock signal and the internal clock signal and the duty cycle of the internal clock signal can be minimized.

In addition, according to the clock input circuit of the present invention, the timing margin can be improved by improving data setup time, hold time, and the like in the semiconductor chip.

Claims (10)

A first clock buffer unit for differentially amplifying an external clock signal and a first reference voltage signal to generate a first clock signal; A second clock buffer unit generating a second clock signal by differentially amplifying a second reference voltage signal stably generated regardless of noise generated in the external clock signal and the first reference voltage signal; And And a driver unit configured to generate an internal clock signal pulled down in response to the first clock signal and pulled up in response to the second clock signal. The method of claim 1, The first reference voltage signal is a clock input circuit, characterized in that the first reference voltage signal set externally. The method of claim 1, And the second reference voltage signal is generated from a bandgap reference voltage generator. The method of claim 1, And a rise time and a fall time of the first clock signal and the second clock signal are determined according to the voltage level of the first reference voltage signal.  The method of claim 1, A pull-down device connected between a ground voltage and a first node and pull-down driving the first node in response to an enable signal; A first transistor coupled between the first node and a second node and turned on in response to the first reference voltage signal;  A second transistor connected between the first node and an output node of the first clock signal and turned on in response to the external clock signal; A third transistor and a fourth transistor sharing a gate to the second node, The third transistor is connected between a power supply voltage and the second node; And a fourth transistor is connected between a power supply voltage and an output node of the first clock signal. The method of claim 5, And the pull-down element, the first transistor, and the second transistor are NMOS transistors, and the third and fourth transistors are PMOS transistors.  The method of claim 1, A pull-up element connected between a power supply voltage and a first node and configured to pull-up the first node in response to a signal buffering an enable signal; A first transistor coupled between the first node and a second node and turned on in response to the second reference voltage signal;  A second transistor connected between the first node and an output node of the second clock signal and turned on in response to the external clock signal; A third transistor and a fourth transistor sharing a gate to the second node, The third transistor is connected between a ground voltage and the second node; And the fourth transistor is connected between the ground voltage and the output node of the second clock signal. The method of claim 7, wherein And the pull-up element and the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors. The method of claim 1, A pull-down device configured to pull-down drive the internal clock signal output terminal in response to the first clock signal; And a pull-up device configured to pull-up the internal clock signal output terminal in response to the second clock signal. The method of claim 9, The driver unit further comprises a latch unit connected to the internal clock signal output terminal to latch the internal clock signal.

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