KR100734375B1 - Led having vertical structure and method for manufacturing the same - Google Patents

Abstract

A vertically structured light emitting device and a manufacturing method thereof are provided to improve crystallization of a thin film and internal quantum efficiency by selectively growing the thin film on a surface where pillars are formed. Plural pillars(20) are formed on a substrate. Plural semiconductor layers(30) are formed on a surface where the pillars are formed. A first electrode(40) is formed on the semiconductor layers. A supporting layer(60) is formed on the first electrode. The substrate is removed. A second electrode(70) is formed on a surface whose substrate is removed. The substrate is one of sapphire, Si, ZnO, and Sic. The pillars are regularly arranged. The height of the pillar is 0.05 to 10 mum, a radius thereof is 0.01 to 6 mum, and an interval between the pillars is 0.03 to 18 mum.

Description

Vertical light emitting device and its manufacturing method {LED having vertical structure and method for manufacturing the same}

1 is a cross-sectional view showing an example of a conventional horizontal light emitting device.

2 is a cross-sectional view showing an example of a horizontal light emitting device in which a conventional photonic crystal is formed.

3 to 5 are cross-sectional views showing an embodiment of the manufacturing method of the vertical light emitting device of the present invention.

  3 is a cross-sectional view showing a substrate.

  4 is a cross-sectional view illustrating a step of forming a pillar of dielectric material on a substrate.

  5 is a plan view of FIG. 4.

6 to 10 are cross-sectional views showing another embodiment of the manufacturing method of the vertical light emitting device of the present invention.

  6 is a cross-sectional view illustrating a step of forming a semiconductor thin film on a substrate.

  7 is a cross-sectional view illustrating a step of forming a pillar of dielectric material on a semiconductor thin film.

  8 is a plan view of FIG. 7.

  9 is a cross-sectional view illustrating a process of forming a plurality of semiconductor layers on a pillar of a dielectric material.

  10 is a cross-sectional view illustrating a step of forming a first electrode and a support layer on a semiconductor layer.

11 is a cross-sectional view showing an embodiment of a vertical light emitting device of the present invention.

<Brief description of the main parts of the drawing>

10 substrate 11 semiconductor thin film

20: dielectric material pillar 21: hole

30 semiconductor layer 40 p-type electrode

50: reflective electrode 60: support layer

70: n-type electrode

The present invention relates to a vertical light emitting device, and more particularly, to a vertical light emitting device for improving light extraction efficiency and a method of manufacturing the same.

Light Emitting Diodes (LEDs) are well-known semiconductor light emitting devices that convert current into light.In 1962, red LEDs using GaAsP compound semiconductors were commercialized, along with GaP: N series green LEDs. It has been used as a light source for display images of electronic devices, including.

The wavelength of light emitted by such LEDs depends on the semiconductor material used to make the LEDs. This is because the wavelength of the emitted light depends on the band-gap of the semiconductor material, which represents the energy difference between the valence band electrons and the conduction band electrons.

Gallium nitride compound semiconductors (Gallium Nitride (GaN)) have attracted much attention in the field of high power electronics development due to their high thermal stability and wide bandgap (0.8-6.2 eV). One reason for this is that GaN can be combined with other elements (indium (In), aluminum (Al), etc.) to produce semiconductor layers that emit green, blue and white light.

In this way, the emission wavelength can be adjusted to match the material's characteristics to specific device characteristics. For example, GaN can be used to create white LEDs that can replace incandescent and blue LEDs that are beneficial for optical recording.

In addition, in the case of the conventional green LED, it was initially implemented as GaP, which was inefficient as an indirect transition type material, and thus practical pure green light emission could not be obtained. However, as InGaN thin film growth succeeded, high brightness green LED could be realized. It became.

Because of these and other benefits, the GaN series LED market is growing rapidly. Therefore, since commercial introduction in 1994, GaN-based optoelectronic device technology has rapidly developed.

Since the efficiency of GaN light emitting diodes outperformed the efficiency of incandescent lamps and is now comparable to that of fluorescent lamps, the GaN LED market is expected to continue to grow rapidly.

Despite the rapid development of GaN device technology as described above, the manufacturing of GaN device has a big disadvantage in terms of cost. This is related to the difficulty of growing GaN epitaxial layers and subsequently cutting the finished GaN-based devices.

GaN-based devices are typically fabricated on sapphire (Al ₂ O ₃ ) substrates. This is because sapphire wafers are commercially available in sizes suitable for mass production of GaN-based devices, support relatively high quality GaN thin film growth, and have a wide range of temperature processing capabilities.

In addition, sapphire is chemically and thermally stable, has a high melting point to enable high temperature manufacturing processes, high binding energy (122.4 Kcal / mole) and high dielectric constant. Chemically, sapphire is crystalline aluminum oxide (Al ₂ O ₃ ).

On the other hand, since the sapphire is an insulator, the shape of the LED element available when using the used sapphire substrate (or other insulator substrate) is, in fact, limited to a lateral or vertical structure.

1 illustrates a horizontal LED device structure among the general GaN series LEDs described above.

The structure of the horizontal LED device is that the n-type gallium nitride (GaN) layer 2, the active layer (light emitting layer: 3), and the p-type gallium nitride (GaN) layer 4 are sequentially positioned on the sapphire substrate 1. The n-type electrode 5 is positioned on the etched surface to expose the n-type GaN layer 2 above, and the p-type electrode 6 is positioned on the p-type GaN layer 4 above.

Recently, research on GaN-based semiconductor light emitting devices has focused on improving luminance. Researches for improving the brightness of optical devices can be classified into methods for improving internal quantum efficiency and methods for improving light extraction efficiency. Recently, researches on how to improve light extraction efficiency have been actively conducted worldwide.

Representative methods for improving light extraction efficiency include etching a sapphire substrate into a constant shape, roughening the surface of a p-type GaN layer, and photonic crystals having a constant period by etching the p-type GaN layer. How to form.

At present, a method of etching a sapphire substrate and a method of roughening the surface of a p-type GaN layer have been applied to mass production technology of light emitting devices worldwide. However, the method using the photonic crystal is well known theoretically and has been reported at the laboratory level, but has not been applied to mass production technology.

Such a method using photonic crystals has more excellent light extraction efficiency than the method of etching sapphire and roughening the surface of p-type GaN layer.

As a representative method using such a photonic crystal, as shown in FIG. 2, in the basic structure as shown in FIG. 1, the upper p-type GaN layer 4 is etched in a regular pattern to form the photonic crystal 7.

However, this method is limited in improving light extraction efficiency due to the inherently low electrical properties of the p-type GaN layer 4 and the degradation of the electrical properties by thin film thickness and etching.

Another method is to form a photonic crystal structure on the upper n-type GaN layer by using a structure in which a p-type GaN layer is first grown on a substrate, a light emitting layer is grown, and an n-type GaN layer is grown on top. .

However, the inherently low electrical conductivity of the p-type GaN layer and the degradation of the electrical properties due to low crystallinity and etching make it impossible to grow the p-type GaN layer at the bottom.

Another method is to grow an n-type GaN layer on a sapphire substrate, then grow a light emitting layer, grow a p-type GaN layer, and then grow an n-type GaN layer again. This is a method using the electrical tunnel junction property between the p-type GaN layer and the n-layer GaN layer.

However, this method also has the problem of increasing the resistance at the junction due to the low electrical properties of the p-type GaN layer, which in turn increases the operating voltage of the device.

In other methods, the n-type GaN layer, the light emitting layer, and the p-type GaN layer are grown on the sapphire substrate in order, and then the sapphire is removed by an appropriate method. The photonic crystal is formed on the GaN layer by an etching process.

However, this method also has a problem that the metal plate is not sufficiently stable in the etching process step of the bonded thin film layer, the etching process is difficult and the productivity is low.

The technical problem to be achieved by the present invention is to implement a light emitting device having a high brightness and high efficiency by applying a photonic crystal structure that can improve the light extraction efficiency, and to increase the crystallinity of the thin film by growing a thin film on the dielectric pillar It is to provide a vertical light emitting device and a method of manufacturing the same that can improve the efficiency of the light emitting device through the stress control therein.

In order to achieve the above technical problem, the present invention comprises the steps of forming a plurality of pillars on the substrate; Forming a plurality of semiconductor layers on a surface on which the pillars are formed; Forming a first electrode on the plurality of semiconductor layers; Forming a support layer on the first electrode; Removing the substrate; It is preferably configured to include the step of forming a second electrode on the surface from which the substrate is removed.

As another aspect for achieving the above technical problem, the present invention, a metal support plate; A reflective electrode on the metal support plate; A p-type electrode positioned on the reflective electrode; An ohmic forming layer positioned on the p-type electrode; A plurality of GaN based semiconductor layers positioned on the ohmic forming layer; A photonic crystal layer positioned on the semiconductor layer and formed by a plurality of holes arranged periodically; An n-type transparent ohmic layer positioned on the photonic crystal layer; It is preferable to comprise the n-type electrode located on the n-type transparent ohmic layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the substrate 10 is treated with a surface by a wet or dry process. As the substrate 10, sapphire, silicon (Si), zinc oxide (ZnO), silicon carbide (SiC), or the like may be used.

On this substrate 10, as shown in Figure 4, a plurality of pillars of dielectric material 20 are formed. The vertical cross-sectional shape of the dielectric pillars 20 can be round, square, hexagonal, and other polygons.

The dielectric material pillar 20 may be formed of an oxide or nitride, and in particular, may be formed using silicon oxide (SiO ₂ ) or silicon nitride (SiN).

The dielectric material pillar 20 may be formed through a pattern process or an etching process. That is, the dielectric material layer may be formed and etched to form the dielectric material pillar 20.

As shown in FIG. 4, the dielectric material pillar 20 may be formed in the entire region, but in some cases, the dielectric material pillar 20 may be formed only in the region in which the unit elements are formed. Alternatively, it may be formed by filling the dielectric material (not shown). FIG. 5 illustrates a plane in which dielectric pillars 20 are formed only in a unit device formation region.

Meanwhile, as shown in FIG. 6, the GaN semiconductor thin film 11 is grown on the substrate 10 using a conventional semiconductor thin film growth apparatus, and the above-described dielectric material pillars 20 are formed on the GaN thin film 11. It may be formed.

In this case, as shown in FIG. 6, the GaN semiconductor thin film 11 may be formed only in the unit device formation region, or the semiconductor thin film 11 may be formed on the entire surface, and the unit device division region may be etched and removed.

The thin film 11 may be formed to have a thickness of 0.001 to 5 μm. The thin film 11 may be used as a buffer layer on the substrate 10.

Subsequently, as shown in FIG. 7, the dielectric material pillar 20 is formed on the portion where the GaN semiconductor thin film 11 is formed.

In FIG. 8, the plane in which the dielectric material pillars 20 are formed on the GaN semiconductor thin film 11 is illustrated.

In addition, the dielectric material pillar 20 may not be formed in the unit device division region, and the dielectric material may be filled in the entire division region.

The following process will be described using the structure in which the dielectric material pillars 20 are formed on the GaN semiconductor thin film 11. However, the following process may be similarly applied to the structure in which the dielectric material pillars 20 are directly formed on the substrate 10.

As shown in FIG. 9, a plurality of GaN-based semiconductor layers 30 are formed on the GaN semiconductor thin film 11 on which the dielectric material pillars 20 are formed.

The GaN series semiconductor layer 30 includes an n-type GaN layer 31, a light emitting layer (active layer 32), and a p-type GaN layer 33. The light emitting layer usually forms a single or multiple quantum well structure. In this case, materials such as In and Al may be mixed and used to form a quantum well structure.

The n-type GaN layer 31 is not formed on the dielectric material pillar 20 at first, but is formed on the thin film 11 between the dielectric material pillars 20.

As such, when the n-type GaN layer 31 is formed between the thin film 11 and the dielectric material pillar 20 to cover the dielectric material pillar 20, the n-type GaN layer 31 may be As shown in Fig. 9, it is grown in layers.

In this case, since the GaN-based semiconductor layer 30 is not formed since the sapphire substrate 10 or the dielectric material (not shown) is filled in the unit device division region, a separate process of separating the device from the device in a subsequent process step You do not need this.

In addition, if the GaN semiconductor layer 30 is selectively formed on the dielectric material pillar 20, a high quality n-type GaN layer 31, a light emitting layer 32, and a p-type GaN layer 33 may be formed. have.

For this reason, the thin film layer selectively formed on the dielectric material pillar 20 can effectively alleviate the strain due to the substrate 10 in a significant amount.

This reduction in strain in the single device thin film layer may eventually increase the internal quantum efficiency of the light emitting layer 32.

Furthermore, according to the present invention, since the pillars 20 of the dielectric material are positioned below the n-type GaN layer 31, the semiconductor layer 30 grown thereon is disposed between the substrate 10 and the thin film of the semiconductor layer 30. It is possible to reduce the density of threading dislocations, which is an inherent thin film defect, starting at the interface of. This reduction in dislocation density can greatly contribute to improving the performance of the device.

Thereafter, as shown in FIG. 10, a p-type electrode 40 is formed on the GaN-based semiconductor layer 30 after filling the separation region between the device and a thermochemically removable material such as epoxy. Form. The p-type electrode 40 forms an ohmic electrode, and a reflective electrode 50 for improving reflection efficiency may be formed on the p-type electrode 40.

At this time, the time when the material such as epoxy is filled may be different.

If an oxide layer such as indium tin oxide or zinc oxide (ZnO), AlZnO, InZnO, or the like is used as the p-type electrode 40, the ohmic characteristics are improved on the p-type GaN layer 33. A thin n-type GaN layer may be further formed as the ohmic forming layer 34.

In addition, the support layer 60 may be formed or attached on the p-type electrode 40 or the reflective electrode 50 to support the structure of the entire device when the substrate 10 is later removed.

The support layer 60 may be a metal plate, a silicon (Si) substrate, or the like formed using a metal plate such as copper (Cu), gold (Au), nickel (Ni), or an alloy thereof, which is advantageous for heat dissipation. In addition, the metal plate may be formed by plating on the reflective electrode 50.

When the metal plate is formed as the support layer 60, a seed metal for intermetallic bonding may be used between the support layer 60 and the p-type electrode 40 or the reflective electrode 50. .

The next step is to remove the substrate 10 on which the GaN semiconductor layer 30 thin film is grown. In the case of the sapphire substrate 10, a laser may be used or physically removed, and in the case of silicon, chemical or physical removal may be performed. As such, the surface from which the substrate 10 has been removed is preferably etched and subjected to surface treatment.

As such, the structure in which the dielectric material pillars 20 are arranged is located in the n-type GaN layer 31 of the GaN semiconductor layer 30 from which the substrate 10 is removed. In some cases, these pillars 20 may be removed by etching. When the dielectric material pillar 20 is removed as shown in FIG. 11, a plurality of holes 21 are formed in the n-type GaN layer 31.

The arrangement of the dielectric material pillars 20 or the holes 21 may improve the luminous efficiency of the light emitting device even though the array of the dielectric material pillars 20 or the holes 21 does not have a predetermined period and pattern.

On the other hand, when the pillar 20 or the hole 21 has a predetermined period and pattern in the nitride semiconductor thin film layer, the photonic crystal structure is formed on the light emitting surface by the regularly aligned pillar 20 or the hole 21 Can be.

When such a photonic crystal structure is formed, the refractive index is arranged periodically in the photonic crystal structure. At this time, when the period of the photonic crystal is approximately half of the wavelength of the emitted light, the photonic band gap is caused by multiple scattering of photons by the photonic crystal lattice whose refractive index changes periodically. Is formed.

In such a photonic crystal structure, light has a property of being effectively emitted in a constant direction. That is, since such a light forbidden zone is formed, the emitted light does not flow into or pass through the dielectric material pillar 20 or the hole 21 constituting the photonic crystal structure, and other than the dielectric material pillar 20 or the hole 21. Extraction through the part may occur.

The above phenomenon can be explained by the behavior of photons in the photonic crystal structure formed by the plurality of holes 21 having periodicity.

That is, the dielectric constant is periodically modulated in the photonic crystal structure by the plurality of holes 21 having periodicity, and affects the behavior of light propagating through the photonic crystal structure.

In particular, in the case where the light inhibiting zone of the photonic crystal structure belongs to or is included in the wavelength band of the light emitted from the light emitting device, the photon of the light emitting device produces an effect as if it is reflected by the total reflection phenomenon in the light emitting device.

These photoblocks have similarities to the electrons in the crystal structure, and photons belonging to the photoblocks do not freely propagate in the photonic crystal.

Therefore, if all the photons of the light emitted from the light emitting element belongs to the light inhibiting zone, all the photons exit the light emitting element similar to the total reflection phenomenon, the luminous efficiency is increased.

As a result, in order for the photonic crystal structure to effectively emit light, the height and radius of the dielectric material pillar 20, the gap between the pillar 20 and the pillar 20, or the depth of the hole 21 being etched and the hole 21 are used. It is preferable that the size and the distance between the hole 21 and the hole 21 is optimized according to the wavelength of light emitted.

In the case of the nitride semiconductor light emitting device, the height of the dielectric material pillar 20 is 0.001 to 10 μm, the radius of the pillar 20 is 0.001 to 6 μm, and the interval between the pillar 20 and the pillar 20, that is, the photonic crystal period is 0.003. 18 micrometers is preferable.

Therefore, the depth of the hole 21 formed by etching the dielectric material pillar 20 is 0.001 ~ 10㎛, the radius of the hole 21 is 0.001 ~ 6㎛, the interval between the hole 21 and the hole 21 Becomes 0.003-18 micrometers.

An example of the light emitting device structure formed through such a process is as shown in FIG. 11.

As shown, an n-type electrode 70 is formed on the surface from which the substrate 10 is removed. In this case, even when the dielectric material pillar 20 is removed by etching, it is preferable not to remove the dielectric material 20 in at least a portion where the n-type electrode 70 is formed.

In addition, an n-type transparent ohmic layer 72 may be formed in a portion where the hole 21 is exposed, thereby improving luminous efficiency by current diffusion.

On the other hand, by forming the reflective layer 71 on the lower side of the n-type electrode 70, the n-type electrode 70 is reflected from the reflective layer 71 without absorbing the light emitted from the light emitting layer 32 It can also be released to the outside.

Hereinafter, specific embodiments of the present invention will be described with reference to FIGS. 3 to 11.

In the present invention, metal organic chemical vapor deposition (MOCVD) was used to grow the nitride semiconductor thin film.

Sapphire was used as the substrate 10. Ammonia was used as the nitrogen source and hydrogen and nitrogen were used as the carrier gas.

Gallium (Ga), indium (In) and aluminum (Al) used an organometallic source. The n-type dopant was made of silicon (Si), and the p-type dopant was made of magnesium (Mg).

A 1 μm thick n-type GaN semiconductor 11 thin film was grown on the sapphire substrate 10 at 1030 ° C., and a pressure of 250 Torr was applied.

The photonic crystal period was 1.2 μm, the radius of the dielectric material pillar 20 was 0.4 μm, and the etching depth was 3 μm. Silicon oxide (SiO ₂ ) was used as the dielectric material pillar 20.

Thereafter, a 6 μm thick n-type GaN layer 31 is grown on the photonic crystal structure, and the light emitting layer 32 having five pairs of indium gallium nitride / gallium nitride (InGaN / GaN) multiple quantum well structures thereon. Was formed.

A p-type GaN layer 33 having a thickness of 0.1 µm was grown on the light emitting layer 32, and a thin n-type GaN layer (omic forming layer: 34) was formed on the top thereof to improve ohmic characteristics.

After filling an epoxy in the region between the device and the device, 0.2 μm of indium tin oxide (ITO) was deposited on the p-type electrode 40, and then the support layer 60 formed of the reflective electrode 50 and copper (Cu) was formed. It was.

Next, after the sapphire substrate 10 was removed using a laser, the exposed surface was etched by 1 μm to remove the crystal defect layer.

As such, the exposed surface was chemically treated to form an n-type electrode 70 layer.

When the device formed by the above method was separated into a single device and then packaged to measure the characteristics of the light emitting device, the device luminance was improved by more than 35% compared to the reference specimen.

The above embodiment is an example for explaining the technical idea of the present invention in detail, and the present invention is not limited to the above embodiment, various modifications are possible, and various embodiments of the technical idea are all protected by the present invention. It belongs to the scope.

The present invention as described above has the following effects.

First, by applying a photonic crystal structure excellent in the light extraction efficiency improvement effect to the light emitting device in an effective way it is possible to implement a light emitting device of high brightness and high efficiency.

Second, by selectively growing a thin film on a structure in which the pillars of the dielectric material are periodically aligned, the crystallinity of the thin film may be improved and the internal quantum efficiency of the light emitting device may be improved by controlling the stress in the thin film.

Third, since the nitride semiconductor photonic crystal structure can be formed without etching the nitride semiconductor thin film layer, the process is easy, thereby improving productivity and reducing production costs of device fabrication.

Claims (20)

Forming a plurality of pillars on the substrate; Forming a plurality of semiconductor layers on a surface on which the pillars are formed; Forming a first electrode on the plurality of semiconductor layers; Forming a support layer on the first electrode; Removing the substrate; And forming a second electrode on a surface from which the substrate is removed. The method of claim 1, wherein the substrate is one of sapphire, Si, ZnO, and SiC. The method of claim 1, wherein the plurality of pillars are regularly arranged. The method of claim 1, wherein the plurality of pillars, A method of manufacturing a vertical light emitting device, characterized in that the height is 0.05 to 10 mu m, the radius is 0.01 to 6 mu m, and the spacing between the pillars is 0.03 to 18 mu m. The method of claim 1, wherein the plurality of pillars are formed of a dielectric material. The method of claim 5, wherein the dielectric material is any one of silicon oxide and silicon nitride. The method of claim 1, wherein the forming of the plurality of semiconductor layers comprises: Forming an n-type semiconductor layer on the semiconductor layer on which the plurality of pillars are formed; Forming an active layer on the n-type semiconductor layer; And forming a p-type semiconductor layer on the active layer. The method of claim 7, further comprising forming a thin n-type semiconductor layer on the p-type semiconductor layer. The method of claim 1, wherein the forming of the first electrode comprises: Forming an ohmic electrode; And forming a reflective electrode on the ohmic electrode. The method of claim 1, wherein the support layer is a metal plate or a silicon substrate. The method of claim 1, wherein the forming of the plurality of pillars on the substrate comprises: Forming a semiconductor thin film on the substrate; Vertical light emitting device manufacturing method comprising the step of forming a plurality of pillars on the thin film. 12. The method of claim 1 or 11, wherein after removing the substrate, And etching a surface from which the substrate is removed. 12. The method of claim 11, wherein the semiconductor thin film is formed in a unit element formation region. The method of claim 1, wherein after removing the substrate, And removing a portion or the entirety of the plurality of pillars exposed by removing the substrate. The method of claim 1, wherein the forming of the second electrode comprises: Forming a transparent ohmic layer on a surface from which the substrate is removed; And forming an electrode pad on a surface where the transparent ohmic layer is formed. A support plate; A reflective electrode on the support plate; A p-type electrode positioned on the reflective electrode; An ohmic forming layer positioned on the p-type electrode; A plurality of GaN based semiconductor layers positioned on the ohmic forming layer; A photonic crystal layer positioned on the semiconductor layer and formed by a plurality of holes arranged periodically; An n-type transparent ohmic layer positioned on the photonic crystal layer; And a n-type electrode positioned on the n-type transparent ohmic layer. 17. The vertical light emitting device of claim 16, wherein the ohmic forming layer is a thin n-type GaN layer. The vertical type light emitting device of claim 16, wherein the p-type electrode is formed of at least one of ITO, ZnO, AlZnO, and InZnO. 17. The vertical light emitting device of claim 16, wherein a reflective layer is positioned between the transparent ohmic layer and the n-type electrode. The vertical type light emitting device according to claim 16, wherein the support plate is a metal plate or silicon made of one of Cu, Au, and Ni or an alloy thereof.

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