KR100729784B1 - Method for fabricating thin film transistor substrate - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate. In order to improve the contact characteristics of an aluminum wiring and a transparent conductive material layer and to simplify the manufacturing process, an insulating film covering the wiring in a silicon-rich atmosphere is deposited on the surface of the wiring. Form a contact auxiliary layer. In order to manufacture the thin film transistor substrate according to the present invention, after forming a gate wiring including a gate line and a gate electrode on the substrate, a first contact auxiliary layer and a gate insulating film covering the gate wiring are formed. Subsequently, after the semiconductor pattern is formed on the gate insulating layer, a data line including a data line crossing the gate line, a source electrode connected to the gate line, and a drain electrode corresponding to the source electrode is formed. Subsequently, after forming a passivation layer covering the semiconductor pattern and the data line, a first contact hole exposing the drain electrode is formed, and then a pixel electrode electrically connected to the drain electrode through the first contact hole is formed.

Contact auxiliary layer, aluminum wiring, process simplification, silicon rich atmosphere

Description

Method of manufacturing thin film transistor substrate {METHOD FOR FABRICATING THIN FILM TRANSISTOR SUBSTRATE}

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ of FIG. 1.

3A to 7B are process charts for manufacturing a thin film transistor substrate according to the first embodiment of the present invention.

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate taken along the cutting lines X′- ′ ′ and X′- ′ ′ shown in FIG. 8;

11A through 18C are manufacturing process diagrams of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate used in a liquid crystal display device.                         

In the liquid crystal display, a liquid crystal material is injected between a lower substrate on which a thin film transistor and a pixel electrode are formed and an upper substrate on which an opposing electrode and a color filter are formed, and different potentials are applied to the pixel electrode and the opposite electrode. By applying to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to express the image.

A general manufacturing process of a thin film transistor substrate is to form a gate wiring on the substrate, an active layer formed of a three-layer film of a gate insulating film, a semiconductor layer, and an ohmic contact layer on the gate wiring, and then a data wiring formed thereon. A protective film and a pixel electrode are formed.

In order to manufacture a thin film transistor substrate for a large-area high definition liquid crystal display device, a step of forming a low resistance wiring is necessary. As the low resistance wiring, an aluminum series such as aluminum or an aluminum alloy is mainly used. Low-resistance wiring should be in electrical contact with the pixel electrode with low resistance, but aluminum-based has a high contact resistance with indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, since not only the pixel electrode but also the gate pad or the data pad must be in contact with an auxiliary pad made of ITO or IZO, a technique for improving the contact resistance between the aluminum-based and the transparent conductive material is required. Currently, a technique of using chromium or molybdenum as an intermediate layer between an aluminum-based and a transparent electrode is used to avoid direct contact between the two material layers, but this technique has a problem in that the manufacturing process is complicated.

The present invention is to provide a method for manufacturing a thin film transistor substrate to improve the contact characteristics of the aluminum wiring and the transparent conductive material layer.

In addition, the present invention is to provide a method for manufacturing a thin film transistor substrate that can simplify the manufacturing process.

In order to solve this problem, in the present invention, an insulating film covering the wiring in a silicon-rich atmosphere is deposited to form a contact auxiliary layer on the surface of the wiring.

In detail, in order to manufacture the thin film transistor substrate according to the present invention, after forming a gate wiring including a gate line and a gate electrode on the substrate, a first contact auxiliary layer and a gate insulating film covering the gate wiring are formed. Subsequently, after the semiconductor pattern is formed on the gate insulating layer, a data line including a data line crossing the gate line, a source electrode connected to the gate line, and a drain electrode corresponding to the source electrode is formed. Subsequently, after forming a passivation layer covering the semiconductor pattern and the data line, a first contact hole exposing the drain electrode is formed, and then a pixel electrode electrically connected to the drain electrode through the first contact hole is formed.

The first contact auxiliary layer and the gate insulating layer may be formed at the same time. At this time, the gate insulating film is formed using a mixed gas in which NH ₃ : SiH ₄ is mixed in a ratio of 10: 1 or less, or the gate wirings are surface treated with SiH ₄ plasma before forming the gate insulating film.

In the present invention, it is advantageous to clean the gate wirings with an alkaline solution before forming the gate insulating film, and after forming the gate insulating film, heat treatment is preferably performed at 250 to 350 ° C.

In addition, the second contact auxiliary layer may be formed on the surface of the data line in the process of forming the passivation layer. The second contact auxiliary layer forms the surface portion of the data line in the process of forming the passivation layer after forming the data line. It is made of silicon-rich atmosphere and formed together with the protective film. At this time, the protective film uses a mixed gas in which NH ₃ : SiH ₄ is mixed in a ratio of 10: 1 or less. It is preferable to surface-treat the data wiring with SiH ₄ plasma before forming the protective film. At this time, it is advantageous to wash the data wirings with an alkaline solution before forming the protective film, and after the protective film is formed, it is advantageous to proceed the heat treatment at 250 to 350 ° C.

In the present invention, the semiconductor pattern and the data wiring may be formed together using one mask, wherein the mask includes a first region, a second region having a lower transmittance than the first region, and a third having a higher transmittance than the first region. It is patterned to include regions. In this case, the semiconductor pattern and the data line may be formed together by using a photoresist pattern having a different thickness formed using a mask. The photoresist pattern may include a first portion having a first thickness and a source electrode and a drain electrode having an upper thickness on the data line. It may be formed of a second portion having a second thickness thinner than the first thickness in the upper portion therebetween.                     

In the present invention, the first contact hole may expose the second contact auxiliary layer portion on the drain electrode, and contact the pixel electrode to the second contact auxiliary layer portion on the drain electrode. Here, the gate line further includes a gate pad connected to the gate line, the data line further includes a data pad connected to the data line, forming a second contact hole exposing the gate pad in the passivation layer and the gate insulating layer, and forming the passivation layer. And forming a third contact hole exposing the data pad in the second hole, and forming an auxiliary gate pad electrically connected to the gate pad through the second contact hole and an auxiliary data pad electrically connected to the data pad through the third contact hole. have. At this time, the second contact hole exposes the first contact auxiliary layer portion on the gate pad, the auxiliary gate pad contacts the first contact auxiliary layer portion on the gate pad, and the third contact hole is located on the second pad on the data pad. The contact auxiliary layer portion may be exposed and the auxiliary data pad may contact the second contact auxiliary layer portion on the data pad.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ of FIG. 1.

Gate wirings 22, 24, and 26 having a thickness of 2500 to 3,500 GHz are formed on the insulating substrate 10, which is made of a low resistance metal material, for example, aluminum, such as aluminum or an aluminum alloy. The gate lines 22, 24, and 26 include a gate line 22 extending in the horizontal direction, a gate pad 24, and a gate electrode 26. The gate wirings 22, 24, and 26 may be formed in a double layer or more structure in addition to the single layer structure. The first contact auxiliary layer 210 made of a conductive material such as aluminum-silicon nitride film (SiAlON) is formed on the surfaces of the gate lines 22, 24, and 26.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 1500 to 4000 GPa made of an insulating material, for example, silicon nitride, covers the gate wirings 22, 24, and 26.

On the gate insulating layer 30, a semiconductor pattern 42 having a thickness of 00 to 1500 Å made of a semiconductor material, for example, amorphous silicon, overlaps the gate electrode 26, and an example of a semiconductor material doped with impurities is formed on the semiconductor pattern 42. For example, ohmic contact layers 55 and 56 having a thickness of 500 to 800 kPa made of amorphous silicon doped with impurities at a high concentration are formed.

On the ohmic contacts 55 and 56 and the gate insulating layer 30, a metal material 601 including molybdenum, titanium, tantalum, or chromium, and a low resistance metal material such as aluminum or Double-layered data lines 62, 64, 65, and 66 are formed of an aluminum-based layer 602 made of aluminum, such as an aluminum alloy. The data wires 62, 64, 65, and 66 protrude from the data line 62, the data pad 64, and the data line 62 formed in the vertical direction to contact a single ohmic contact layer 55 to form a thin film. A source electrode 65 constituting part of the transistor and a drain electrode 66 constituting part of the thin film transistor in contact with the other ohmic contact layer 56 corresponding to the source electrode 65 are included. On the surface of the aluminum based layer 602 of the data lines 62, 64, 65, and 66, a second contact auxiliary layer 610 made of a conductive material such as aluminum-silicon nitride oxide (SiAlON) is formed.

A protective film 70 made of an insulating material, for example, silicon nitride, is formed on the exposed front surface of the substrate including the data lines 62, 64, 65, and 66.

In the passivation layer 70, first and third contact holes 72 and 76 exposing the second contact auxiliary layer 610 existing on the surface of the drain electrode 66 and the data pad 64 are formed. The second contact hole 74 exposing the first contact auxiliary layer 210 existing on the surface of the gate pad 24 is formed in the 70 and the gate insulating layer 30.

Further, on the passivation layer 70, a pixel electrode 82, an auxiliary gate pad 84, and an auxiliary data pad 86 made of IZO or ITO are formed. The pixel electrode 82 is electrically connected to the drain electrode 66 through the first contact hole 72 to receive an image signal from the data line 62. In addition, the auxiliary gate pad 84 and the auxiliary data pad 86 are electrically connected to the gate pad 24 and the data pad 64 through the second and third contact holes 74 and 76.

In the present invention, the pixel electrode 82 and the auxiliary data pad 86 are directly connected to the drain electrode 66 and the data pad 64 through the second contact auxiliary layer 610 made of aluminum-silicon nitride film (SiAlON). The auxiliary gate pad 84 is in direct contact with the gate pad 24 through the first contact auxiliary layer 210 formed of aluminum-silicon nitride oxide (SiAlON). Since a transparent conductive material such as IZO or ITO is in contact with a conductive material such as aluminum-silicon nitride film (SiAlON) with low contact resistance, in the present invention, the pixel electrode 82 made of IZO or ITO, auxiliary data The pad 86 and the auxiliary gate pad 84 have a low contact resistance to the drain electrode 66, the data pad 64, and the gate pad 24 made of aluminum through the contact auxiliary layers 210 and 610 and are stable. Contact with.

Next, a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a metal material layer having a low resistance characteristic, for example, an aluminum-based layer is deposited on the substrate 10, and is etched by a photolithography process using a mask to form the substrate 10. Gate wirings 22, 24, and 26 are formed on the substrate. The gate wirings 22, 24, and 26 include a gate line 22, a gate pad 24, and a gate electrode 26.

Next, as shown in FIG. 4, the surface of the gate wirings 22, 24, 26 is cleaned using an alkaline solution.

Next, a gate insulating film 30 made of an insulating material, for example, silicon nitride, is deposited. At this time, the first contact auxiliary layer 210 made of a conductive material such as aluminum-silicon nitride oxide (SiAlON) is also formed on the surfaces of the gate lines 22, 24, and 26 together with the gate insulating layer 30.

The gate insulating film 30 is preferably performed immediately after cleaning the surface of the gate wirings 22, 24, and 26 to minimize the possibility of forming a natural oxide film caused by the exposure of the gate wirings 22, 24, and 26 to the atmosphere. Do.                     

The gate insulating film 30 is formed by CVD deposition using a mixed gas of NH ₃ and SiH ₄ at 270 ° C. or higher. At this time, the surface of the gate wirings 22, 24, and 26 are made into a silicon-rich atmosphere so that the gate insulating film 30 is deposited. In this case, while the gate insulating film 30 covering the gate wirings 22, 24, and 26 is formed, the surface of the gate wirings 22, 24, and 26 is directly made of a conductive material such as aluminum-silicon nitride film (SiAlON). A first contact auxiliary layer 210 is also formed.

Aluminum-silicon nitride film (SiAlON) is formed by the reaction of aluminum, nitrogen, oxygen, and silicon, and aluminum or silicon-silicon nitride film (SiAlON) with higher silicon content has lower contact resistance with ITO or IZO. Are contacted with. Since the content of aluminum is limited by the gate wirings 22, 24 and 26, in the present invention, in order to increase the content of silicon, the process conditions for making the surface of the gate wirings 22, 24 and 26 become a silicon-rich atmosphere. Make

When depositing the gate insulating film 30, as a method for making the surface of the gate wirings 22, 24, and 26 into a silicon-rich atmosphere, the content ratio of the reaction gas used for depositing the gate insulating film 30 is controlled. .

For example, gate wiring using a mixed gas having a high silicon content, for example, a mixed gas in which the ratio of NH ₃ : SiH ₄ is 10: 1 or less (eg, 3: 1 or 5: 1). The gate insulating film 30 is deposited by making the surface of (22, 24, 26) a silicon-rich atmosphere. In this case, the content of silicon is greatly increased as compared with the conventional silicon content ratio for depositing the gate insulating film 30.

In addition, when depositing the insulating film 30, another method for making the surface of the gate wirings 22, 24, and 26 become a silicon-rich atmosphere, and before the gate insulating film 30 is deposited, the gate wirings 22, 24, 26 may be used. The surface of is treated with silicon plasma for at least 10 seconds. In this case, silicon is abundantly present near the surface of the gate wirings 22, 24, and 26.

As such, in the case of depositing the gate insulating film 30 in a silicon-rich atmosphere, an aluminum-silicon nitride film (SiAlON) that directly covers the surface of the gate wirings 22, 24, and 26 while the gate insulating film 30 is formed. That is, the first contact auxiliary layer 210 is formed. Since the contact sentry layer 210 is in contact with the transparent conductive material layer formed later with a low contact resistance, the contact auxiliary layer functions to assist the contact between the gate wirings 22, 24, and 26 and the transparent conductive material layer. do.

 Subsequently, when annealing is performed in the range of 250 to 350 ° C. for 30 minutes to 2 hours, the resistance characteristic of the first contact auxiliary layer 210 is further stabilized by the annealing.

Next, as illustrated in FIGS. 5A and 5B, the semiconductor layer and the semiconductor layer doped with impurities are sequentially stacked on the gate insulating layer 30, and then the semiconductor layer and semiconductor doped with impurities are subjected to a photolithography process using a mask. The layer is etched to form the semiconductor pattern 42 and the ohmic contact layer 52.

Next, as shown in FIGS. 6A and 6B, a metal layer 601 made of molybdenum, titanium, tantalum, or chromium based on the front surface of the substrate and an aluminum-based layer made of aluminum, such as aluminum-neodymium, thereon 602 is continuously deposited and then etched by a photolithography process using a mask to form data lines 62, 63, 66, and 68. The data lines 62, 64, 65, and 66 include a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66.

Subsequently, the island-like ohmic contact layer 52 integrally formed using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 with the ohmic contact layer 55 and the drain electrode ( 66 into a resistive contact layer 56 in contact with it.

Next, as shown in FIGS. 7A and 7B, the surface of the data lines 62, 64, 65, and 66 is cleaned using an alkaline solution.

Subsequently, a protective film 70 made of an insulating material, for example, silicon nitride, is deposited. In this case, a second contact auxiliary layer 610 made of a conductive material such as aluminum-silicon nitrate (SiAlON) is also formed on the surfaces of the data wiring lines 62, 64, 65, and 66 together with the passivation layer 70.

The passivation layer 70 is performed immediately after cleaning the surfaces of the data lines 62, 64, 65, and 66 to minimize the possibility of forming a natural oxide film caused by exposing the data lines 62, 64, 65, and 66 to the atmosphere. It is desirable to.

The protective film 70 is formed by CVD deposition using a mixed gas of NH ₃ and SiH ₄ at 270 ° C. or higher. At this time, the surface of the data lines 62, 64, 65, 66 is made into a silicon-rich atmosphere to deposit the protective film 70. In this case, the protective film 70 covering the data wires 62, 64, 65, and 66 is formed, and the surface of the data wires 62, 64, 65, and 66 is formed directly on the surface of the aluminum-silicon nitride oxide (SiAlON). A second contact auxiliary layer 610 made of a conductive material is also formed.

Aluminum-silicon nitride film (SiAlON) is formed by the reaction of aluminum, nitrogen, oxygen and silicon, and aluminum or silicon-silicon nitride film (SiAlON) formed by increasing the content of aluminum or silicon has lower contact with ITO or IZO. Contact with resistance. Since the aluminum content is limited by the data wirings 62, 64, 65, and 66, in order to increase the content of silicon in the present invention, the surface of the data wirings 62, 64, 65, and 66 may have a silicon-rich atmosphere. To make the process conditions.

In the deposition of the protective film 70, as a method for making the surface of the data lines 62, 64, 65, and 66 into a silicon-rich atmosphere, the content ratio of the reactive gas used to deposit the protective film 70 is controlled. .

For example, using a mixed gas having a high silicon content, for example, a mixed gas in which the ratio NH ₃ : SiH ₄ is 10: 1 or less (eg, 3: 1 or 5: 1). The protective film 70 is deposited by making the surfaces of the wirings 62, 64, 65, and 66 into a silicon-rich atmosphere.

In addition, during the deposition of the protective film 70, another method for making the surface of the data wirings 62, 64, 65, 66 into a silicon-rich atmosphere, and before the deposition of the protective film 70, the data wirings 62, 64, 65. , 66) is treated with silicon plasma for at least 10 seconds. In this case, silicon is abundantly present near the surface of the data lines 62, 64, 65, and 66.                     

As described above, in the case of depositing the gate protective film 70 in a silicon-rich atmosphere, an aluminum-silicon nitride film (SiAlON) that directly covers the surface of the data lines 62, 64, 65, and 66 while the protective film 70 is formed. That is, the second contact auxiliary layer 610 is formed. Since the contact sentry layer 610 is in contact with the transparent conductive material layer formed later with a low contact resistance, the contact auxiliary layer assists the contact between the data lines 62, 64, 65 and 66 and the transparent conductive material layer. Function

Subsequently, when annealing is performed in the range of 250 to 350 ° C. for 30 minutes to 2 hours, the resistance characteristic of the second contact auxiliary layer 610 is further stabilized by the annealing.

Next, the first contact hole 72 exposing the second contact auxiliary layer 610 on the drain electrode 66 by etching the passivation layer 70 and the gate insulating layer 30 by a photolithography process using a mask. A second contact hole forming a third contact hole 76 exposing a portion of the second contact auxiliary layer 610 over the data pad 64 and a second contact hole exposing the first contact auxiliary layer 210 over the gate pad 24. Form 74.

Next, as shown in FIGS. 1 and 2, the pixel electrode 82, which is electrically connected to the drain electrode 66 by etching the IZO layer or the IZO layer by deposition and using a photolithography process using a mask, An auxiliary gate pad 84 and an auxiliary data pad 86 are electrically connected to the gate pad 24 and the data pad 64, respectively. In this case, the pixel electrode 82 is electrically connected to the drain electrode 66 through the first contact hole 72, and the auxiliary gate pad 84 and the auxiliary data pad 86 are second and third contact holes. It is electrically connected to the gate pad 24 and the data pad 64 via 74 and 76.                     

Since a transparent conductive material such as IZO or ITO is in contact with a conductive material such as aluminum-silicon nitride film (SiAlON) with low contact resistance, in the present invention, the pixel electrode 82 made of IZO or ITO, an auxiliary data pad The 86 and the auxiliary gate pad 84 have a low contact resistance to the drain electrode 66, the data pad 64, and the gate pad 24 made of aluminum through the contact auxiliary layers 210 and 610, and stably. It is characterized by contact. In addition, the present invention is advantageous in simplifying the process because it is not necessary to perform a complicated process such as depositing and etching a separate metal layer in order to contact the aluminum-based wiring and the IZO layer or the ITO layer.

In practice, using the method for manufacturing a thin film transistor substrate according to the first embodiment of the present invention, the gate wirings 22, 24, and 26 are formed of aluminum-neodymium (AlNd), and then cleaned with TMAH, and the gate insulating film ( 30), the deposition gas ratio NH ₃ : SiH ₄ was deposited at 4.44: 1, and the transparent conductive material layer was deposited by IZO. As a result, the contact resistance between the gate wiring and the transparent conductive material layer was 10E5 kPa. Came out low and evenly.

In addition, after the data wirings 62 and 64. 65. 66 are formed of chromium (Cr) / aluminum-neodymium (AlNd) using the method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention, TMAH And a protective film 70, the deposition ratio of NH ₃ : SiH ₄ , which is a deposition gas, was deposited at 7.71: 1, and the transparent conductive material layer was deposited by IZO. The contact resistance was as low and uniform as 10E5-10E6 kPa.

In addition, by using the method for manufacturing a thin film transistor substrate according to the first embodiment of the present invention, after forming the date wiring (62, 64. 65. 66) of chromium (Cr) / aluminum-neodymium (AlNd), TMAH 10 seconds after the surface of the data lines 62, 64, 65, and 66 were plasma-treated with SiH ₄ plasma before the protective film 70 was deposited, and the transparent conductive material layer was deposited by IZO. And the contact resistance of the transparent conductive material layer were 10E5 to 10E6 kPa, which was low and uniform.

FIG. 8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are cross-sectional views taken along cut lines VII- ′ and VII- ′, respectively.

Gate wirings 22, 24, 26, and 28 having a thickness of 2500 to 2500 이루어진 made of a low resistance metal material, for example, aluminum or silver, are formed on the insulating substrate 10. The gate wirings 22, 24, 26, 28 are held in parallel with the gate line portions 22, 24, 26 and the gate line 22, which are composed of the gate line 22, the gate pad 24, and the gate electrode 26. The storage electrode 28 for capacitors is included.

The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed in a double layer or more structure in addition to the single layer structure.                     

The first contact auxiliary layer 210 made of a conductive material such as aluminum-silicon nitride (SiAlON) is formed on the surfaces of the gate lines 22, 24, 26, and 28.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 1500 to 4000 GPa made of silicon nitride or the like covers the gate wirings 22, 24, 26, 28.

On the gate insulating layer 30, semiconductor patterns 42 and 48 having a thickness of 800 to 1500 Å made of a semiconductor material, for example, amorphous silicon, are formed, and an example of a semiconductor material doped with impurities is formed on the semiconductor patterns 42 and 48. For example, the resistive contact layer patterns 55, 56, and 58 having a thickness of 500 to 800 탆 made of amorphous silicon doped with impurities are formed.

The semiconductor patterns 42 and 48 include a semiconductor pattern 42 for a thin film transistor and a semiconductor pattern 48 for a storage capacitor, which are regions between the source electrode 65 and the drain electrode 66, that is, the channel region of the thin film transistor. Except for the above, the data lines 62, 64, 65, 66, 68 and the ohmic contact layer patterns 55, 56, 58 have the same shape. That is, the semiconductor capacitor pattern 48 for the storage capacitor is the same as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, whereas the semiconductor pattern 42 for the thin film transistor has the data line 62 described later. ), The same as the data line portions 62, 64, 65, 66 formed by the data pad 64, the source electrode 65, and the drain electrode 66, but between the source electrode 65 and the drain electrode 66. It further includes a region defined as a channel of the thin film transistor located.

On the ohmic contact layer patterns 55, 56, and 58, a metal material 601 of molybdenum series, titanium series, tantalum series or chromium series, and an aluminum series layer of aluminum such as aluminum or an aluminum alloy The double-layered data lines 62, 64, 65, 66 and 68 are formed.

The data lines 62, 64, 65, 66, and 68 are formed of data lines 62 formed in the vertical direction, data pads 64, source electrodes 65 and drain electrodes 66 of the thin film transistors. (62, 64, 65, 66) and a conductor pattern 68 for a storage capacitor which are located on the storage electrode 28 are included.

Here, the ohmic contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the lower semiconductor patterns 42 and 48 and the upper data lines 62, 64, 65, 66, and 68. And the same shape as that of the data wirings 62, 64, 65, 66, and 68. At this time, one ohmic contact layer pattern 55 is in contact with the integral data line 62, the data pad 64 and the source electrode 65, and the other ohmic contact layer pattern 56 is connected to the drain electrode ( 66, and another contact layer pattern 58 is in contact with the conductor pattern 68 for the storage capacitor.

On the surface of the aluminum based layer 602 of the data lines 62, 64, 65, 66, and 68, a second contact auxiliary layer 610 made of a conductive material such as aluminum-silicon nitride oxide (SiAlON) is formed. have.

A protective film 70 made of an insulating material such as silicon nitride is formed on the exposed front surface of the substrate including the data lines 62, 64, 65, 66, and 68.

The passivation layer 70 includes first, fourth and third contacts exposing the drain electrode 66, the conductive pattern 68 for the storage capacitor, and the second contact auxiliary layer 610 on the surface of the data pad 64. Holes 72, 78, and 76 are formed, and in the passivation layer 70 and the gate insulating layer 30, second contact holes 74 exposing the first contact auxiliary layer 210 existing on the surface of the gate pad 24. ) Is formed.

Further, on the passivation layer 70, a pixel electrode 82, an auxiliary gate pad 84, and an auxiliary data pad 86 made of IZO or ITO are formed. The pixel electrode 82 is electrically connected to the drain electrode 66 and the conductor pattern 68 for the storage capacitor through the first and fourth contact holes 72 and 78, and the image signal from the data line 62. Received. In addition, the auxiliary gate pad 84 and the auxiliary data pad 86 are electrically connected to the gate pad 24 and the data pad 64 through the second and third contact holes 74 and 76.

In the present invention, the pixel electrode 82 and the auxiliary data pad 86 are directly connected to the drain electrode 66 and the conductive pattern 68 for the storage capacitor and the data pad 64 through the second contact auxiliary layer 610. And the auxiliary gate pad 84 directly contacts the gate pad 24 through the first contact auxiliary layer 210. Since a transparent conductive material such as IZO or ITO is in contact with a conductive material such as aluminum-silicon nitride film (SiAlON) with low contact resistance, in the present invention, the pixel electrode 82 made of IZO or ITO, an auxiliary data pad The 86 and the auxiliary gate pad 84 may include a drain electrode 66 made of aluminum series, a conductive pattern 68 for a storage capacitor, a data pad 64, and a gate pad through the contact auxiliary layers 210 and 610. 24) It has a low contact resistance and makes stable contact.                     

Next, a method of manufacturing the thin film transistor substrate according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 11A to 18C and FIGS. 8, 9 and 10.

First, as shown in FIGS. 11A, 11B, and 11C, a metal material having a low resistance characteristic, for example, an aluminum based layer is deposited on the substrate 10, and then etched by a photolithography process using a mask. 10) the gate wirings 22, 24, 26, 28 are formed. At this time, the gate wirings 22, 24, 26, 28 are formed with gate lines 22, 24, 26 made of gate lines 22, gate pads 24, gate electrodes 26, and storage electrodes for storage capacitors ( 28).

Subsequently, an alkaline solution is used to clean the surfaces of the gate wirings 22, 24, and 26.

Next, a gate insulating film 30 made of an insulating material, for example, silicon nitride, is deposited. In this case, a first contact auxiliary layer 210 made of a conductive material such as aluminum-silicon nitride oxide (SiAlON) is also formed on the surfaces of the gate lines 22, 24, 26, and 28 together with the gate insulating layer 30.

The gate insulating film 30 is performed immediately after cleaning the surface of the gate wirings 22, 24, 26, and 28 to eliminate the possibility of forming a natural oxide film caused by exposing the gate wirings 22, 24, 26, and 28 to the atmosphere. It is desirable to minimize it.

The gate insulating film 30 is formed by CVD deposition using a mixed gas of NH ₃ and SiH ₄ at 270 ° C. or higher. At this time, the surface of the gate wirings 22, 24, 26, 28 is made into a silicon-rich atmosphere to deposit the gate insulating film 30. In this case, while the gate insulating film 30 covering the gate wirings 22, 24, 26, and 28 is formed, the surface of the gate wirings 22, 24, 26, and 28 is directly connected to the aluminum-silicon nitride film (SiAlON). A first contact auxiliary layer 210 made of the same conductive material is also formed.

Aluminum-silicon nitride film (SiAlON) is formed by the reaction of aluminum, nitrogen, oxygen and silicon, and aluminum or silicon-silicon nitride film (SiAlON) formed by increasing the content of aluminum or silicon has lower contact with ITO or IZO. Contact with resistance. Since the aluminum content is limited by the gate wirings 22, 24, 26, and 28, in order to increase the content of silicon in the present invention, the surface of the gate wirings 22, 24, 26, and 28 is made to have a silicon-rich atmosphere. To create process conditions.

In the deposition of the gate insulating film 30, as a method for making the surface of the gate wirings 22, 24, 26, and 28 into a silicon-rich atmosphere, the content ratio of the reaction gas used to deposit the gate insulating film 30 is determined. Adjust

For example, gate wiring using a mixed gas having a high silicon content, for example, a mixed gas in which the ratio of NH ₃ : SiH ₄ is 10: 1 or less (eg, 3: 1 or 5: 1). The gate insulating film 30 is deposited by making the surface of (22, 24, 26, 28) a silicon-rich atmosphere. In this case, the content of silicon is greatly increased as compared with the conventional silicon content ratio for depositing the gate insulating film 30.

In addition, when depositing the insulating film 30, another method for making the surface of the gate wirings 22, 24, 26, 28 become a silicon-rich atmosphere, before the gate insulating film 30 is deposited, the gate wirings 22, 24. , 26, 28) is treated with silicon plasma for at least 10 seconds. In this case, silicon is abundantly present near the surface of the gate wirings 22, 24, 26, and 28.

As described above, in the case of depositing the gate insulating film 30 in a silicon-rich atmosphere, the aluminum-silicon nitride film directly covering the surface of the gate wirings 22, 24, 26, and 28 while the gate insulating film 30 is formed ( SiAlON, that is, the first contact auxiliary layer 210 is formed. Since the contact sentry layer 210 is in contact with the transparent conductive material layer formed later with low contact resistance, the contact auxiliary layer assists the contact between the gate wirings 22, 24, 26, 28 and the transparent conductive material layer. Function

Subsequently, when annealing is performed in the range of 250 to 350 ° C. for 30 minutes to 2 hours, the resistance characteristic of the first contact auxiliary layer 210 is further stabilized by the annealing.

12A, 12B, and 12C, the semiconductor patterns 42 and 48, the ohmic contact layer patterns 55, 56, and 58, and the data wirings 62, 64, 65, of the multilayer structure are formed on the gate insulating layer 30. 66, 68).

At this time, the data lines 62, 64, 65, 66, and 68 are formed of the data line 62, 64, 65 consisting of the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66. 66 and a storage electrode 68 for the storage capacitor.

The ohmic contact layer patterns 55, 56, and 58 having the same pattern are in contact with the lower end of the data wires 62, 64, 65, 66, and 68, and the ohmic contact layer patterns 55, 56, and 58 are in contact with the bottom of the data line 62, 64, 65, 66, and 68. The semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are in contact with each other. The thin film transistor semiconductor pattern 42 is the same as the data line portions 62, 64, 65, and 66, and further includes a region defined as a channel of the thin film transistor positioned between the source electrode 65 and the drain electrode 66. Include.

The data lines 62, 64, 65, 66, and 68, the ohmic contact layers 55, 56, and 58, and the semiconductor patterns 42 and 48 may be formed using only one mask. This will be described with reference to FIGS. 13A to 17B.

First, as shown in FIGS. 13A and 13B, the semiconductor layer 40 and the semiconductor layer 50 doped with impurities are successively deposited on the gate insulating film 30 using chemical vapor deposition. Subsequently, after depositing a metal layer 601 made of molybdenum series, titanium series, tantalum series, or chromium series, an aluminum series layer 602 made of aluminum series such as aluminum-neodymium is deposited thereon.

Next, as shown in FIGS. 14A and 14B, a photoresist film is coated on the aluminum-based layer 601 and then irradiated with light through a mask (not shown), followed by development to develop the photoresist patterns 112 and 114. Form. In this case, the photoresist patterns 112 and 114 may have a first portion 112 of the photoresist layer positioned at the data line portion A between the channel portion C of the thin film transistor, that is, between the source electrode 65 and the drain electrode 66. It is formed to be thicker than the second portion 114 of the positioned photosensitive film, and the other portion (B) is formed so as not to remain. The ratio of the thickness of the first portion 112 of the photosensitive film of the second portion 114 of the photosensitive film should be different depending on the process conditions in the etching process, which will be described later, but the thickness of the second portion 114 is determined by the first portion 112. It is preferable to set it as 1/2 or less of thickness.

As such, photoresist patterns having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) directly exposed to the light, and the polymers are completely decomposed because the amount of light is less at the portion (B) corresponding to the slit pattern or translucent film. The polymer is hardly decomposed in the part A covered by the light shielding film. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

When the selective exposed photoresist is developed, only portions where polymer molecules are not decomposed remain, and a photoresist having a thickness thinner than a portion that is not irradiated with light is left in the central portion irradiated with little light.

Next, as shown in FIGS. 15A and 15B, the exposed aluminum series layer 602 of the other portion B and the lower metal layer 601 are etched using the photoresist patterns 112 and 114 as masks. The semiconductor layer 50 doped with impurities below the semiconductor layer 50 is exposed.

In this way, only the conductor patterns 67 and 68 in the channel portion C and the data wiring portion A remain, and the conductive layer in the other portion B is removed, and the semiconductor doped with impurities located below it. Layer 50 is revealed. The conductor pattern 68 is a conductor pattern for the storage capacitor, and the conductor pattern 67 is a data wiring metal layer in which the source electrode 65 and the drain electrode 66 are not separated yet and exist in an integrated state.

Next, as shown in FIGS. 16A and 16B, the semiconductor layer 50 doped with the exposed impurities of the other portion B and the semiconductor layer 40 thereunder together with the second portion 114 of the photoresist film. Simultaneously removed by dry etching. The etching may be performed under the condition that the photoresist patterns 112 and 114, the semiconductor layer 50 and the semiconductor layer 40 doped with impurities are simultaneously etched, and the gate insulating layer 30 is not etched. It is preferable to etch under the conditions in which the etching ratio with respect to (112, 114) and the semiconductor layer 40 is substantially the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness.

When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the second portion 114 of the photoresist layer is the sum of the thicknesses of the semiconductor layer 40 and the semiconductor layer 50 doped with impurities. It must be less than or equal to

In this case, the second portion 114 of the photoresist film positioned in the channel portion C is removed to expose the conductor pattern 67 of the channel portion C, and the semiconductor layer 50 doped with impurities in the other portion B. ) And the semiconductor layer 40 are removed to reveal the gate insulating film 30 thereunder. On the other hand, since the first portion 112 of the photosensitive film of the data wiring portion A is also etched, the thickness becomes thin.

In this step, the semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are completed.

The ohmic contact layer 57 is formed on the thin film transistor semiconductor pattern 42 in the same pattern as the semiconductor pattern 42. The ohmic contact layer 58 is also formed on the semiconductor capacitor 48 for the storage capacitor. It is formed in the same pattern as 48).

Subsequently, residues of the second portion of the photoresist film remaining on the surface of the conductor pattern 67 of the channel portion C are removed by ashing.

Next, as shown in FIGS. 17A and 17B, the double layer conductor pattern 67 positioned in the channel portion C using the first portion 112 of the remaining photoresist pattern as a mask and the ohmic contact layer thereunder. The pattern 57 is removed by etching.

In this case, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to a certain thickness. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the first portion 112 of the photoresist pattern is etched to expose the lower data lines 62, 64, 65, 66, and 68. It is a matter of course that the photosensitive film pattern is thick so that there is no.

In this way, the source electrode 65 and the drain electrode 66 are separated from the conductor pattern 67 to complete the data line 62, the source electrode 65, and the drain electrode 68. The patterns 55, 56 and 58 are completed.

Finally, when the first portion 112 of the photosensitive film pattern remaining in the data wiring portion A is removed by an ashing operation, a cross-sectional structure as shown in FIGS. 12B and 12C can be obtained.

Next, as shown in Figs. 18A, 18B, and 18C, the surface of the data lines 62, 64, 65, and 66 is cleaned using an alkaline solution.

Subsequently, a protective film 70 made of an insulating material, for example, silicon nitride, is deposited. At this time, the second contact auxiliary layer 610 made of a conductive material such as aluminum-silicon nitride (SiAlON) is also formed on the surfaces of the data lines 62, 64, 65, 66, and 68 together with the passivation layer 70. .

The protective film 70 is formed immediately after cleaning the surfaces of the data wires 62, 64, 65, 66, and 68, so that the natural oxide film caused by the exposure of the data wires 62, 64, 65, 66, and 68 to the atmosphere. It is desirable to minimize the possibility of formation.

The protective film 70 is formed by CVD deposition using a mixed gas of NH ₃ and SiH ₄ at 270 ° C. or higher. At this time, the surface of the data lines 62, 64, 65, 66, 68 is made into a silicon-rich atmosphere to deposit the protective film 70. In this case, while the protective film 70 covering the data wires 62, 64, 65, 66, and 68 is formed, the aluminum-silicon nitride oxide film ( A second contact auxiliary layer 610 made of a conductive material such as SiAlON is also formed.

Aluminum-silicon nitride film (SiAlON) is formed by the reaction of aluminum, nitrogen, oxygen and silicon, and aluminum or silicon-silicon nitride film (SiAlON) formed by increasing the content of aluminum or silicon has lower contact with ITO or IZO. Contact with resistance. Since the aluminum content is limited by the data wirings 62, 64, 65, 66, and 68, in order to increase the content of silicon in the present invention, the surface of the data wirings 62, 64, 65, 66, and 68 may be made of silicon. It is to create process conditions that make the atmosphere rich.

In the deposition of the passivation layer 70, as a way to make the surface of the data lines 62, 64, 65, 66, and 68 a silicon-rich atmosphere, the content ratio of the reaction gas used to deposit the passivation layer 70 is determined. Adjust

For example, using a mixed gas having a high silicon content, for example, a mixed gas in which the ratio NH ₃ : SiH ₄ is 10: 1 or less (eg, 3: 1 or 5: 1). The protective film 70 is deposited by making the surfaces of the wirings 62, 64, 65, 66, 68 rich in silicon.

In addition, during the deposition of the protective film 70, another method for making the surface of the data wirings 62, 64, 65, 66, and 68 into a silicon-rich atmosphere, before the deposition of the protective film 70, is performed. , 65, 66) were treated with silicon plasma for at least 10 seconds. In this case, silicon is abundantly present near the surface of the data lines 62, 64, 65, and 66.

As described above, in the case of depositing the gate protective film 70 in a silicon-rich atmosphere, the aluminum-silicon nitride film directly covering the surface of the data lines 62, 64, 65, 66, and 68 while the protective film 70 is formed. (SiAlON), that is, the second contact auxiliary layer 610 is formed. Since the contact sentry layer 610 is in contact with the transparent conductive material layer formed later with low contact resistance, the contact assisting aids the contact between the data lines 62, 64, 65, 66 and 68 and the transparent conductive material layer. It functions as a layer.

Subsequently, when annealing is performed in the range of 250 to 350 ° C. for 30 minutes to 2 hours, the resistance characteristic of the second contact auxiliary layer 610 is further stabilized by the annealing.

Subsequently, the passivation layer 70 and the gate insulating layer 30 are etched by a photolithography process using a mask to form a portion of the second contact auxiliary layer 610 on the drain electrode 66 and the conductive pattern 68 for the storage capacitor. A third contact hole 76 exposing the first contact hole 72 and the fourth contact hole 78 exposing the second contact auxiliary layer 610 on the data pad 64, and forming a gate pad ( 24) forming a second contact hole 74 exposing the first contact auxiliary layer 210 above.

Next, as shown in FIGS. 8, 9, and 10, the IZO layer or the IZO layer is deposited and etched by a photolithography process using a mask to form the drain electrode 66 and the conductor pattern for the storage capacitor ( An auxiliary gate pad 84 and an auxiliary data pad 86 electrically connected to the pixel electrode 82, the gate pad 24, and the data pad 64 that are electrically connected to each other are formed. In this case, the pixel electrode 82 is electrically connected to the drain electrode 66 and the conductor pattern 68 for the organic capacitor through the first and fourth contact holes 72 and 78, and the auxiliary gate pad 84 and The auxiliary data pad 86 is electrically connected to the gate pad 24 and the data pad 64 through the second and third contact holes 74 and 76.

Since a transparent conductive material such as IZO or ITO is in contact with a conductive material such as aluminum-silicon nitride film (SiAlON) with low contact resistance, in the present invention, the pixel electrode 82 made of IZO or ITO, an auxiliary data pad The 86 and the auxiliary gate pad 84 may include a drain electrode 66 made of aluminum series, a conductive pattern 68 for a storage capacitor, a data pad 64, and a gate pad through the contact auxiliary layers 210 and 610. It is characterized by stable contact with low contact resistance. In addition, the present invention is advantageous in simplifying the process because it is not necessary to perform a complicated process such as depositing and etching a separate metal layer in order to contact the aluminum-based wiring and the IZO layer or the ITO layer.

In practice, using the method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention, the gate wirings 22, 24, 26, 28 are formed of aluminum-neodymium (AlNd), and then cleaned with TMAH, and the gate When the insulating film 30 is deposited, the deposition ratio of NH ₃ : SiH ₄ , which is a deposition gas, is deposited at 4.44: 1, and the transparent conductive material layer is deposited by IZO. As a result, the contact resistance between the gate wiring and the transparent conductive material layer is 10E5. 낮 came out low and evenly.

According to the method of manufacturing a thin film transistor substrate according to the present invention, a transparent conductive material layer such as IZO or ITO can be directly contacted with an aluminum-based wiring, and a complex process such as depositing and etching a separate metal layer is performed. It is advantageous in simplifying the process because the aluminum-based wiring and the IZO layer or the ITO layer can be contacted without the

Claims (19)

delete delete Forming a gate wiring including a gate line and a gate electrode on the substrate, Forming a first contact auxiliary layer and a gate insulating layer covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Forming a data line including a data line crossing the gate line, a source electrode connected to the gate line, and a drain electrode corresponding to the source electrode; Forming a protective film covering the semiconductor pattern and the data wiring; Forming a first contact hole exposing the drain electrode, Forming a pixel electrode electrically connected to the drain electrode through the first contact hole, In the forming of the first contact auxiliary layer and the gate insulating film, a method of manufacturing a thin film transistor substrate using a mixed gas having a gas ratio of NH ₃ : SiH ₄ of 10: 1 or less. Forming a gate wiring including a gate line and a gate electrode on the substrate, Surface treating the gate wiring with a SiH ₄ plasma, Forming a first contact auxiliary layer and a gate insulating layer covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Forming a data line including a data line crossing the gate line, a source electrode connected to the gate line, and a drain electrode corresponding to the source electrode; Forming a protective film covering the semiconductor pattern and the data wiring; Forming a first contact hole exposing the drain electrode, Forming a pixel electrode electrically connected to the drain electrode through the first contact hole. The method of claim 3 or 4, And after the gate wiring is formed, cleaning the gate wiring with an alkaline solution. The method of claim 3 or 4, After the gate insulating film is formed, the method of manufacturing a thin film transistor substrate further comprising the step of performing a heat treatment at 250 ~ 350 ℃. The method of claim 3 or 4, And forming a second contact auxiliary layer on the surface of the data line in the process of forming the passivation layer. delete In claim 7, In the forming of the protective film, a method of manufacturing a thin film transistor substrate using a mixed gas in which NH ₃ : SiH ₄ is mixed in a ratio of 10: 1 or less. In claim 7, And surface treating the data line with a SiH ₄ plasma prior to forming the passivation layer. In claim 7, And cleaning the data line with an alkaline solution before forming the passivation layer. In claim 7, After the protective film is formed, the method of manufacturing a thin film transistor substrate further comprising the step of performing a heat treatment at 250 ~ 350 ℃. The method of claim 3 or 4, The semiconductor pattern and the data line are formed together using a single mask. In claim 13, And the mask is patterned to include a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In claim 13, And the semiconductor pattern and the data line are formed together using photoresist patterns having different thicknesses formed using the mask. The method of claim 15, The photoresist pattern may include a first portion having a first thickness on the upper portion of the data line and a second portion having a second thickness thinner than the first thickness on the upper portion between the source electrode and the drain electrode. Manufacturing method. In claim 7, And the first contact hole exposes a portion of a second contact auxiliary layer on the drain electrode, and the pixel electrode contacts a portion of a second contact auxiliary layer on the drain electrode. The method of claim 17, The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line. Forming a second contact hole exposing the gate pad in the passivation layer and the gate insulating layer in forming the first contact hole, and forming a third contact hole exposing the data pad in the passivation layer, Forming a pixel electrode to form an auxiliary gate pad electrically connected to the gate pad through the second contact hole and an auxiliary data pad electrically connected to the data pad through the third contact hole; Method of manufacturing a substrate. The method of claim 18, The second contact hole exposes a first contact auxiliary layer portion on the gate pad, the auxiliary gate pad contacts a first contact auxiliary layer portion on the gate pad, and the third contact hole is on the data pad. Exposing a second contact auxiliary layer portion of the substrate, wherein the auxiliary data pad contacts a second contact auxiliary layer portion on the data pad.

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