KR100653985B1 - Method for forming transistor of semiconductor device - Google Patents

Abstract

The present invention relates to a transistor manufacturing method of a semiconductor device that improves the refresh characteristics by preventing the dopant increase in the storage node portion to reduce the leakage current.

This method includes performing a plurality of ion implantation processes in an active region of a silicon substrate divided into an active region and a device isolation region, forming a buffer oxide layer defining a bit line contact portion on the silicon substrate, and forming a substrate on which the buffer oxide layer is formed. Selectively epitaxially growing silicon on the surface to form a silicon epitaxial layer, planarizing the silicon epitaxial layer to the point where the upper surface of the buffer oxide layer is exposed, and implanting channel ions into the silicon epitaxial layer using the buffer oxide layer as a mask. Removing the buffer oxide film, forming a gate pattern on the substrate from which the buffer oxide film has been removed, partially overlapping the silicon epitaxial film, forming a gate spacer on the sidewall of the gate pattern, and forming a gate spacer. Source / drain formation ions are applied to the substrate using a mask. And forming a source / drain junction.

Threshold Voltage, Asymmetric Junction, Stepped Profile, Diffusion-Proof, Silicon Epitaxial

Description

Method for forming transistor of semiconductor device             

1A and 1B are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to the prior art.

2 is a simulation result diagram showing an electric field distribution of a transistor manufactured by a transistor manufacturing method of a semiconductor device according to the prior art.

3A through 3H are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

   -Explanation of symbols for the main parts of the drawings-

100: silicon substrate 110: device isolation film

120: buffer film 130: silicon epitaxial film

140: gate pattern 150: thermal oxide film

165: gate spacer 170: source / drain junction

The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device to improve the refresh characteristics by preventing the dopant increase in the storage node portion to reduce the leakage current.

A DRAM device is a memory device that stores data and retrieves it if necessary. The DRAM device is composed of a set of cells, which are composed of a capacitor that stores data, and a transistor that switches out a charge stored in the capacitor.

The data storage of the DRAM device means that the charge is accumulated in the capacitor, and ideally, the charge stored in the capacitor does not disappear. However, as the design rule of the device decreases recently, the channel length between the source and the drain also decreases gradually, increasing the threshold voltage or increasing the leakage current in the junction region. As a result, data stored in the capacitor is lost, and the refresh characteristic of recharging the lost charge is degraded.

In order to prevent such deterioration of the refresh characteristics, the channel threshold voltage adjustment ion implantation was additionally performed in the state of partially blocking the storage node, that is, the junction portion to which the capacitor and the contact are to be connected, in this case. In the case of threshold voltage ion implantation, there is a problem in that the concentration of the channel region is rapidly increased, thereby lowering the refresh characteristics.

Hereinafter, with reference to the accompanying drawings will be described in detail the problem according to the transistor manufacturing method of the semiconductor device according to the prior art.

1A and 1B are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to the prior art.

Although not shown in the drawing, various ion implantation processes, that is, well, field stop, punch stop, and channel threshold voltage regulation ion implantation processes are performed in the silicon substrate 10.

As shown in FIG. 1A, after the gate oxide layer 20 and the gate polysilicon (not shown) are deposited on the silicon substrate 10, the gate electrode 30 is formed by performing a selective photographing and etching process. do. Thereafter, an insulator is deposited on the entire surface of the substrate 10 on which the gate electrode 30 is formed, and then selectively etched to form a gate spacer 40 made of an insulator on the sidewall of the gate electrode 30.

Subsequently, an impurity ion implantation process is performed on the silicon substrate 10 using the gate spacer 40 as an ion implantation mask to form a junction region 50 for forming a cell junction region.

Subsequently, as shown in FIG. 1B, after the photoresist pattern 60 is formed on the silicon substrate 10 to expose only the surface of the substrate 10 of the bit line contact portion, which is a region to be joined with the subsequent bit line, the channel threshold is formed. By further performing ion implantation, an asymmetric junction structure is formed.

FIG. 2 is a simulation result diagram showing electric field distribution of a transistor manufactured by a transistor manufacturing method of a semiconductor device according to the prior art. As shown here, the expected threshold voltage Vt is ~ 1.7E13V, and the maximum electric field is ~ 0.58. It can be seen that the electric field in the junction region is high at about MV / cm.

As described above, according to the transistor manufacturing method of the semiconductor device according to the related art, as the design rule of the DRAM decreases, when only the bit line contact portion, which is a junction portion to be contacted with the bit line, is further ion implanted, The impurity concentration of is abnormally increased, and a steep doping profile between the channel and the junction is formed to increase the electric field. As such, when the electric field increases, the refresh characteristics also decrease.

In addition, as the DRAM design rules decrease, the process of removing the mask formed to expose only the bit line contact portion for the additional ion implantation process becomes difficult. That is, there is a problem that all of the photosensitive material constituting the mask is left without being etched.

An object of the present invention is to solve the above problems, by preventing ion diffusion between the storage node portion and the bit line contact portion, thereby increasing the concentration of the storage node portion to secure the refresh characteristics of the DRAM memory cell It is to provide a method for manufacturing a transistor.

In order to achieve the above object, the present invention includes performing a plurality of ion implantation processes in an active region of a silicon substrate, which is divided into an active region and an isolation region, and a buffer oxide layer defining bit line contact portions on the silicon substrate. Forming a silicon epitaxial film by selectively epitaxially growing silicon on the surface of the substrate on which the buffer oxide film is formed, and planarizing the silicon epitaxial film to a point where the upper surface of the buffer oxide film is exposed; Implanting channel ions into the silicon epitaxial layer using the buffer oxide layer as a mask, removing the buffer oxide layer, and forming a gate pattern partially overlapping the silicon epitaxial layer on the substrate from which the buffer oxide layer is removed. And a gate spacer on sidewalls of the gate pattern. And the step of forming the gate and spacers as a mask, ion implantation for source / drain formed on the substrate to provide a method of manufacturing a semiconductor transistor device comprising the steps of forming a source / drain junction.

Here, as the plurality of ion implantation processes, it is preferable to proceed with a well, field stop, punch stop, and channel ion implantation process.

In addition, forming a gate pattern overlapping the silicon epitaxial layer by a predetermined portion on the substrate from which the buffer oxide layer is removed may sequentially deposit a gate oxide layer, a gate conductive layer, and a gate hard mask on the entire surface of the substrate from which the buffer oxide layer is removed. Forming a photoresist pattern defining a gate formation region on the gate hard mask, wherein the gate formation region overlaps a predetermined portion of the silicon epitaxial layer, and using the photoresist pattern as a mask as a gate hard mask and a gate. It is preferable to include the step of sequentially etching the conductive film and the gate oxide film.                     

In addition, after the forming of the gate pattern, the thermal oxidation process may be further included. In the etching process for forming the gate pattern, it is preferable to compensate the etching damage of the substrate.

In addition, the buffer oxide film is formed to have a thickness of 10 ~ 25002, the thickness of the silicon epitaxial film can also be adjusted to a thickness of 10 ~ 2500Å, it is possible to adjust the height of the vertical surface of the channel having a stepped profile. The vertical surface of the stepped profile serves as a diffusion barrier to prevent ion diffusion.

In addition, the planarization of the silicon epitaxial layer is preferably performed using any one of a chemical mechanical polishing process and an etch back process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

A method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention will now be described in detail with reference to the drawings.

3A through 3H are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, various ion implantation processes, that is, wells, field stops, punch stops, and the like, are formed in an active region of a silicon substrate 100 divided into an active region and an element isolation region by the device isolation layer 110. The channel ion implantation process is performed. In this case, the implanted ions mainly use ions such as B, P, Ar, and BF ₂ . In addition, the present invention injects the dose of 1E12 ~ 1E17 with energy of 5 KeV ~ 500 KeV in order to adjust the doping profile of the junction region formed by the implanted ions.

The buffer oxide film 120 is deposited to a predetermined thickness on the silicon substrate 100 having various ion implantation processes. At this time, the thickness of the buffer oxide film 120 serves to adjust the thickness of the silicon epitaxial film to be described later. That is, the thickness of the silicon epitaxial film is determined by determining the height of the vertical surface of the stepped profile that serves to prevent the ion diffusion, the buffer oxide film 120 is preferably formed to have a thickness of 10 ~ 25002.

Subsequently, a photoresist pattern 125 defining a bit line contact portion is formed on the buffer oxide layer 120, and then the buffer oxide layer 120 is etched using an etching mask to etch the silicon substrate 100 in a region corresponding to the bit line contact portion. ) Reveals the surface.

Thereafter, the photoresist pattern 125 is removed.

As shown in FIG. 3B, the silicon on the surface of the silicon substrate 100 exposed by the buffer oxide film 120 is selectively epitaxially grown, and then planarized to the point where the surface of the buffer oxide film 120 is exposed to silicon growth. The film 130 is formed. In this case, the silicon growth layer 130 is planarized by any one of a chemical mechanical polishing process or an etch back process.

As shown in FIG. 3C, an additional channel ion implantation process is performed on the silicon growth layer 130 using the buffer oxide layer 120 as an ion implantation mask to reduce the resistance of the bit line contact portion. At this time, in the additional channel ion implantation process, the present invention can simplify the overall process by using the buffer oxide film 120 as an ion implantation mask without a separate ion implantation mask process.

Subsequently, the buffer oxide layer 120 is removed to expose the silicon substrate 100.

As shown in FIG. 3D, a thermal oxidation process is performed on the substrate 100 from which the buffer oxide film 120 is removed to form a gate oxide film 143.

3E, a gate conductive film 145 and a gate hard mask 147 are sequentially stacked on the gate oxide film 143, and then a photoresist pattern defining a gate formation region thereon (not shown). Not formed). In this case, the gate formation region defines a portion of the silicon epitaxial layer 130 and a portion of the substrate 100 on which the silicon epitaxial layer 130 is not formed.

Subsequently, the gate hard mask 147, the gate conductive layer 145, and the gate oxide layer 143 are sequentially etched using the photoresist pattern (not shown) as a mask to form the gate pattern 140. In this case, the gate pattern 140 forms a channel having a stepped profile by the silicon epitaxial layer 130 disposed below. Accordingly, the present invention blocks the diffusion of ions implanted into the bitline contact portion into the storage node portion by the vertical plane of the stepped profile forming the channel, thereby preventing the concentration of the storage node portion from increasing.

Thereafter, as illustrated in FIG. 3F, a thermal oxidation process is performed on the substrate 100 on which the gate pattern 140 is formed to form a thermal oxide film 150, and then the substrate on which the thermal oxide film 150 is formed ( An insulating film 160 such as nitride or oxide is deposited on the substrate 100.

As shown in FIG. 3G, the insulating film 160 and the thermal oxide film 150 are selectively etched to sequentially stack the thermal oxide film 150 and the insulating film 160 from sidewalls of the gate pattern 140. The gate spacer 165 is formed.

As shown in FIG. 3H, source / drain forming ions are implanted into the substrate 100 using the gate spacer 165 as an ion implantation mask to form a source / drain region 170.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

As described above, in the present invention, the channel length of the gate is formed to have a stepped profile by using a silicon epitaxial film, so that the length of the channel is increased, thereby securing a large amount of current.

In addition, the present invention uses a vertical surface of a channel having a stepped profile as a diffusion barrier, thereby preventing ions from diffusing into the storage node portion during additional ion implantation into the bit line contact portion, thereby preventing the concentration of the storage node portion from increasing.

Accordingly, the refresh characteristic of the DRAM cell may be improved by minimizing electric field concentration and leakage current.

Claims (6)

Performing a plurality of ion implantation processes in the active region of the silicon substrate divided into the active region and the device isolation region; Forming a buffer oxide layer defining a bit line contact portion on the silicon substrate; Selectively epitaxially growing silicon on the surface of the substrate on which the buffer oxide film is formed to form a silicon epitaxial film; Planarizing the silicon epitaxial layer to a point where the upper surface of the buffer oxide layer is exposed; Implanting channel ions into a silicon epitaxial layer using the buffer oxide layer as a mask; Removing the buffer oxide layer; Forming a gate pattern partially overlapping the silicon epitaxial layer on the substrate from which the buffer oxide layer is removed; Forming a gate spacer on sidewalls of the gate pattern; and And forming a source / drain junction by implanting source / drain forming ions into the substrate using the gate spacer as a mask. The method of claim 1, The plurality of ion implantation processes are wells, field stops, punch stops, and channel ion implantation processes. The method of claim 1, Forming a gate pattern partially overlapping the silicon epitaxial layer on the substrate from which the buffer oxide layer has been removed includes sequentially depositing a gate oxide layer, a gate conductive layer, and a gate hard mask on the entire surface of the substrate from which the buffer oxide layer has been removed. And forming a photoresist pattern defining a gate formation region on the gate hard mask, wherein the gate formation region overlaps a predetermined portion of the silicon epitaxial layer, and using the photoresist pattern as a mask as a gate hard mask and a gate conductive layer. And sequentially etching the gate oxide film. The method of claim 1, And further performing a thermal oxidation process after the forming of the gate pattern. The method of claim 1, The buffer oxide film is a transistor manufacturing method of a semiconductor device formed to have a thickness of 10 ~ 2500Å. The method of claim 1, The planarizing of the silicon epitaxial layer is a transistor manufacturing method of a semiconductor device using any one of a chemical mechanical polishing process or an etch back process.

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