KR100605434B1 - Stacked type semiconductor device - Google Patents

Abstract

A stacked semiconductor device comprising a plurality of semiconductor integrated circuit devices including a semiconductor integrated circuit chip and having specifications, wherein at least three or more predetermined semiconductor integrated circuit devices of the semiconductor integrated circuit devices are arranged according to the order of the specification values. It is stacked.

Stacked Devices, 3D Stacked, Specifications, LSI Chip, Multichip Devices

Description

Multilayer Semiconductor Device {STACKED TYPE SEMICONDUCTOR DEVICE}

1A is a diagram schematically illustrating a cross-sectional configuration as an example of a stacked semiconductor device according to an embodiment of the present invention.

1B is a diagram schematically illustrating a cross-sectional configuration of another stacked semiconductor device according to an embodiment of the present invention.

1C is a diagram schematically illustrating a cross-sectional configuration of another stacked semiconductor device according to an embodiment of the present invention.

2A and 2B schematically illustrate an example of Type 1 of a stacked semiconductor device according to an embodiment of the present invention.

3A and 3B schematically illustrate another example of Type 1 of a stacked semiconductor device according to an embodiment of the present invention.

4A and 4B schematically illustrate another example of Type 1 of a stacked semiconductor device according to an embodiment of the present invention.

5A and 5B schematically illustrate another example of Type 1 of a stacked semiconductor device according to an embodiment of the present invention.

6A and 6B schematically illustrate another example of Type 1 of a stacked semiconductor device according to an embodiment of the present invention.

7A and 7B schematically illustrate an example of type 2 of a stacked semiconductor device according to an embodiment of the present invention.

8 is a diagram schematically illustrating an example of a type 3 of a stacked semiconductor device according to an embodiment of the present invention.

9 is a diagram schematically illustrating an example of a type 4 of a stacked semiconductor device according to an embodiment of the present invention.

10 is a diagram schematically illustrating another example of a type 4 of a stacked semiconductor device according to an embodiment of the present invention.

FIG. 11 is a diagram schematically illustrating another example of a type 4 of a stacked semiconductor device according to an embodiment of the present invention. FIG.

12 is a diagram schematically illustrating a cross-sectional configuration of another stacked semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

BS: Base Board

S1 to S5: semiconductor integrated circuit chip

TP: Through Plug

CN: Conductive Connecting Material

TM: Terminal

The present invention relates to a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices are stacked.

Background Art With the miniaturization and weight reduction of electronic devices such as portable devices and mobile devices, miniaturization and high integration are required for electronic components constituting electronic devices. Therefore, there is a demand for a stacked semiconductor device (multi-chip device) in which a semiconductor integrated circuit chip (LSI chip) is stacked three-dimensionally.

However, no effective stacking method for semiconductor integrated circuit chips has been proposed.

A first aspect of the present invention is a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices including a semiconductor integrated circuit chip and having specifications are stacked, wherein at least three or more predetermined semiconductor integrated circuit devices of the semiconductor integrated circuit devices are provided. Laminated | stacked according to the magnitude | size order of the said specification value.

A second aspect of the present invention is a stacked semiconductor device in which at least three or more semiconductor integrated circuit devices including a semiconductor integrated circuit chip and having specifications are stacked, wherein the lowermost or uppermost semiconductor integrated circuit is among the semiconductor integrated circuit devices. The specification value of the device is minimum or maximum.

A third aspect of the present invention is a stacked semiconductor device in which at least two or more semiconductor integrated circuit devices including a semiconductor integrated circuit chip and having specifications are stacked, wherein the adjacent semiconductor integrated circuit devices are adjacent to each other. It is electrically connected by the electrically conductive material which penetrates a device, and specification values other than the size of the lowermost or uppermost semiconductor integrated circuit device among the said semiconductor integrated circuit devices are minimum or maximum.

A fourth aspect of the present invention is a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices including a semiconductor integrated circuit chip and having specifications are stacked, wherein the stacked semiconductor device includes a predetermined number of specific semiconductors among the semiconductor integrated circuit devices. Has a group comprising integrated circuit devices, wherein the predetermined number is two or more and less than the total number of the semiconductor integrated circuit devices, the specification values of the specific semiconductor integrated circuit devices are all within a predetermined range, and the specific semiconductor integrated circuit The devices are stacked in series.

A fifth aspect of the present invention is a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices including a semiconductor integrated circuit chip are stacked, wherein the specific semiconductor integrated circuit devices having the largest amount of transmission and reception of signals among the semiconductor integrated circuit devices are sequentially stacked. It is.

According to a sixth aspect of the present invention, there is provided a first semiconductor integrated circuit device including a semiconductor integrated circuit chip and provided in the same plane, and a plurality of first semiconductor integrated circuit devices including a semiconductor integrated circuit chip and interposed therebetween. A stacked semiconductor device comprising a plurality of second semiconductor integrated circuit devices.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1A illustrates a first configuration example of a stacked semiconductor device according to an embodiment of the present invention.

A plurality of semiconductor integrated circuit chips (LSI chips) S1 to S5 are stacked on the base substrate BS. The base substrate BS functions as a motherboard and is provided with a terminal TM and a wiring pattern, a power supply, and the like (not shown).

The semiconductor integrated circuit chips S1 to S5 are provided with a through plug TP made of a conductive material penetrating the semiconductor integrated circuit chip. The conductive connecting material CN is connected between the terminal TM of the base substrate BS and the lowermost through plug TP and between the adjacent through plugs TP. For example, a ball grid array BGA is used for the conductive connection material CN. Signals are transmitted and received between the base substrate and the semiconductor integrated circuit chip and between the semiconductor integrated circuit chip through the through plug TP and the conductive connecting material CN.

1B illustrates a second configuration example of the stacked semiconductor device according to the embodiment of the present invention.

On the base substrate BS, a plurality of semiconductor integrated circuit chips S1 to S5 are stacked. The base substrate BS functions as a motherboard and is provided with a terminal TM and a wiring pattern, a power supply, and the like (not shown).

The semiconductor integrated circuit chips S1 to S5 are mounted on the substrates SBA1 to SBA5. On the board | substrates SBA1-SBA5, the wiring (not shown) which electrically connects the terminal of semiconductor integrated circuit chips S1-S5 and the through plug TP mentioned later is provided. Substrates SBB1 to SBB5 are interposed between the base substrate BS and the lowermost substrate SBA1 and between adjacent substrates SBA1 to SBA5. Holes are formed in the centers of the substrates SBB1 to SBB5, and semiconductor integrated circuit chips S1 to S5 are disposed corresponding to the holes.

The through plugs TP made of a conductive material penetrating these substrates are provided on the substrates SBA1 to SBA5 and the substrates SBB1 to SBB5. The conductive connecting material CN is connected between the terminal TM of the base substrate BS and the through plug TP of the lowest layer, and between the adjacent through plugs TP. For example, soldering is used for the conductive connecting material CN. Signal transmission and reception are performed between the base substrate and the semiconductor integrated circuit chip and between the semiconductor integrated circuit chip through the through plug TP, the conductive connecting member CN, and the wirings (not shown) provided on the substrates SBA1 to SBA5. .

For example, as shown in Fig. 1A, when the semiconductor integrated circuit chips S1 to S5 are directly connected by a through plug, the semiconductor integrated circuit chip itself corresponds to the semiconductor integrated circuit device.

For example, as shown in FIG. 1B, when the substrates SBA1 to SBA5 on which the semiconductor integrated circuit chips S1 to S5 are mounted are connected by a through plug, a semiconductor integrated circuit chip (for example, A substrate with a chip composed of S1) and a substrate (for example, SBA1) corresponds to a semiconductor integrated circuit device. In such a board | substrate with a chip, the specification of a semiconductor integrated circuit device may be a specification of a semiconductor integrated circuit chip itself, or the specification of a board | substrate with a chip may be sufficient.

In summary, the semiconductor integrated circuit device may be a semiconductor integrated circuit chip or may be a device including a semiconductor integrated circuit chip and other elements (substrate and the like). In addition, the specification of a semiconductor integrated circuit device may be the specification of a semiconductor integrated circuit chip (case 1), or may be the specification of the device containing a semiconductor integrated circuit chip and another element (substrate etc.) (case 2).

In the following description, for the sake of simplicity, case 1 is assumed and described, but the same applies to case 2.

Hereinafter, the basic type of the lamination method of the laminated semiconductor device according to the present embodiment will be described.

(Type 1)

In this type, at least three or more predetermined semiconductor integrated circuit chips are stacked in the order of the specification values.

2A and 2B schematically illustrate an example of this type. The horizontal axis represents the stacking order of the semiconductor integrated circuit chips S1 to S5, and the vertical axis represents the specification values (power consumption, etc.) of the semiconductor integrated circuit chips S1 to S5. In the example of FIGS. 2A and 2B, the specification value is increased or decreased in the stacking range of the chips S2 to S4, but of course, the specification value may be increased or decreased in the stacking range of four or more layers.

3A and 3B schematically illustrate another example of this type. Thus, two or more chips (S3 and S4 in the example of the figure) having the same specification may be adjacent to each other. In other words, even in the case of a plurality of chips having the same specification value, the property value may be increased or decreased in at least two or more steps.

4A and 4B schematically illustrate another example of this type. This example is an example in which at least one of the lowermost chip S1 and the uppermost chip S5 is included in three or more predetermined chips. In the example of the figure, S1 and S2 are included together in three or more predetermined chips, and the specification value increases or decreases over the entire lamination range. 3A and 3B, chips with the same specification may be adjacent to each other.

5A and 5B schematically illustrate another example of this type. This example is an example in which at least one of the lowermost chip S1 and the uppermost chip S5 is not included in three or more predetermined chips. In the example of the figure, the chip S3 having the maximum or minimum specification value exists at positions other than the lowermost chip S1 and the uppermost chip S5. 3A and 3B, chips with the same specification may be adjacent to each other.

6A and 6B schematically illustrate another example of this type. This example is an example in which a specific chip is sandwiched between predetermined chips. In the example of the figure, the specific chip S3 has a larger or smaller specification value than the chips S2 and S4 adjacent to both sides of the chip S3. For chips S1, S2, S4 and S5 other than the specific chip S3, the specification value is increased or decreased.

(Type 2)

In this type, among the semiconductor integrated circuit chips of the whole stacking range, the specification value of the lowermost or uppermost semiconductor integrated circuit chip is minimum or maximum. The total number of stacks of semiconductor integrated circuit chips is two or more or three or more.

7A and 7B schematically illustrate an example of this type. In the example shown in the figure, the specification value of the lowermost chip S1 is minimum or maximum, but of course, the specification value of the uppermost chip S5 may be minimum or maximum.

In the case where the specification value of the lowermost chip S1 is minimum (or maximum), the chip having the smallest (or large) specification value may be the uppermost chip S5 next. On the contrary, when the specification value of the uppermost chip S5 is minimum (or maximum), the chip having the smallest (or large) specification value may be the lowermost chip S1 next. Moreover, when there are many chips with the minimum or maximum specification value, you may arrange them in the lowest layer and the uppermost layer, and FIG. 5A and 5B are such an example, and correspond to this type of example.

(Type 3)

In this type, a group of specifications having a predetermined value constitutes a group, and at least two or more semiconductor integrated circuit chips included in the group are successively stacked.

Fig. 8 schematically shows an example of this type. In the example shown in Fig. 8, chips S1 and S2, chips S3 and S4, and chips S5 and S6 each constitute one group. In the example shown in Fig. 8, although the number of chips included in one group is two, three or more chips may be used. Moreover, the number of chips contained in each group may differ. And chips which are not included in any group may exist.

(Type 4)

This type is to arrange one or two or more specific semiconductor integrated circuit chips in a predetermined stacking position among a plurality of semiconductor integrated circuit chips.

9 schematically shows an example of this type. In this example, among a plurality of chips, specific semiconductor integrated circuit chips (in the example shown in Fig. 9, S2 and S3) are successively stacked. Typically, among the chips, specific chips having the largest amount of signal transmission / reception are stacked successively. Further, the nearest ones of the specification values may be laminated successively (this is also included in the type 3 grouping concept).

Fig. 10 schematically shows another example of this type. In the example of the figure, the chip S1 which has the largest amount of transmission / reception with the base board | substrate BS among all the chips is arrange | positioned in the position closest to the base board | substrate BS. The concept shown in FIG. 10 is also included in the concept of type 2. FIG.

Fig. 11 schematically shows another example of this type. In the example of the figure, the chip S5 with the largest amount of transmission / reception of signals with the outside among all the chips is arranged at the position farthest from the base substrate BS. The concept shown in Fig. 11 is also included in the type 2 concept.

In each of the above types, the specifications of the semiconductor integrated circuit chip include power consumption, operating voltage, operating voltage number, operating current, guaranteed operating temperature, generated electromagnetic wave amount, operating frequency, dimensions, connection terminal number, connection terminal pitch, thickness, And an amount of transmission and reception of signals to and from the base substrate on which the semiconductor integrated circuit chip is mounted.

As described above, a multilayer semiconductor device having excellent performance can be obtained by optimizing a stacking method of a semiconductor integrated circuit chip.

In addition, the above-described lamination method is effective for a stacked semiconductor device which makes electrical connections between adjacent chips using a through plug as shown in Fig. 1A or 1B. For example, when electrical connection between chips is made by wire bonding, there are limitations based on the dimensions of the chip, for example, disposing a small chip on a large chip from the viewpoint of ease of wire bonding. Therefore, it can be considered that the degree of freedom is small in the chip stacking method. When the electrical connection between the chips is performed by the through plugs, there are no restrictions as described above. For example, it is possible to adopt a configuration example as shown in Fig. 1C. It is possible to apply various lamination methods as described above.

Hereinafter, the specific lamination method of a semiconductor integrated circuit chip with respect to each specification value is demonstrated. In addition, the lamination | stacking method demonstrated in the following specific example is an example, It is possible to employ | adopt the various lamination | stacking methods as basically demonstrated by each said type.

(Example 1)

In this example, the chips are stacked based on the power consumption (for example, maximum power consumption) of the semiconductor integrated circuit chips S1 to S5.

In the case of stacking a plurality of chips incorporating different functions, it is necessary to perform heat dissipation (cooling) of the entire module in consideration of power consumption of each chip, in other words, in consideration of heat flow generated from each chip. Thus, each chip is stacked as in the following specific example 1A or specific example 1B.

(Example 1A)

In this example, chips are stacked in the order of the chips with the highest power consumption, that is, the amount of heat generated, in the heat diffusion and propagation directions. For example, each chip is stacked as shown in Fig. 4B.

In this way, by disposing a chip with high power consumption on the base substrate BS side, that is, a heat sink side, heat of a chip with high power consumption can be quickly and efficiently sent to the heat sink. In other words, the temperature of the chip with high power consumption can be reduced quickly. Therefore, since heat of a chip with low power consumption can be efficiently sent to the heat sink, heat dissipation (cooling) of the entire module can be efficiently performed.

And when the heat sink is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip | tip, you may laminate | stack each chip like FIG. 5B. In addition, in this example, it is also possible to laminate | stack each chip like FIG. 2B, FIG. 3B, FIG. 6B, FIG. 7B, etc., for example.

(Example 1B)

In this example, chips are stacked in the order of the chips with the lowest power consumption, that is, the amount of heat generated in the diffusion propagation direction of heat. For example, each chip is stacked as shown in Fig. 4A.

If a chip with a large amount of power consumption exists on the base substrate BS side, that is, a heat sink side, the chip with a lot of power consumption may act as a thermal diffusion barrier. As a result, heat diffusion into the heat sink may be disturbed from the chip with low power consumption.

In this example, since a chip with low power consumption is disposed on the side of the base substrate BS, the chip with high power consumption does not become a heat diffusion barrier. Therefore, due to the temperature gradient, heat diffusion can be efficiently performed from a chip with a large amount of power to a small chip with a heat sink, and heat dissipation (cooling) of the entire module can be efficiently performed.

And when the heat sink is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip | tip, you may laminate | stack each chip like FIG. 5A. In other examples, the chips can be stacked in the same manner as in FIGS. 2A, 3A, 6A, 7A, and the like.

(Example 2)

In this example, the chips are stacked based on the operating voltage (power supply voltage) and the operating voltage number (power supply voltage) of the semiconductor integrated circuit chips S1 to S5.

When a plurality of chips are stacked and modularized, the operating voltage or the number of operating voltages may be different in each chip. In such a case, it is necessary to stack each chip in consideration of voltage drop and connection with a power supply. Therefore, each chip is laminated as in the following specific example 2A to specific example 2D.

(Example 2A)

In this example, chips are stacked in the order of the chips having the highest operating voltage (power supply voltage). For example, as shown in FIG. 4B, each chip is stacked. When a plurality of operating voltages exist in one chip, for example, the operating voltages of the respective chips are compared based on the maximum operating voltage.

When the voltage is supplied to each chip from the base substrate, that is, the power supply substrate, the voltage is supplied to the chip on the side far from the power supply via the chip in the middle. In general, chips with lower operating voltages also have lower allowable operating voltages. For this reason, when the operating voltage of the chip on the way to become the voltage supply path is low, it leads to a decrease in reliability such as malfunction or damage.

In this example, a chip having a high operating voltage is arranged on the base substrate BS side. Therefore, a voltage higher than the operating voltage of the chip in the middle is not supplied to the chip in the middle of the voltage supply path from the power source of the base substrate. Therefore, the fall of the reliability, such as a malfunction or damage, can be prevented.

And when the power supply board is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip, you may laminate | stack each chip like FIG. 5B. In addition, in this example, each chip can also be laminated | stacked like FIG. 2B, FIG. 3B, FIG. 6B, FIG.

(Example 2B)

In this example, chips are stacked in the order of the chips having the lowest operating voltage (power supply voltage). For example, as shown in FIG. 4A, each chip is stacked. When a plurality of operating voltages exist in one chip, for example, the operating voltages of the respective chips are compared based on the maximum operating voltage.

When a voltage is supplied to each chip from the base board, that is, the power board, the chip on the side farther from the power source tends to have a voltage drop because the voltage supply path is longer than that of the chip on the side close to the power source. The effect of the voltage drop is greater for chips with lower operating voltages. In this example, a chip having a low operating voltage is arranged on the base substrate BS side. Therefore, in the case of the whole module, the influence of a voltage drop can be reduced and reliability improvement can be aimed at.

And when the power supply board is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip | tip, you may laminate | stack each chip like FIG. 5A. In addition, in this example, it is also possible to stack chips as shown in Figs. 2A, 3A, 6A, 7A and the like.

(Example 2C)

In this example, when the number of operating voltages (power supply voltage) of each chip is different, for example, when a chip having one operating voltage and a chip having two operating voltages are stacked, a chip having a large number of operating voltages is used. It is arrange | positioned at the board | substrate BS side, ie, a power supply board side. For example, as shown in FIG. 4B, each chip is stacked.

By arranging the chips having a large number of operating voltages on the base substrate BS side, that is, on the power supply substrate side, the number of through plugs for supplying the power supply voltage from the base substrate BS to each chip can be reduced. Therefore, the process cost can be reduced and the reliability can be improved.

And when the power supply board is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip, you may laminate | stack each chip like FIG. 5B. In addition, in this example, each chip can be laminated | stacked like FIG. 2B, FIG. 3B, FIG. 6B, FIG. 7B, etc., for example.

(Example 2D)

In this example, in the case where the module is constituted by chips of a single operating voltage number, for example, a plurality of chips having close or identical operating voltages are grouped to stack chips in the group continuously. For example, each chip is stacked as shown in FIG.

For example, by forming groups of chips having the same operating voltage, the power supply terminals can be made common, and the number of through plugs for supplying the power supply voltage from the base substrate BS to each chip can be reduced. Therefore, reduction of process cost and improvement of reliability can be aimed at.

(Example 3)

In this example, the chips are stacked based on the operating currents of the semiconductor integrated circuit chips S1 to S5.

If the operating current of each chip is different, it is necessary to stack each chip in consideration of the operating current of each chip. Therefore, each chip is laminated as follows.

In this example, when the operating currents of the respective chips are different, the chips are stacked in the order in which the operating currents (for example, the maximum operating currents) are large. For example, as shown in FIG. 4B, each chip is stacked.

When current is supplied to each chip from the base substrate, that is, the power substrate, the current supply path is longer in the chip on the side farther from the power substrate than in the chip on the side near the power substrate. For this reason, the resistance component in the current supply path increases in the chip on the side far from the power supply board. If a chip with a large operating current is placed on a chip far from the power supply, the voltage loss increases due to the relationship of voltage = current X resistance. In this example, a chip with a large operating current is arranged on the base substrate BS side, that is, on the power supply substrate side. In other words, since the chip with the large operating current is disposed at the position where the resistance component of the current path becomes small, the loss of voltage can be minimized.

And when the power supply board is arrange | positioned at the both sides (chip S1 side and chip S5 side) of a chip, you may laminate | stack each chip like FIG. 5B. In addition, in this example, it is also possible to laminate | stack each chip like FIG. 2B, FIG. 3B, FIG. 6B, FIG. 7B, etc., for example.

(Example 4)

In this example, the chips are stacked based on the guaranteed operating temperatures of the semiconductor integrated circuit chips S1 to S5.

In the case of stacking and modularizing a plurality of chips, it is necessary to secure the reliability of the entire module in consideration of the guaranteed operating temperature (reliability criteria) of each chip. Therefore, each chip is laminated as follows.

In this example, when the guaranteed operating temperatures between the chips are different, the chips having the guaranteed operating temperatures close to or identical to each other are grouped, and chips in the group are successively stacked to ensure reliability standards. For example, it corresponds to the concept of FIG. The chip having the lowest guaranteed operating temperature may be arranged at the stacking position where the temperature is lowest (lamination position designed to be the lowest temperature). The guaranteed operating temperature of the entire module may be adjusted to the standard of the chip having the lowest guaranteed operating temperature.

By stacking each chip in consideration of the guaranteed operating temperature in this manner, it is possible to secure the reliability of the entire module (extending the lifespan, etc.), and it is easy to perform the reliability management by stacking chips close to the guaranteed operating temperature. Lose.

(Example 5)

In this example, the chips are stacked based on the transmission and reception of signals of the semiconductor integrated circuit chips S1 to S5.

In the case of stacking and modularizing a plurality of chips, there is a possibility that a module may be degraded or malfunction due to signal delay or the like unless the transmission and reception of signals such as a signal transmission / reception amount and a signal transmission / reception rate are considered. Therefore, each chip is laminated | stacked like the following specific examples 5A-5C.

(Example 5A)

In this example, specific chips having the closest relationship are arranged adjacent to each other. That is, as shown in Fig. 9, specific chips having the closest relationship (S2 and S3 in the example of Fig. 9) are disposed adjacent to each other.

For example, the largest chips are placed adjacent to each other. Specifically, a logic chip having a signal processing function and a memory chip (cache chip such as DRAM or SRAM) that transmits and receives data between the logic chips are stacked adjacently. On the contrary, a chip which does not transmit or receive a signal, for example, a power supply control chip, is disposed at a distant position. If another chip is placed between the chips for transmitting and receiving data, the processing speed is slowed down by signal delay, and the function of the entire system is degraded. By arranging the chips as described above adjacent to each other, the processing speed can be improved and the function of the entire system can be improved.

In the case where signals are transmitted and received to each other, chips closest to the operating frequency may be arranged adjacent to each other. In this way, the timing shift at the time of data transmission / reception can be suppressed to the minimum and the function of the whole system can be improved.

(Example 5B)

In this example, a chip (e.g., a signal processing chip for processing a high-speed signal) having the most transmission / reception with the motherboard, which is an interface substrate, is arranged adjacent to the motherboard. That is, as shown in Fig. 10, the chip S1 having the most transmission and reception of signals to and from the motherboard (base substrate BS) is arranged adjacent to the motherboard. Thereby, the signal delay in the transmission and reception of the signal to and from the motherboard can be suppressed to a minimum, and the function of the entire system can be improved.

(Example 5C)

In this example, for example, as shown in Fig. 11, the chip S5, which has a large amount of transmission and reception of signals to and from the outside, is arranged at a position farthest from the motherboard (base substrate BS). For example, a chip for processing external signals such as image signals, audio signals, and antenna signals of CCD and CMOS sensors is arranged on the uppermost layer. With this arrangement, when a CCD, an antenna, or the like is provided above the chip S5, the signals can be transmitted and received between the chip S5 and the outside without being shielded by the other chips S1 to S4. have.

(Example 6)

In this example, the chips are laminated on the basis of the generated electromagnetic waves of the semiconductor integrated circuit chips S1 to S5.

When a plurality of chips are stacked and modularized, the operating voltage also decreases with the increase in the amount of transmission and reception of signals and the speed of the signals between the chips. As a result, each chip is susceptible to noise. That is, there is a possibility that malfunction, sound, or distortion of an image may occur due to electromagnetic interference (EMI) generated by electromagnetic waves generated from each chip, power line, ground line, or the like. Therefore, each chip is laminated as in the following specific examples 6A and 6B.

(Example 6A)

In this example, a chip with a large amount of electromagnetic wave generation is arranged at a position close to the motherboard. For example, as shown in Fig. 7B, the chip S1 having the greatest amount of electromagnetic waves is disposed at the position closest to the base substrate BS. Conversely, you may arrange | position the chip with the smallest generation amount of electromagnetic waves at the position farthest from a base substrate.

For example, it is based on a chip having the highest amount of generated electromagnetic waves (for example, a chip having a large operating current in which a large current flows instantaneously, a sensor chip, a voice / image processing chip, a chip processing a signal of a transmitting / receiving antenna, etc.). The chip is placed closest to the substrate, and the chip susceptible to electromagnetic waves is placed at a position far from the base substrate. By arranging in this way, the influence of the electromagnetic waves from the chip S1 to the other chips S2 to S5 can be suppressed, and malfunctions due to the electromagnetic waves can be prevented.

In addition to Fig. 7B, it is also possible to stack each chip in accordance with various stacking methods as described in Types 1 and 2 above.

(Example 6B)

In this example, a chip susceptible to electromagnetic waves is disposed at a position farthest from the motherboard (base substrate), for example, in accordance with Type 2. In this way, chips that are susceptible to electromagnetic waves (eg chips for sensors, chips for processing audio, image processing, chips for transmitting and receiving signals, etc.) are stacked away from power substrates (base substrates) that are sources of EMI By arrange | positioning at the position, malfunction etc. by electromagnetic waves can be prevented.

(Example 7)

In this example, the chips are stacked based on the chip dimensions of the semiconductor integrated circuit chips S1 to S5.

Since the dimensions of each chip to be stacked may not all be the same, chips of various dimensions are often stacked. When various chip dimensions are mixed in this way, if the stacking order of each chip is not appropriate, problems such as cracking due to stress, poor connection, and increase in manufacturing cost arise.

Since modules stacked in three dimensions are generally high-performance and high-density, the number of connection terminals between the module and the outside increases considerably. In the package of such a module, a connection called a flip chip is used in which the connection terminals are arranged in a lattice form. Moreover, resin, such as glass epoxy, is used for a motherboard and a package from a weight and a price. Since the ratio of the thermal expansion coefficient between such a resin and a semiconductor such as silicon or GsAs is about five times, a stress due to the difference in the thermal expansion coefficient is generated between them. In the three-dimensional stacked module, since the terminal pitch is rapidly abrupt compared to the two-dimensional module in which each chip is arranged side by side in the horizontal direction, a reliable connection between the motherboard and the chip becomes difficult.

In view of this, in this example, as shown in Fig. 7B, the chip S1 having the largest chip size is disposed at the stacking position closest to the base substrate BS (mother board). The following method is mentioned as a determination method of a chip dimension.

(Example 7A)

In this example, the chip dimensions are determined based on the length of each chip's long side (the long side of the rectangle when the chip surface perpendicular to the stacking direction is called a rectangle, or any side when the chip surface is square). The chip with the longest side is placed at the position closest to the base substrate (mother board).

(Example 7B)

In this example, the length of the long side of each chip (the long side of the rectangle when the chip surface perpendicular to the stacking direction is called a rectangle, or any side when the chip surface is a square) and the short side (the vertical side in the stacking direction) The chip dimensions are determined based on the sum of the lengths of the short sides of the rectangle when the chip surface is a rectangle, or any side when the chip surface is a square), and the chip having the largest sum is the most on the base substrate. Place it close to you.

(Example 7C)

In this example, the chip size is determined based on the area of each chip (the area of the chip surface perpendicular to the stacking direction), and the chip having the largest area is placed at the position closest to the base substrate.

Thus, in this example, by stacking each chip in the order of the largest chip size, connection failure due to stress is suppressed, and the reliability of the entire module can be improved.

In addition, also in the specific example 7, it is possible to laminate | stack each chip according to the various lamination | stacking methods similar to what was demonstrated by type 1 and type 2.

(Example 8)

In this example, each chip is laminated on the basis of the number of connection terminals or the connection terminal pitch of the semiconductor integrated circuit chips S1 to S5.

Each chip to be stacked is connected to each other or between the chip and the motherboard (base substrate) by a connection terminal such as a through plug. However, since the number of terminals and the terminal pitch of each chip to be stacked are not the same, chips of various terminal numbers and terminal pitches are mixed and stacked in many cases. When various numbers of terminals and terminal pitches are mixed in this manner, if the stacking order of each chip is not appropriate, problems such as cracking due to stress, poor connection, and increase in manufacturing cost arise. That is, the same problem as described in Embodiment 7 occurs. In addition, the number of terminals for transmitting and receiving signals to and from the motherboard varies according to each chip, and unless the proper stacking order is selected, efficient placement of each chip and improvement of the performance of the entire module cannot be achieved. In this example, each chip is laminated as in the following specific examples 8A and 8B.

(Example 8A)

In this example, for example, as shown in Fig. 7B, the chip S1 having the largest number of terminals is disposed at the position closest to the base substrate BS (motherboard). More specifically, the chip with the largest number of terminals connected to the motherboard is arranged at the stacking position closest to the motherboard. By arranging in this way, efficient connection can be performed and the performance of the whole module can be improved.

(Example 8B)

In this example, for example, as shown in Fig. 7B, the chip having the widest terminal pitch is arranged at the position closest to the motherboard. In terms of the number of terminals, the chip with the smallest number of terminals is placed at the position closest to the motherboard. This arrangement reduces the stress between the motherboard and the chip. Therefore, since a highly reliable connection can be made, the reliability of the whole module can be improved.

In addition, also in the specific example 8, it is possible to laminate | stack each chip according to the various lamination | stacking methods as demonstrated in Type 1 and Type 2.

(Example 9)

In this example, the chips are stacked based on the chip thicknesses of the semiconductor integrated circuit chips S1 to S5.

Since the thickness of each chip to be stacked is not all the same, chips of various thicknesses are often mixed and stacked. In the case where the thicknesses of the various chips are mixed in this way, problems such as cracking due to stress and poor connection may occur if the stacking order of the respective chips is not appropriate. That is, since the module laminated | stacked in three dimensions aims at high function and high density, it is preferable to make each chip thickness as thin as possible, but when chip thickness is too thin, chip strength becomes weak. Therefore, there exists a problem that the reliability of the whole module falls. In view of this, in this example, the chips are stacked as in the following specific examples 9A and 9B.

(Example 9A)

In this example, for example, as shown in Fig. 7B, the chip S1 having the thickest chip thickness is disposed at the position closest to the base substrate BS (motherboard).

Since the absolute value of the yield stress (strength) with respect to loads such as bending and stress is proportional to the thickness, the strength of the thick chip is generally large. In the modules stacked three-dimensionally, the thermal expansion coefficients described above are different, so that the stress between the chip of the lowest layer and the motherboard is the greatest. Therefore, by arranging the thickest chip on the motherboard side, the strength of the entire module is improved, and a highly reliable three-dimensional module can be obtained.

(Example 9B)

In this example, for example, as shown in Fig. 7A, the chip having the thinnest chip thickness is disposed at the position closest to the base substrate BS (mother board).

As described above, the absolute value of the yield stress (strength) is proportional to the thickness, but the thinner is superior in the displacement with respect to the stress, that is, the bending point. In the case of a chip which is easy to bend, that is, a thin chip, even if a stress acts on the motherboard, the chip is less likely to be broken due to the flexibility of the chip itself. Therefore, the strength of the whole module is improved and a highly reliable three-dimensional module can be obtained.

In addition, also in the specific example 9, it is possible to laminate | stack each chip according to the various lamination | stacking methods as demonstrated in Type 1, Type 2.

(Example 10)

In this example, each chip is arranged in consideration of the positional relationship of the semiconductor integrated circuit device chips.

As described above, since the dimensions of each chip to be stacked are not all the same, chips of various sizes are often stacked and stacked. When various chip dimensions are mixed in this way, an efficient arrangement cannot be performed unless the stacking method of each chip is appropriate.

In this example, a large number of small chips are placed between the large chips. 12 is a diagram illustrating an example thereof. About the code | symbol, it is the same as FIG. 1A. As shown in Fig. 12, a large chip is disposed at the positions of the chip S1 and the chip S3, and a large number of chips S2 are small at the position between the chip S1 and the chip S3. In the horizontal direction (same plane). By performing such arrangement, each chip can be arranged in a high density, and a high performance module can be obtained.

According to the present invention, it is possible to provide an effective stacking method of a semiconductor integrated circuit chip.

Claims (27)

A stacked semiconductor device in which a plurality of semiconductor integrated circuit devices each including a semiconductor integrated circuit chip and having specifications are stacked. At least three or more semiconductor integrated circuit devices are laminated | stacked according to the order of the magnitude | size of the numerical value of the said specification, in which at least two of them differ from the said specification, The above specification includes power consumption, operating voltage, operating voltage, operating current, guaranteed operating temperature, generated electromagnetic wave, operating frequency, connecting terminal number, connecting terminal pitch, thickness, and the base substrate on which the semiconductor integrated circuit device is mounted. A multilayer semiconductor device, which is any one of a transmission / reception amount of a signal and a transmission / reception amount of a signal to the outside. The method of claim 1, The semiconductor integrated circuit device further comprises a substrate, wherein the semiconductor integrated circuit chip is mounted on the substrate. The method of claim 1, And said specification is a specification of said semiconductor integrated circuit chip. The method of claim 1, At least three or more semiconductor integrated circuit devices are stacked in succession. The method of claim 1, At least three or more semiconductor integrated circuit devices are laminated by sandwiching fourth semiconductor integrated circuit devices other than the at least three or more semiconductor integrated circuit devices. The method of claim 1, And at least three or more semiconductor integrated circuit devices are configured to include at least one semiconductor integrated circuit device of a lowermost layer and an uppermost layer of the semiconductor integrated circuit devices. The method of claim 1, The adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material passing through the semiconductor integrated circuit device. delete A stacked semiconductor device in which at least three or more semiconductor integrated circuit devices each including a semiconductor integrated circuit chip and having specifications are stacked; Among the semiconductor integrated circuit devices, at least two of them have different specifications, and the specifications of the lowermost or uppermost semiconductor integrated circuit device are minimum or maximum, The above specification includes power consumption, operating voltage, operating voltage, operating current, guaranteed operating temperature, generated electromagnetic wave, operating frequency, connecting terminal number, connecting terminal pitch, thickness, and the base substrate on which the semiconductor integrated circuit device is mounted. The amount of transmission / reception of the signal and the amount of transmission / reception of the signal to the outside are any of the stacked semiconductor devices. The method of claim 9, The semiconductor integrated circuit device further comprises a substrate, wherein the semiconductor integrated circuit chip is mounted on the substrate. The method of claim 9, And said specification is a specification of said semiconductor integrated circuit chip. The method of claim 9, The adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material passing through the semiconductor integrated circuit device. delete A stacked semiconductor device comprising at least two semiconductor integrated circuit devices having a semiconductor integrated circuit chip and having specifications, wherein: The semiconductor integrated circuit device includes a conductive material penetrating through the semiconductor integrated circuit device, wherein the semiconductor integrated circuit devices are electrically connected by the conductive material, and the specifications of the lowermost or uppermost semiconductor integrated circuit device are minimal. Or maximum The above specification includes power consumption, operating voltage, operating voltage, operating current, guaranteed operating temperature, generated electromagnetic wave, operating frequency, connecting terminal number, connecting terminal pitch, thickness, and the base substrate on which the semiconductor integrated circuit device is mounted. The amount of transmission / reception of the signal and the amount of transmission / reception of the signal to the outside are any of the stacked semiconductor devices. The method of claim 14, The semiconductor integrated circuit device further comprises a substrate, wherein the semiconductor integrated circuit chip is mounted on the substrate. The method of claim 14, And said specification is a specification of said semiconductor integrated circuit chip. delete delete At least three or more semiconductor integrated circuit devices each including a semiconductor integrated circuit chip and having specifications are stacked, and at least two of them are stacked semiconductor devices having different specifications. A group is formed by the semiconductor integrated circuit devices which are at least two or more and less than the total number, wherein the semiconductor integrated circuit devices in the group have their specifications within a predetermined range, and the semiconductor integrated circuit devices are successively stacked. It is The above specification includes power consumption, operating voltage, operating voltage, operating current, guaranteed operating temperature, generated electromagnetic wave, operating frequency, connecting terminal number, connecting terminal pitch, thickness, and the base substrate on which the semiconductor integrated circuit device is mounted. The amount of transmission / reception of the signal and the amount of transmission / reception of the signal to the outside are any of the stacked semiconductor devices. The method of claim 19, The semiconductor integrated circuit device further comprises a substrate, wherein the semiconductor integrated circuit chip is mounted on the substrate. The method of claim 19, And said specification is a specification of said semiconductor integrated circuit chip. delete delete The method of claim 19, The adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material passing through the semiconductor integrated circuit device. delete delete delete

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