KR100413413B1 - Device for demodulating digital vestigial side band - Google Patents

Abstract

PURPOSE: A device for demodulating a digital VSB(Vestigial Side Band) is provided to lower an IF as doubling a clock frequency of an A/D converter, and to perform a VSB demodulation process in a digital area without an interference, thereby exactly maintaining a phase difference of a carrier and improving demodulation performance. CONSTITUTION: An analog processor(200) multiplies the first IF signal by a predetermined frequency, and converts the first IF signal into the second IF signal lower than the first IF signal. A digital processor(220) converts an output of the analog processor(200) into a digital signal, and demodulates the digital signal. The digital processor(220) comprises as follows. An A/D converter(207) doubles an output of a buffer amplifier(206). An LPF(212) decimates demodulated I and Q channel digital signals to sample only one of the signals per symbol, and removes a high band. A timing recoverer(214) recovers a timing used as an A/D clock. An FS synchronous recoverer(215) compensates for signal deterioration. A carrier recoverer(216) recovers a carrier by using the demodulated I and Q channel digital signals.

Description

Digital Residual Sideband Demodulation Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high definition television (HDTV), and more particularly to a digital VSB demodulation device that digitally processes the residual side band (VSB) demodulation in HDTV.

The 8VSB, which is determined by the US HDTV transmission system standard, is a signal transmitted by modulating only the other part of the two side bands generated by amplifying the signal when one of the two side bands generated up and down about the carrier is greatly attenuated. There are 8 levels, and it is used to blow the air over.

Therefore, if the broadcasting station modulates the digital data to 8VSB and blows it through the antenna, it can be received and demodulated and watched by the HDTV receiver in each home.

On the other hand, when performing a VSB modulation in a broadcast station, a pilot signal is loaded and sent to the air in order to accurately demodulate the signal at the receiver.

Since the frequency used for HDTV broadcasting uses the same frequency as current NTSC TV broadcasting, the pilot size should be very small in order not to affect NTSC broadcasting.

Therefore, when two adjacent intervals of the 8 signal levels of 8 VSB are '2', the pilot size is '1.25', so that the power of the transmission signal is increased by 0.3 dB.

FIG. 1 is a block diagram illustrating a conventional VSB demodulation device used by Zenith in the USA. The frequency synthesizer 103 receives a channel tuning signal and generates and outputs a first local frequency (1st LO). By multiplying the broadcast signal input through the 101 and the first local frequency (1st LO) to select only the frequency of the desired broadcast signal and multiply by the second local frequency (2nd LO) output from the voltage controlled oscillator (VCO) 114 The tuner 102 converts an intermediate frequency (IF) signal of a frequency band, which is easy to handle in a general circuit, and removes the remaining sections, leaving only a band in which information exists in the IF signal output from the tuner 102 ( Surface Acoustic Wave (SAW) filter 104, IF amplifier 105 for amplifying the signal output from the SAW filter 104, and the frequency at which the center frequency of the reference oscillator 106 is fixed is 90 ° phase A phase delayer 107 for delaying, a first mixer 108 for multiplying an output signal of the phase delayed reference oscillator 106 with a signal amplified by the IF amplifier 105, and outputting an I channel signal; A second mixer 109 for outputting a Q channel signal by multiplying the output signal of the fixed reference oscillator 106 by the signal amplified by the IF amplifier 105, and a second passive filter to provide a predetermined one of the I channel signals. Automatic frequency control (FCC) filter 110, which passes only the low frequency band signal and simultaneously changes its phase according to the frequency of the I-channel signal, amplifies the output signal of the AFC filter 110 with a predetermined gain. A predetermined limit among the limiter 111 for limiting, the third mixer 112 for multiplying and outputting the Q channel signal of the second mixer 109 and the output signal of the limiter 111, and the output signal of the third mixer 112. that Automatic phase control loop which provides a control signal to the selected signal to pass only the frequency band signals to pass through the carrier so that the correction to the desired frequency to the VCO (114) (Automatic Phase Control; APC filter 113 and a VCO 114 for outputting the second local frequency 2nd L.O. to the tuner 102 under the control of the APC filter 113.

In FIG. 1 configured as described above, broadcast signals in the air are first input to the tuner 102 of the receiver via the antenna 101.

In addition, the frequency synthesizer 103 receives a channel tuning signal selected by a user and generates a first local frequency (1st L.O.) having a frequency difference of 920 MHz from a desired broadcast signal.

The tuner 102 multiplies a plurality of broadcast signals output from the antenna 101 and a first local frequency (1st LO) output from the frequency synthesizer 103 to obtain a frequency of a desired broadcast signal among the signals input through the antenna 101. Let 920MHz.

Then, the frequency of the desired broadcast signal is lowered to an intermediate frequency of 46.69 MHz by multiplying by the second local frequency 2nd L.O. output from the VCO 114.

At this time, since the HDTV broadcast signal has all the information in the 6MHz band from the intermediate frequency of 46.69MHz, the SAW filter 104 removes all remaining sections except for the 6MHz band in which the information exists from the output of the tuner 102.

The output of the SAW filter 104 is amplified by the IF amplifier 105 and then input to the first and second mixers 108 and 109.

On the other hand, the output of the reference oscillator 106 whose center frequency is fixed at 46.69 MHz is input to the second mixer 109 and multiplied by the output of the IF amplifier 105 to generate a Q channel signal.

In addition, the output of the reference oscillator 106 is input to the first mixer 108 with a phase delay of 90 ° in the phase retarder 107.

Here, the phase delayed signal is multiplied with the output signal of the IF amplifier 105 to generate an I channel signal.

On the other hand, the frequency of the pilot inserted in the broadcast station must be exactly at 46.69MHz at the output of the IF amplifier 105 to operate normally at the remaining receiver, which is often not exactly 46.69MHz.

However, since the output frequency of the reference oscillator 106 is fixed at 46.69 MHz, the difference between the two frequencies output from the first and second mixers 108 and 109 when the output frequency of the pilot in the IF amplifier 105 is not 46.69 MHz. As many bits as there are.

The FPLL is used to remove the beat frequency.

That is, the oscillation frequency of the reference oscillator 106 is fixed at 46.69 MHz and the frequency and phase of the IF signal carrier are changed by changing the oscillation frequency of the VCO 114 to remove the bit frequency.

The purpose of the FPLL is to find the direction and magnitude of shifting the oscillation frequency of the VCO 114.

The first and second mixers 108 and 109, the AFC filter 110, the limiter 111, the third mixer 112, and the APC filter 113 are referred to as FPLL described above, and the operation thereof is as follows.

That is, the I-channel signal that is the output of the first mixer 108 has cos (ω i -ω o) t = co Δω t when the output frequency is ω o and the pilot output frequency of the IF amplifier 105 is ω i.

Δω = ω o -ω i (bit frequency).

On the other hand, the Q channel signal that is the output of the second mixer 109 has the form of sin Δωt.

The AFC filter 110 is composed of a second-order passive filter that can lock a bit frequency of ± 100KHz, and also has a characteristic of changing the frequency in phase with the characteristics of the low pass filter (LPF), the I signal A phase value is output for each bit frequency of.

At this time, the output of the AFC filter 110 is input to the limiter 111 is amplified and limited.

The output of the limiter 111 is multiplied by the third mixer 112 and output with the Q channel signal.

The output of the third mixer 112 controls the VCO 114 through an APC filter 113 which limits the band of the signal to 2KHz.

When the bit frequency is present and the output of the limiter 111 is changed, the FLL process is performed. When the output of the limiter 111 is no longer changed, the PLL process is started to correct the phase.

However, the conventional VSB demodulation device has the following problems since the VSB demodulation is performed in the analog domain as shown in FIG.

First, because of the use of analog devices, it is difficult for the I-channel signal and the Q-channel signal to maintain a phase difference of exactly 90 °, thereby demodulating performance.

Second, when designing an application specific integrated circuit (ASIC), it is difficult to integrate and the volume becomes large even if integrated.

Third, the signal characteristic deterioration occurs due to the deterioration of the characteristics of the analog device due to the sensitivity of the temperature characteristics, etc., and it is necessary to continuously adjust finely.

The present invention is to solve the above problems, the object of the present invention is to reduce the intermediate frequency to 5π / 8 and the clock frequency of the analog-to-digital converter to twice the symbol frequency, digital to perform VSB demodulation in the digital domain In providing a VSB demodulation device.

A feature of the digital VSB demodulation device according to the present invention for achieving the above object is 5π which is a second IF signal lower than the first IF signal by multiplying a first frequency input from a predetermined frequency. A low-frequency IF signal output unit for converting to / 8, an A / D converter for sampling a second IF signal output from the low-frequency IF signal output unit at a frequency twice the symbol frequency and converting it into a digital signal, and the A / A channel signal output unit for demodulating the output of the D converter by cos 5π / 8 and sin 5π / 8 to demodulate the baseband I and Q channel digital signals and performing decimation and filter processing to sample only one symbol per symbol; A DS synchronization recovery unit for restoring synchronization existing for each data segment DS using an I-channel digital signal outputted from the channel signal output unit, and a DS synchronization recovery unit existing for each DS recovered in the DS synchronization recovery unit. There is composed, including a timing recovery unit for using the symmetry of the timing synchronizing signal restored, by using the I, Q-channel digital signal demodulation to baseband carrier recovery unit to recover the carrier.

Another feature of the digital VSB demodulator according to the present invention is a low frequency IF which multiplies a first IF signal input from a predetermined frequency and converts it to 5π / 8 which is a second IF signal lower than the first IF signal. An A / D converter for sampling a second IF signal output from the low frequency IF signal output part at a frequency twice the symbol frequency and converting the signal into a digital signal, and cos 5π at the output of the A / D converter. Demodulates the baseband I, Q channel digital signals by multiplying / 8, sin 5π / 8, filters the demodulated I, Q channel digital signals, respectively, and adds the two filtered outputs to eliminate interference signals in the passband. A DS synchronization recovery unit for restoring synchronization existing for each data segment DS using a signal output unit, a channel digital signal output from the channel signal output unit, and a DS synchronization recovery unit; And a carrier recovery unit for restoring the timing by using the symmetry of the synchronization signal existing for each DS, and a carrier recovery unit for recovering the carrier using the baseband demodulated I and Q channel digital signals.

1 is a block diagram of a conventional VSB demodulation device

2 is a block diagram of a digital VSB demodulation device according to the present invention;

3A and 3B are diagrams illustrating a frequency spectrum of the channel signal output unit of FIG. 2.

4A and 4B show examples of coefficients to multiply the first and second mixers of FIG.

FIG. 5 is a block diagram showing an equivalent configuration of the first and second mixers of FIG.

FIG. 6 is a block diagram illustrating a first embodiment of the channel signal output unit of FIG. 2. FIG.

7 is a detailed block diagram of the filter unit of FIG. 6.

FIG. 8 is a block diagram illustrating a second embodiment of the channel signal output unit of FIG. 2. FIG.

9 is a detailed block diagram illustrating an example of the filter unit of FIG. 8.

FIG. 10 is a detailed block diagram illustrating another example of the filter unit of FIG. 8. FIG.

FIG. 11 is a block diagram illustrating a third embodiment of the channel signal output unit of FIG. 2. FIG.

12 is a detailed block diagram of the filter unit of FIG.

FIG. 13 is a block diagram illustrating a fourth exemplary embodiment of the channel signal output unit of FIG. 2. FIG.

14 is a detailed block diagram of the filter unit of FIG. 13.

15 is a block diagram showing another embodiment of the digital VSB demodulation device according to the present invention;

16A to 16G are frequency spectrum diagrams of respective parts of FIG.

17 is a detailed block diagram of a digital carrier recovery unit according to the present invention.

Explanation of symbols for the main parts of the drawings

200: analog processing unit 201: tuner

202: SAW filter 203: AGC amplifier

204 Mixer 205 Low Pass Filter

206: buffer amplifier 220: digital processing unit

207: A / D converter 208: reverse rotation

209: first mixer 210: second mixer

211: phase delay 212: filter

213: DS synchronization recovery unit 214: timing recovery unit

215: FS synchronization recovery unit 216: carrier recovery unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a digital VSB demodulation device according to the present invention.

Referring to FIG. 2, an analog processor 200 for converting a first IF signal by a predetermined frequency to a second IF signal lower than the first IF signal and a digital output for demodulating and demodulating the outputs of the analog processor 200. The digital processing unit 220 is configured.

가 되도록 하는 믹서(204), 상기 믹서(204)에서 출력되는 제 2 IF 신호를 로우패스필터링하는 LPF(205), 및 상기 LPF(205)의 출력을 증폭하는 버퍼 증폭기(206)를 포함하여 구성된다.The analog processing unit 200 selects only a predetermined frequency band among RF signals input through an antenna and filters the first IF signal output through the tuner 201 and the tuner 201 to convert the first IF signal of 46.69 MHz. An SAW filter 202, an amplifier 203 that amplifies the 46.69 MHz first IF signal through the SAW filter 202, and amplifies the amplified first IF signal with a predetermined frequency (cos (ωct)). A second IF signal lower than the first IF signal to be multiplied, i.e.

And a mixer 204 for performing a low pass filtering on the second IF signal output from the mixer 204, and a buffer amplifier 206 for amplifying the output of the LPF 205. do.

(n은 정수)을 곱하여 기저대역의 I 채널 디지털 신호로 복조하는 제 1 믹서(209), 상기

(n은 정수)를 90°위상 지연시켜

로 출력하는 위상 지연기(211), 상기 A/D 변환기(207)의 출력에 상기 위상 지연기(211)에서 출력되는

(n은 정수)을 곱하여 기저대역의 Q 채널 디지털 신호로 복조하는 제 2 믹서(210), 상기 제 1, 제 2 믹서(209,210)에서 복조된 I, Q 채널 채널 디지털 신호에 대해 심볼당 1개만 샘플링하도록 데시메이션한 후 고역 부분을 제거하는 LPF(212), 상기 LPF(212)에서 출력되는 I 채널 디지털 신호를 이용하여 데이터 세그먼트(Data Segment ; DS)마다 존재하는 동기를 복구하는 DS 동기 복구부(213), 상기 DS 동기 복구부(213)에서 복구된 DS 동기를 이용하여 A/D 컨버터(207)의 A/D 클럭(A/D clk)으로 사용할 타이밍을 복구하는 타이밍 복구부(214), 상기 복구된 DS 동기를 이용하여 전송 채널상의 신호 열화를 보상하는 FS 동기 복구부(215), 상기 A/D 컨버터(207)의 출력과 DS 동기 복구부(213)의 출력을 이용하여 수신 신호를 일정한 진폭 레벨로 유지시키는 AGC(217), 및 상기 기저대역으로 복조된 I, Q 채널 디지털 신호를 이용하여 반송파를 복구하는 반송파 복구부(216)를 포함하여 구성된다.The digital processor 220 outputs the A / D converter 207 and the A / D converter 207 to A / D sample the output of the buffer amplifier 206 of the analog processor 200 at twice the symbol frequency. on

a first mixer 209 that demodulates into a baseband I-channel digital signal by multiplying (n is an integer);

(n is an integer) to delay the phase by 90 °

A phase retarder 211 outputting a signal output from the phase retarder 211 to an output of the A / D converter 207.

Only one per symbol for the second mixer 210 demodulating the baseband Q channel digital signal by multiplying (n is an integer) and the I, Q channel channel digital signal demodulated by the first and second mixers 209 and 210. DSF recovery unit for restoring synchronization existing for each data segment (DS) by using an LPF 212 for decimating to remove the high frequency part and an I-channel digital signal output from the LPF 212 213, a timing recovery unit 214 for restoring timing to be used as an A / D clock (A / D clk) of the A / D converter 207 by using the DS synchronization restored by the DS synchronization recovery unit 213; And a received signal using the output of the FS synchronization recovery unit 215, the A / D converter 207, and the output of the DS synchronization recovery unit 213 that compensate for signal degradation on a transmission channel using the recovered DS synchronization. AGC 217 to maintain a constant amplitude level, and the baseband demodulated I, Q And a carrier recovery unit 216 for recovering a carrier using a null digital signal.

Here, the channel signal output unit for outputting baseband I, Q channel digital signals includes the first and second mixers 209 and 210, the phase delay unit 211, and the LPF 212.

The reverse rotation unit 208, which is not mentioned, enables carrier recovery in the digital domain. In this case, the reverse rotation unit 208 can operate even if the VCO is configured to operate in the analog region.

In the present invention configured as described above, the tuner 201 selects only a predetermined frequency band selected by the user from the RF signals input through the antenna, converts the first IF signal of 46.69 MHz, and outputs the SAW filter 202.

At this time, since the HDTV broadcast signal has all the information in the 6MHz band from the intermediate frequency of 46.69MHz, the SAW filter 202 removes all remaining sections except for the 6MHz band in which the information exists from the output of the tuner 201.

The output of the SAW filter 202 is amplified by the AGC amplifier 203 to a predetermined gain and then output to the mixer 204.

In this case, in order to perform VSB demodulation in the digital domain, the IFB must be converted to an IF signal having a lower frequency than the first IF signal converted by the tuner 201.

That is, when A / D sampling is performed in the A / D converter 207 as it is 46.69 MHz, the frequency of the required clock signal should be 186.76 MHz (46.69 MHz * 4) in consideration of various factors. This is too big.

Therefore, the mixer 204 multiplies the output of the AGC amplifier 203 by cos (ωct) and outputs a second IF signal. The cos (ωct) is determined so that the second IF signal is 5π / 8.

The output of the mixer 204 is amplified by the buffer amplifier 206 after being removed from one side band through the LPF 205 and input to the A / D converter 207.

The A / D converter 207 converts the second analog IF signal output from the buffer amplifier 206 into a digital IF signal at a frequency twice the symbol frequency.

At this time, the frequency spectrum is shifted from the baseband in the positive frequency direction and the negative frequency direction by 5π / 8 as shown in FIG. 3A.

Accordingly, the IF signal digitally converted by the A / D converter 207 is demodulated by the first and second mixers 209 and 210 and converted into baseband.

The first mixer 209 multiplies the digital intermediate frequency output from the A / D converter 207 by cos n * 5π / 8 (n = 1,2,3, ...) to baseband I-channel digital signals. And the second mixer 210 multiplies the digital intermediate frequency output from the A / D converter 207 by sin n * (5π / 8) (n = 1,2,3, ...) to baseband. Demodulate the Q-channel digital signal.

That is, cos 5π / 8, cos 10π / 8, cos 15π / 8, cos 20π / 5, ... are periodically repeated and multiplied in the first mixer 209, and sin 5π in the second mixer 210. / 8, sin 10π / 8, sin 15π / 8, sin 20π / 5, ... are repeated and multiplied periodically.

Therefore, the frequency spectrum is frequency inversed as shown in FIG. 3b, and the frequency is shifted to the baseband.

At this time, even if the transition band spacing between the spectrum is relatively wide like the hatched portion, even if passing through the LPF (212) there is no interference of adjacent frequencies.

Here, it can be seen that there are certain rules for the values multiplied by the first mixer 209 and the second mixer 210.

That is, the values multiplied by the first and second mixers 209 and 210 are represented by cos (π · 5/8 · n) and sin (π · 5/8 · n). Values are periodic.

The period repeats 16 data cycles, but due to the nature of symmetry, only three coefficients are needed for multiplication.

4A and 4B, cos (π / 8 · n) and sin (π / 8 · n) are shown for simplicity.

In FIGS. 4A and 4B, values are output in the order in which they are located above the waveform.

Therefore, in the case of cos (π · 5/8 · n) multiplied by the first mixer 209, 0, c, -b, a, 1, -a, -b, c, 0, -c, b, a, -1, a, b, -c repeats periodically, and in the case of sin (π · 5/8 · n) multiplied by the second mixer 210, 1, -a, -b, c, 0 , -c, b, a, -1, a, b, -c, 0, c, -b, -a repeat periodically, but due to the nature of symmetry, the values necessary for multiplication are three coefficients a except for the sign a It can be seen that only b, c.

On the other hand, the carrier recovery unit 216 does not interfere with the operation even if the input data is shortened and input.

That is, as a result of data reduction, the aliasing component is carried on the present signal, but the signal used for carrier recovery is a pilot signal component from the transmitter, so it only loses a little in the signal-to-noise ratio and has little effect on the overall operation.

This is because the maximum transition width of the pilot bit signal is not so large (e.g., -100KHz to + 100KHz), so the effect of using a lowpass filter passing only a narrow low pass portion can be almost negligible.

In this case, the reduction ratio, that is, how many different data are used for signal processing may be various, but the present invention will be described with an example of limiting to two.

Accordingly, the first and second mixers 209 and 210 for generating I and Q signals input to the digital carrier recovery unit 216 may be configured as shown in FIG. 5.

Referring to FIG. 5, a multiplier 251 for multiplying the output of the A / D converter 207 by the coefficient b and an A / D converter provided to the output of the multiplier 251 provided to the A input terminal or the B input terminal according to the selection signal ( 207) or 0 is selected to output 0, -b, 1, -b, 0, b, -1, b sequentially through the output I, and 1, -b, 0, through the Q output and a selector 253 which sequentially outputs b, -1, b, 0, and -b.

That is, when the input unit selects one of two input values, the period of 0, -b, 1, -b, 0, b, -1, b is repeated on the I side, and 1, on the Q side. It can be seen that the cycle of -b, 0, b, -1, b, 0, -b is repeated.

Meanwhile, the present invention reduces hardware complexity by configuring the LPF of FIG. 2 using a half band filter widely used in digital signal processing.

The half-band filter is a filter in which all values of the filter coefficients are zero, except for the middle one.

That is, the coefficients of the filter h (n), n = -N, -N-1, ..., -1, 0, 1, ..., N-1, N except for n = 0 Becomes h (2 · n) = 0.

When interpreted in the frequency domain, the filter's frequency characteristics are characterized by a filter that is fully symmetric about π / 2.

This filter is widely used because all the values across two are zero, so the coefficient values of the filter used for the actual multiplication are significantly reduced.

Therefore, the complexity of the hardware can be reduced.

Using this property, the first and second mixers 209 and 210 and the LPF 212 of FIG. 2 may be configured as shown in FIG. 6.

Referring to FIG. 6, the multiplexer 301 which separates the output of the A / D converter 207 into an even part and an odd part and an I, Q channel required for carrier recovery using an even-numbered output output from the multiplexer 301. A carrier recovery signal output unit 303 for separately outputting a digital signal, an even I signal output unit 306 for outputting only the even I channel digital signal Ie1 using an even number output output from the multiplexer 301, Odd I signal output unit 308 for outputting only odd I channel digital signal Io1 using odd numbered outputs output from the multiplexer 301, and even and odd numbers of the even and odd I signal output units 306 and 308 A filter unit 312 for filtering and adding an I-channel digital signal, respectively, and restoring data of a symbol period to the DS synchronization recovery unit 213, and the carrier recovery signal output unit in synchronization with a symbol frequency Fs ( 303), It can be I-signal output unit configured to signal controller 302 to provide a timing signal for selecting a (306, 308).

Since the configuration of the carrier recovery signal output unit 303 is the same as that of FIG. 5, a description thereof will be omitted.

The even I signal output unit 306 is a multiplier 305 for multiplying the even number output of the multiplexer 301 by a coefficient b, an output of the even number output or the multiplier 305 of the multiplexer 301, or 0 Is selected according to the selection signal of the timing controller 302, and selector 307 for outputting the even-numbered I-channel digital signal Ie1.

The odd I signal output unit 308 is a multiplier 309 for multiplying an odd-numbered output output from the multiplexer 301 with a coefficient a, and a multiplier for multiplying an odd-numbered output output from the multiplexer 301 with a coefficient c ( 310 and a selector 311 which selects outputs of the multipliers 309 and 310 according to a selection signal of the timing controller 302 and outputs an odd-numbered I-channel digital signal Io1.

In this case, the coefficients a, b, and c are the same as the coefficients described with reference to FIGS. 4A and 4B.

6, the multiplexer 301 divides the output of the A / D converter 207 into even and odd portions.

The selector 304 of the carrier recovery signal output unit 303 is a timing control unit that outputs zero or zero of the multiplier 305 in which the coefficient b is multiplied by the output of the A / D converter 207 or the output of the A / D converter 207. It selects according to the selection signal provided at 302 and outputs I, Q channel digital signals I1 and Q1 necessary for carrier recovery.

That is, when the I / Q channel digital signal is separated using the even-numbered input output from the multiplexer 301, the I channel digital signal I1 is 0, -b, 1, -b, 0, b, -1. The cycle of, b is repeated, and the Q channel digital signal Q1 repeats the cycles of 1, -b, 0, b, -1, b, 0, and -b.

On the other hand, the selector 307 of the even-I signal output unit 306 is the output of the multiplier 305 multiplied by the coefficient b multiplied by the output of the A / D converter 207 or the output of the A / D converter 207, or 0 Is selected according to the selection signal provided from the timing controller 302 to output the even-numbered I-channel digital signal Ie1.

That is, when the selector 307 selects only the even input of the I channel digital signal, the even I channel digital signal Ie1 repeats the periods of 0, -b, 1, -b, 0, b, -1, and b. Done.

The selector 311 of the odd I signal output unit 308 has a coefficient c at the output of the multiplier 309 or the output of the A / D converter 207 multiplied by the coefficient a at the output of the A / D converter 207. The output of the multiplier 310 is selected according to the selection signal provided from the timing controller 302 to output the odd-numbered I-channel digital signal Io1.

That is, when the selector 311 selects only the odd-numbered input of the I-channel digital signal, the odd I-channel digital signal Io1 repeats the cycles c, a, -a, c, -c, a, a, and -c. Done.

The even I-channel digital signal Ie1 is filtered by the first filter 313 of the filter unit 312. The first filter 313 uses a half-band filter as shown in FIG.

Accordingly, the second filter 314 filtering the odd I-channel digital signal Io1 may be configured with only a delay element as shown in FIG. 7.

The adder 315 adds the output of the first filter 313 and the output of the second filter 314 to recover only the values corresponding to the original symbol periods, and outputs the values to the DS synchronization recovery unit 213.

8 is a multiplexer 351 for dividing the output of the A / D converter 207 into even and odd parts, and an even-numbered output output from the multiplexer 351 as another embodiment of FIG. 6. An even-numbered I-channel digital signal by using an even-numbered output unit 353 and an odd-numbered output output from the multiplexer 351 to separate and output the even-numbered I-channel digital signal Ie1 and the Q-channel digital signal Qe1. The odd-numbered signal output unit 356 separately outputs (Io1) and the Q-channel digital signal Qo1, and the paired, odd-I, Q-channel digital signals Ie1, Qe1, Io1, Qo1), respectively, after filtering, adding, restoring the data of the symbol period, and outputting the data to the DS synchronization recovery unit 213, and the even and odd signal output units 353 and 356 in synchronization with the symbol frequency Fs. The timing controller 352 provides a timing signal.

The even signal output unit 353 is a multiplier 354 for multiplying the even number output of the multiplexer 351 by a coefficient b, and an output of 0 or an output of the even number output or multiplier 354 of the multiplexer 351. The selector 355 selects the signal according to the selection signal of the timing controller 352 to separately output the even-numbered I-channel digital signal Ie1 and the even-numbered Q-channel digital signal Qe1.

The odd signal output unit 356 is a multiplier 357 for multiplying the odd-numbered output output from the multiplexer 351 by a coefficient a, and a multiplier 358 for multiplying the odd-numbered output output from the multiplexer 351 by a coefficient c. And a selector 359 for selecting and outputting the outputs of the multipliers 357 and 358 according to the selection signal of the timing controller 352 to separate and output the odd-numbered I-channel digital signal Io1 and the odd-numbered Q-channel digital signal Qo1. It is composed of

Similarly, the coefficients a, b and c are the same as the coefficients described in Figs. 4A and 4B.

The filter unit 400 is output from the first filter 401 and the even signal output unit 353 to half-band filter the even-numbered I-channel digital signal Ie1 output from the even-signal output unit 353. A second filter 402 for half-band filtering the even-numbered Q-channel digital signal Qe1 and processing the odd-numbered I-channel digital signal Io1 output from the odd-signal output unit 356 by the first filter 401. A third filter 403 for delaying the time by a time, a fourth filter 404 for delaying the odd Q-channel digital signal Qo1 output from the odd signal output unit 356 by the processing time of the second filter 402, A first adder 405 for adding outputs of the first and third filters 401 and 403, a second adder 406 for adding outputs of the second and fourth filters 402 and 404, and the first and third filters By adding the outputs of the two adders 405 and 406, the data of the symbol period is restored and output to the DS synchronization recovery unit 213. Claim 3 is composed of an adder 407.

In this case, the timing controller 352 generates a selection signal to the selectors 355 and 359 of the even and odd signal output units 353 and 356. If the counter can be configured as a counter, only 0, 1, 2, 3, 4, 5, It is possible to generate a signal which repeats 6,7 periodically and provide it as a selection signal.

In FIG. 8 configured as described above, the multiplexer 351 separates the output of the A / D converter 207 into even and odd portions.

The selector 355 of the even-signal output unit 353 is a timing control unit that outputs or zeros the output of the multiplier 354 in which the coefficient b is multiplied by the output of the A / D converter 207 or the output of the A / D converter 207. Selected according to the timing signal provided at 352 to separately output the even-numbered I-channel digital signal Ie1 and the Q-channel digital signal Qe1.

Accordingly, the even I-channel digital signal Ie1 output from the selector 355 repeats the cycles of 0, -b, 1, -b, 0, b, -1, b, and the even Q-channel digital signal Qe1. ) Repeats the cycle of 1, -b, 0, b, -1, b, 0, -b.

The selector 359 of the odd-signal output unit 356 has a coefficient c multiplied by the output of the multiplier 357 or the output of the A / D converter 207 multiplied by the coefficient a by the output of the A / D converter 207. The output of the multiplier 358 is selected according to the timing signal provided from the timing controller 302 to separately output the odd-numbered I-channel digital signal Io1 and the Q-channel digital signal Qo1.

Therefore, the odd I-channel digital signal Io1 output from the selector 311 repeats the cycles c, a, -a, c, -c, a, a, -c, and the Q channel digital signal Qo1. Will repeat the cycles -a, c, -c, a, a, -c, c, -a.

The even-numbered I, Q channel digital signals Ie1 and Qe1 are filtered by the first filter 401 and the second filter 402 of the filter unit 400, respectively. 401 and 402 are processed by a half band filter as shown in FIG.

Therefore, the third and fourth filters 403 and 404 respectively filtering the odd I and Q channel digital signals Io1 and Qo1 may be configured only with delay elements having a delay time as shown in FIG. 9.

At this time, the delay elements of the third and fourth filters 403 and 404 are delay elements for generating a delay time such as the filter processing delay time of the first and second filters 401 and 402.

Here, the delay element of the fourth filter 404 that delays the odd-numbered Q-channel digital signal Qo1 by a predetermined time may be removed if the second filter 402 is well designed.

The first adder 405 adds outputs of the first and third filters 401 and 403, and the second adder 406 adds outputs of the second and fourth filters 402 and 404, and the third adder ( 407 reconstructs only values corresponding to the original symbol period by adding the outputs of the first and second adders 405 and 406, and outputs the values to the DS synchronization recovery unit 213. FIG.

In this case, the filter unit 400 may share a multiplier and an adder using a multiplexer as shown in FIG. 10.

That is, the even-numbered I-channel digital signal Ie1 and Q-channel digital signal are transmitted through the multiplexer 503 while the even-numbered I-Q channel digital signals Ie1 and Qe1 are transmitted through the delay elements 501 and 502 connected in series. The filter coefficients Ci and Cq that pass through Qe1 alternately and multiply each may also be shared by passing through the multiplexer 505 to the multiplier 504 in order to share the multiplier and the adder.

At this time, odd-numbered I, Q channel digital signals Io1 and Qo1 output through the respective filters 506 and 507 of the plurality of delay elements are alternately passed through the multiplexer 508 to the adder 509.

Thus, the amount and complexity of hardware can be reduced.

The DS synchronization recovery unit 213 detects a DS synchronization from the data Ie2 of the symbol period restored by the filtering unit 400, and the timing recovery unit 214 for each DS detected by the DS synchronization recovery unit 213. Timing recovery is performed by using the symmetry of the existing synchronization signal.

In this case, since the timing recovery unit 214 is performed using the symmetry of the synchronization signal existing for each DS synchronization, the timing recovery unit 214 cannot restore the timing information unless the DS synchronization recovery unit 213 detects the DS synchronization signal. Since it is provided to the clock of the A / D converter 207 again, the timing information is not restored, which causes a vicious cycle in which the detection of the DS synchronization signal is not easy.

That is, the DS synchronization recovery unit 213 first detects the synchronization signal and uses the timing recovery unit 214 to restore the timing information. The timing information is not restored during the initial driving of the system as in the case of channel conversion. In this state, the detection of the synchronization signal is not easy, and since the synchronization signal is not detected, the recovery of the timing information is not easy.

This is because the recovery of the timing information adopts a method that uses the symmetry of the signal received through the early-rate structure, which results in inaccurate data values when the initial timing information is not restored, resulting in a long synchronization time or inconsistent synchronization. It may be impossible.

11 solves this problem, and the timing information is detected by restoring the data between the symbol period and the data.

11 is the same in configuration and operation as in FIG. 6 except for the filter unit, and thus, the same block and element will be omitted by using the same reference numerals, and only the filter unit 600 will be described.

Here, the timing controller 302 outputs a selection signal to each of the selectors 304, 307, and 311 in synchronization with the input double symbol frequency 2Fs.

That is, the filter unit 600 includes a first filter 601 for half-band filtering the even I channel digital signal Ie2 output from the even I signal output unit 306, and a plurality of delay elements. Second filter 602 for delaying the even I channel digital signal Ie2 output from the signal output unit 306 by a predetermined time, and an odd I channel output from the odd I signal output unit 308, which is composed of a plurality of delay elements. A third filter 604 for delaying the digital signal Io2 by a predetermined time, a fourth filter 604 for half-band filtering the odd I channel digital signal Io2 output from the odd I signal output unit 308, and A first adder 605 that adds outputs of the first and third filters 601 and 603 to reconstruct the data Ie3 of a symbol period, and an output of the second and fourth filters 602 and 604, and adds an interval between symbol periods. And a second adder 606 for restoring the data Io3.

That is, the first and fourth filters 601 and 604 perform half-band filtering to remove high frequency components of the even and odd I channel digital signals, respectively, and the second and third filters 602 and 603 respectively use even and odd I channel digital signals. Delay the signal by the processing time of the half-band filter.

The first adder 605 performs the operation of the even-numbered I-channel digital signal filtered by the first filter 601 and the odd-numbered I-channel digital signal delayed by the filter processing delay time of the first filter 601 by the third filter 603. And add the data Ie3 of the symbol period, and the second adder 606 adds the odd-numbered I-channel digital signal filtered by the fourth filter 604 and the fourth filter 604 of the second filter 602. The even number I-channel digital signal delayed by the filter processing delay time is added to recover data Io3 between symbol periods.

At this time, the filter unit 600 alternately restores the data Ie3 of the symbol period and the data Io3 between the symbol periods by using a half-band filter, a plurality of delayers, and a multiplexer, as shown in FIG. The output is sent to the synchronous recovery unit 213.

Meanwhile, FIG. 13 is another embodiment of FIG. 11, except for the filter unit, and thus the configuration and operation are the same as those of FIG. 8, and the same block and element will be omitted by the same reference numerals, and the filter unit 700 will be omitted. Explain only.

Here, the timing controller 352 outputs a selection signal to each of the selectors 355 and 359 in synchronization with the input double symbol frequency 2Fs.

That is, the filter unit 700 is output from the first filter 701 and the even signal output unit 353 to half-band filter the even-numbered I-channel digital signal Ie1 output from the even-signal output unit 353. The second filter 702 which half-band filters the even-numbered Q-channel digital signal Qe1 and the odd-numbered I-channel digital signal Io1 output from the odd-numbered signal output unit 356 are processed in the first filter 701. A third filter 703 delaying by as much as the fourth filter 704 delaying the odd Q channel digital signal Qo1 output from the odd signal output unit 356 by the processing time of the second filter 702 A fifth filter 705 for half-band filtering the odd-numbered I-channel digital signal Io1 output from the signal output unit 356, and an odd-numbered Q-channel digital signal Qo1 output from the odd-signal output unit 356. The sixth filter 706 for half-band filtering, and is output from the even signal output unit 353 The seventh filter 707 delaying the first I-channel digital signal Ie1 by the processing time of the fifth filter 705 and the even-numbered Q channel digital signal Qe1 output from the even-signal output unit 353. The eighth filter 708 delaying the processing time of the six filter 706, the first adder 709, and the second and fourth filters 702 and 704 that add outputs of the first and third filters 701 and 703. A second adder 710 for adding an output of the third adder 711 for reconstructing data Ie2 of a symbol period by adding outputs of the first and second adders 709 and 710, and fifth and seventh. The fourth adder 712 for adding the outputs of the filters 705 and 707, the fifth adder 713 for adding the outputs of the sixth and eighth filters 706 and 708, and the fourth and fifth adders 712 and 713. And a sixth adder 714 that adds the output to recover data Io2 between symbol periods.

That is, the first, second, fifth, and sixth filters 701, 702, 705, and 706 half-band filter the even, odd I, and Q channel digital signals Ie1, Qe1, Io1, and Qo1, respectively. The seventh and eighth filters 703, 704, 707, 708 delay the even, odd I, Q channel digital signals Ie1, Qe1, Io1, Qo1 by the processing time of the half-band filter, respectively.

The first adder 709 adds the even-numbered I-channel digital signal filtered by the first filter 701 and the odd-numbered I-channel digital signal delayed by the filter processing time by the third filter 703, and the second adder 710 ) Adds the even-numbered Q-channel digital signal filtered by the second filter 702 and the odd-numbered Q-channel digital signal delayed by the filter processing time by the fourth filter 704, and the third adder 711 adds the first, The data Ie2 of the symbol period is restored by adding the outputs of the second adders 709 and 710.

The fourth adder 712 adds the odd-numbered I-channel digital signal filtered by the fifth filter 705 and the even-numbered I-channel digital signal delayed by the filter processing time by the sixth filter 706, and the fifth adder 713 ) Adds the odd-numbered Q-channel digital signal filtered by the seventh filter 707 and the even-numbered Q-channel digital signal delayed by the filter processing time in the eighth filter 708, and the sixth adder 714 adds the fourth, By adding the outputs of the fourth adders 712 and 713, the data Io2 of the symbol period is restored.

FIG. 14 is a detailed block diagram illustrating first, third, fifth, and seventh filters 701, 703, 705, and 707 for filtering an I channel digital signal of the filter unit 700. The half band filter, a plurality of delayers, and a multiplexer are shown in FIG. And second and fourth filters 702, 704, 706 and 708 for filtering the Q channel digital signal.

Therefore, by adding the processing results of the two filters, data between the symbol period and the data between the symbol periods may be alternately output.

As described above, although the hardware of the filter unit of FIGS. 11 and 13 is slightly complicated, the filter unit obtains data between the symbol period and the symbol period at twice the symbol frequency, and thus, there is an advantage that the timing information can be easily restored by using various methods. .

That is, timing information may be extracted without depending on the DS signal during the initial operation of the system.

For example, by first adjusting the frequency difference between the symbol clocks of the transmission and reception periods through the early rate or the Gardner method during the initial operation of the system with the data between the symbol periods, the symmetry of the synchronization signal existing for each DS detected in the data of the symbol periods is adjusted. To restore the timing information.

Therefore, since timing is started to recover before DS synchronization is recovered, there is no instability that may occur between timing recovery and DS synchronization detection.

On the other hand, Figure 15 is another embodiment of the digital VSB demodulation device according to the present invention, the analog processing unit is the same as Figure 2, so only the digital processing unit is shown, not shown.

을 곱하여 기저대역의 I 채널 디지털 신호로 복조하는 제 1 믹서(802), 상기 A/D 변환기(802)의 출력에

을 곱하여 기저대역의 Q 채널 디지털 신호로 복조하는 제 2 믹서(803), 상기 제 1 믹서(802)에서 복조된 I 채널 디지털 신호를 저역 필터링하는 제 1 필터(804), 상기 제 2 믹서(803)에서 복조된 Q 채널 디지털 신호를 힐버트 변환하는 제 2 필터(805), 및 상기 제 1, 제 2 필터(804,805)의 출력을 가산하여 DS 동기 복구부(212)로 출력하는 가산기(806)를 포함하여 구성된다.The digital processing unit A / D converter 801 and A / D converter 801 for A / D sampling the output of the analog processing unit twice the symbol frequency to the output of the A / D converter 801

Multiply the output of the first mixer 802 and the A / D converter 802 by demodulation to a baseband I-channel digital signal.

The second mixer 803 demodulates the baseband Q channel digital signal by multiplying, the first filter 804 and the second mixer 803 for low pass filtering the I channel digital signal demodulated by the first mixer 802. A second filter 805 for Hilbert transforming the Q-channel digital signal demodulated at the N-axis, and an adder 806 for adding the outputs of the first and second filters 804 and 805 to the DS synchronization recovery unit 212 It is configured to include.

Then, the DS synchronization recovery unit 213 recovers the synchronization existing for each DS using the I-channel digital signal output from the adder 806 and A using the DS synchronization recovered from the DS synchronization recovery unit 213. A timing recovery unit 214 for recovering timing for use as an A / D clock (A / D clk) of the / D converter 207, and an FS synchronization recovery unit for compensating for signal degradation on a transmission channel using the restored DS synchronization 215, an AGC 217 for maintaining a received signal at a constant amplitude level using the output of the A / D converter 207 and the output of the DS synchronization recovery unit 213, and the demodulated I, Q channel digital. A carrier recovery unit 216 for recovering a carrier using a signal is provided as in FIG. 2.

FIG. 15 configured as described above is intended to remove interference of the adjacent channel because the signal of the adjacent channel enters the interference due to the passband characteristic of the SAW filter.

That is, in FIG. 2, the pass band 811 of the SAW filter 202 of the analog processing unit 200 is slightly wider than the bandwidth 812 of the original signal as shown in FIG. 16A.

The reason for this is that since the characteristics of the SAW filter 202 varies greatly depending on the temperature and the manufacturing process, the signal is distorted when the bandwidth of the SAW filter 202 is exactly the bandwidth of the original signal. to be.

In practice, shaping Nyquist waveforms is usually done using filters in the digital domain.

The signal of the band passing through the SAW filter 202 is amplified by the AGC amplifier 203 with a predetermined gain according to the AGC signal, and then output to the mixer 204, and the mixer 204 receives the AGC amplifier ( Multiply the output of 203 by cos (ωct) to shift the frequency to a second IF signal that is lower than the first IF signal.

If the second IF signal is A / D sampled at twice the symbol frequency in the A / D converter 801 after the high frequency portion is removed while passing through the LPF 205 and the buffer amplifier 206, the frequency spectrum is shown in FIG. Appears as

Referring to FIG. 16B, it can be seen that the signals 816, 817, 818, and 820 of adjacent channels ride in noise at the edges of the original signals 815 and 819 due to the passband characteristics of the SAW filter 202.

When the first mixer 802 multiplies the output of the A / D converter 801 by cos (π · 5/8 · n), the frequency shifts to the baseband as shown in FIG. Will be printed).

In this case, if low pass filtering is performed by setting the pass bandwidth of the first filter 804 as shown in 820 of FIG. 16C, the interference components 814 and 817 outside the signal may be attenuated.

However, interference signals 813 and 815 that have already entered the pass band remain without being removed as shown in FIG. 16D even when the first filter 804 performs the filter process.

When the output of the A / D converter 801 is multiplied by sin (π · 5/8 · n) in the second mixer 803, the frequency is shifted to the baseband of the Q channel as shown in FIG. 16E. There is a 180 ° phase difference between and the interference signal.

When the Q channel digital signal of FIG. 16E is Hilbert transformed by the second filter 805, the phase of the desired signal is the same as that of the original signal as in FIG. 16F, but the phase of the interference signal has a phase difference of 180 °.

Therefore, when the output of the first filter 804 as shown in FIG. 16D and the output of the second filter 805 as shown in FIG. 16F are added by the adder 806, the interference signal in the pass band is removed as shown in FIG. The signal can be restored.

Here, although the complexity of the hardware is increased to some extent, the signal characteristics are improved, so that the operation is desired even in a poor channel situation.

Thus, FIG. 15 is advantageously applied to high end products, not low end products.

FIG. 17 is a detailed block diagram of the digital carrier recovery unit 216 of FIGS. 2 and 15 and has been filed by the present applicant.

That is, the I-channel digital signal and the Q-channel digital signal are input to the first and second infinite impulse response filters (IRR filters) 901 and 902, respectively, so that the influence of the NTSC adjacent channel of the digital data is eliminated and its phase is self-phased. Effects due to their effects on properties are eliminated.

The output of the first IIR filter 901 is inputted to the delayer 904 after being limited by the limiter 903.

The retarder 904 linearly changes the frequency band phase characteristic of the output of the first IIR filter 901, which is limited at the limiter 903.

The code converter 905 changes the sign of the Q channel digital signal output from the second IIR filter 902, and then uses the output of the delay unit 904 as a selection signal to convert the Q channel digital signal or the sign whose sign is inverted. A non-inverted Q channel digital signal is selectively output to the digital loop filter 906.

The digital loop filter 906 controls the frequency and phase of the digital signal input through the code converter 905 to output the carrier whose frequency and phase have been recovered to the D / A converter 907.

The D / A converter 907 controls the NCO or VCO by converting a carrier whose frequency and phase have been recovered to an analog value.

That is, the frequency and phase of one carrier selected through the tuner among the plurality of RF signals received through the antenna are recovered, and the recovered carrier is used as a loop control signal for making the RF signal input to the tuner into a baseband signal. do.

As described above, according to the digital VSB demodulation device, the VSB demodulation is performed in the digital domain without interference of adjacent signals by lowering the intermediate frequency to 5π / 8 and the clock frequency of the A / D converter to twice the symbol frequency. This allows the carrier to maintain exactly 90 ° of phase difference, improving demodulation performance, and reducing hardware complexity to facilitate integration and ASIC design.

In addition, the low-pass filtering of the baseband demodulated I-channel digital signal, the Hilbert transform of the baseband demodulated Q-channel digital signal, and then add the two signals, widening the passband than the bandwidth of the original signal. This eliminates interference of signals from adjacent channels coming into the edge of the original signal. Thus, the original signal can be accurately restored.

In addition, by processing the baseband demodulated I, Q channel digital signal with a half-band filter, the filter coefficients are reduced to reduce hardware complexity.

In addition, by facilitating restoration of the timing information by obtaining all the values corresponding to the original symbol period and the value between the symbols, the equalizer can be configured in the half symbol period.

Claims (12)

A low frequency IF signal output unit for multiplying an input first intermediate frequency (IF) signal by a predetermined frequency input from the outside to convert to 5π / 8 which is a second IF signal lower than the first IF signal; An analog / digital converter for sampling the second IF signal output from the low frequency IF signal output unit at a frequency twice the symbol frequency and converting the signal into a digital signal; Multiply the output of the analog / digital converter by cos 5π / 8, sin 5π / 8 to demodulate the baseband I, Q channel digital signals, and then output a channel signal that performs decimation and low pass filtering to sample only one symbol per symbol. Wealth, A DS synchronization recovery unit for recovering synchronization existing for each data segment DS by using an I channel digital signal output from the channel signal output unit; A timing recovery unit for restoring timing by using the symmetry of the synchronization signal existing for each DS recovered by the DS synchronization recovery unit; And a carrier recovery unit for recovering a carrier by using the baseband demodulated I and Q channel digital signals. The method of claim 1, wherein the channel signal output unit A first mixer demodulating the output of the analog / digital converter by cos (5π / 8) n (n is an integer) to a baseband I-channel digital signal; A second mixer for demodulating the output of the analog / digital converter by sin (5π / 8) n (n is an integer) to a baseband Q channel digital signal, And a filter unit for decimating the I and Q channel digital signals output from the first and second mixers at a predetermined ratio, and then removing the high range parts and outputting them to the DS synchronization recovery unit. . The method of claim 1, wherein the channel signal output unit A multiplexer for separating the output of the analog / digital converter into an even and an odd part; A carrier recovery signal output unit configured to generate I, Q channel digital signals necessary for carrier recovery using an even-numbered output output from the multiplexer; An even I signal output unit for outputting only even I channel digital signals using an even number output output from the multiplexer; An odd I signal output unit for outputting only odd I channel digital signals using an odd number output output from the multiplexer; A filter unit for restoring data of a symbol period by filtering and adding the even I channel digital signal and the odd I channel digital signal of the even and odd I signal output units, respectively, and outputting them to a DS synchronization recovery unit; And a timing control unit configured to provide a selection signal to the carrier recovery signal output unit, the even I signal output unit, and the odd I signal output unit in synchronization with an input symbol frequency. The method of claim 3, wherein the carrier recovery signal output unit A multiplier that multiplies a second coefficient by an even-numbered output output from the multiplexer, And a selector for outputting decimated I, Q channel digital signals by selecting an even-numbered output of the multiplexer, an output of the multiplier, or 0 according to a selection signal of the timing controller. The method of claim 3, wherein the even I signal output unit A multiplier that multiplies a second coefficient by an even-numbered output output from the multiplexer, And a selector for outputting even-numbered I-channel digital signals by selecting an even-numbered output of the multiplexer, an output of the multiplier, or 0 according to a selection signal of the timing controller. The method of claim 3, wherein the odd I signal output unit A first multiplier for multiplying an odd number output output from the multiplexer by a first coefficient, A second multiplier for multiplying an odd number output of the multiplexer by a third coefficient; And a selector for outputting odd-numbered I-channel digital signals by selecting outputs of the first and second multipliers according to selection signals of the timing controller. The method of claim 3, wherein the filter unit A first filter performing halfband filtering on the even I channel digital signal; A second filter for delaying the odd I channel digital signal by the processing time of the first filter; And an adder for restoring data corresponding to an original symbol period by adding outputs of the first and second filters. The method of claim 1, wherein the channel signal output unit A multiplexer for separating the output of the analog / digital converter into an even and an odd part; A carrier recovery signal output unit configured to generate I, Q channel digital signals necessary for carrier recovery using an even-numbered output output from the multiplexer; An even signal output unit configured to separately output an even I channel digital signal Ie1 and a Q channel digital signal Qe1 from an even number output output from the multiplexer; An odd signal output unit for separating and outputting an odd-numbered I-channel digital signal Io1 and a Q-channel digital signal Qo1 from an odd-numbered output output from the multiplexer; A filter unit for restoring data of a symbol period by filtering and adding the even I, Q channel digital signals and the odd I, Q channel digital signals Ie1, Qe1, Io1, and Qo1 of the even and odd signal output units, respectively; And a timing controller configured to provide a selection signal to the carrier recovery signal output unit, the even signal output unit, and the odd signal output unit in synchronization with an input symbol frequency. The method of claim 1, wherein the channel signal output unit A multiplexer for separating the output of the analog / digital converter into an even and an odd part; A carrier recovery signal output unit configured to generate I, Q channel digital signals necessary for carrier recovery using an even-numbered output output from the multiplexer; An even I signal output unit for outputting only even I channel digital signals using an even number output output from the multiplexer; An odd I signal output unit for outputting only odd I channel digital signals using an odd number output output from the multiplexer; A filter unit for restoring data between symbol periods and data between symbol periods by filtering and adding the even I channel digital signals and the odd I channel digital signals of the even and odd I signal output units, respectively; And a timing control unit configured to provide a selection signal to the carrier recovery signal output unit, the even I signal output unit, and the odd I signal output unit in synchronization with an input double symbol frequency (2Fs). . The method of claim 1, wherein the channel signal output unit A multiplexer for separating the output of the analog / digital converter into an even and an odd part; A carrier recovery signal output unit configured to generate I, Q channel digital signals necessary for carrier recovery using an even-numbered output output from the multiplexer; An even signal output unit configured to separately output an even I channel digital signal and an even Q channel digital signal from an even number output output from the multiplexer; An odd signal output unit for separating and outputting an odd I channel digital signal and a Q channel digital signal from an odd number output output from the multiplexer; The data between the symbol period and the symbol period is restored by filtering and adding even-numbered I, Q-channel digital signals and odd-numbered I, Q-channel digital signals outputted through the even and odd signal output units, respectively. With filter part to say, And a timing control section configured to provide a selection signal to the carrier recovery signal output section, the even signal output section, and the odd signal output section in synchronization with an input double symbol frequency (2Fs). A low frequency IF signal output unit for multiplying an input first intermediate frequency (IF) signal by a predetermined frequency input from the outside to convert to 5π / 8 which is a second IF signal lower than the first IF signal; An analog / digital converter for sampling the second IF signal output from the low frequency IF signal output unit at a frequency twice the symbol frequency and converting the signal into a digital signal; The output of the analog / digital converter is multiplied by cos 5π / 8 and sin 5π / 8 to demodulate the baseband I and Q channel digital signals, filter the demodulated I and Q channel digital signals, and add the two filtered signals. A channel signal output unit for removing interference signals in a pass band by A DS synchronization recovery unit for recovering synchronization existing for each data segment DS by using the channel digital signal output from the channel signal output unit; A timing recovery unit for restoring timing by using the symmetry of the synchronization signal existing for each DS recovered by the DS synchronization recovery unit; And a carrier recovery unit for recovering a carrier by using the baseband demodulated I and Q channel digital signals. The method of claim 11, wherein the channel signal output unit A first mixer demodulating the output of the analog / digital converter by cos (5π / 8) n (n is an integer) to a baseband I-channel digital signal; A second mixer for demodulating the output of the analog / digital converter by sin (5ππ / 8) n (n is an integer) to a baseband Q channel digital signal, A first filter for low pass filtering the I channel digital signal of the first mixer; A second filter for Hilbert transforming the Q channel digital signal of the second mixer; And an adder which adds the outputs of the first and second filters to remove the interference signal in the pass band.

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