KR100325458B1 - Manufacturing Method of Semiconductor Memory Device - Google Patents
Manufacturing Method of Semiconductor Memory Device Download PDFInfo
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- KR100325458B1 KR100325458B1 KR1019980059155A KR19980059155A KR100325458B1 KR 100325458 B1 KR100325458 B1 KR 100325458B1 KR 1019980059155 A KR1019980059155 A KR 1019980059155A KR 19980059155 A KR19980059155 A KR 19980059155A KR 100325458 B1 KR100325458 B1 KR 100325458B1
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- semiconductor memory
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910010037 TiAlN Inorganic materials 0.000 claims abstract description 51
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000004381 surface treatment Methods 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 12
- 230000008021 deposition Effects 0.000 abstract description 10
- 230000003647 oxidation Effects 0.000 abstract description 9
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 68
- 239000010410 layer Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000010409 thin film Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- 229910052788 barium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 캐패시터와 하부배선층 사이에 배리어 금속막을 적용하는 경우, 후속 열처리시 배리어 금속막의 내산화 특성을 향상시킬 수 있는 반도체 메모리 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor memory device capable of improving the oxidation resistance of the barrier metal film during subsequent heat treatment when the barrier metal film is applied between the capacitor and the lower wiring layer.
본 발명에 따른 반도체 메모리 소자는 하부전극과 고유전율을 갖는 유전체막과 상부전극으로 이루어진 캐패시터와, 하부전극 하부의 하부배선층을 구비하고, 하부전극과 하부배선층 사이에 배리어 금속막을 구비한다. 여기서, 배리어 금속막은 제 1 내지 제 3 TiAlN막을 0 내지 500℃의 온도범위에서 온도를 달리하여 각각 증착하여 형성하고, 각각의 TiAlN막의 증착후에는 막에 대한 표면처리를 각각 진행한다. 또한, 제 1 TiAlN막은 100 내지 500℃의 온도에서 증착하고, 제 2 TiAlN막은 0 내지 300℃에서 증착하고, 제 3 TiAlN막은 300 내지 500℃의 온도에서 증착한다. 또한, 제 1 TiAlN막의 표면처리는 질소나 산소 플라즈마를 이용하여 진행하고, 제 2 TiAlN막의 표면처리는 산소 플라즈마를 이용하여 진행하고, 제 3 TiAlN막의 표면처리는 질소 플라즈마를 이용하여 진행한다.The semiconductor memory device according to the present invention includes a capacitor including a lower electrode, a dielectric film having a high dielectric constant and an upper electrode, a lower wiring layer under the lower electrode, and a barrier metal film between the lower electrode and the lower wiring layer. Here, the barrier metal film is formed by depositing the first to third TiAlN films at different temperatures in a temperature range of 0 to 500 ° C., and after the deposition of each TiAlN film, the surface treatment is performed on the films. In addition, the first TiAlN film is deposited at a temperature of 100 to 500 ° C, the second TiAlN film is deposited at 0 to 300 ° C, and the third TiAlN film is deposited at a temperature of 300 to 500 ° C. The surface treatment of the first TiAlN film is carried out using nitrogen or oxygen plasma, the surface treatment of the second TiAlN film is performed using oxygen plasma, and the surface treatment of the third TiAlN film is performed using nitrogen plasma.
Description
본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 특히 캐패시터와 하부배선사이에 배리어 금속막이 적용된 반도체 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device in which a barrier metal film is applied between a capacitor and a lower wiring.
최근에 반도체 메모리 소자의 집적도가 증가됨에 따라, 셀면적 및 셀 사이의 간격은 축소되는 반면, 캐패시터는 일정용량을 보유해야 하기 때문에, 좁은 면적에 큰 용량을 가지는 캐패시터가 요구된다.In recent years, as the degree of integration of semiconductor memory devices is increased, the cell area and the spacing between cells are reduced, while capacitors have to have a constant capacity, and therefore a capacitor having a large capacity in a small area is required.
이에 대하여, 종래에는 캐패시터의 용량을 극대화하기 위하여, (바륨/스트로튬)티타늄 산화막{(Ba, Sr)TiO3; BST}과 같은 고유전율을 갖는 산화막을 유전체막으로 이용하여 캐패시터를 형성하였다.In contrast, conventionally, in order to maximize the capacity of a capacitor, a (barium / strotium) titanium oxide film {(Ba, Sr) TiO 3; A capacitor was formed using an oxide film having a high dielectric constant such as BST} as a dielectric film.
이러한 고유전율을 갖는 산화막은 일반적으로 고온산화 분위기에서 형성하고, 상기 산화막이 적용되는 캐패시터의 상부 및 하부전극 재료로서 백금(Pt), 루세늄(Ru), 이리듐(Ir)과 같은 물질을 사용하고, 하부전극과 접하는 하부배선재료로서 도핑된 폴리실리콘막을 사용한다.An oxide film having such a high dielectric constant is generally formed in a high temperature oxidizing atmosphere, and materials such as platinum (Pt), ruthenium (Ru), and iridium (Ir) are used as upper and lower electrode materials of the capacitor to which the oxide film is applied. A doped polysilicon film is used as the lower wiring material in contact with the lower electrode.
그러나, 상기한 고유전율 유전체막 형성을 위한 고온산화시, 하부배선재료인 폴리실리콘막의 산화로 인하여 실리콘 산화막이 형성되어 유전체막이 고유전율 유전체막과 저유전율의 실리콘 산화막의 이중막으로 형성된다. 이때, 총유전율이 저유전율의 실리콘 산화막에 의해 결정되기 때문에 유전율이 저하되어 캐패시터의 용량이 저하된다. 또한, 실리콘 산화막으로 인하여 하부전극과 폴리실리콘막 사이의 접착력이 감소되어 캐패시터 구조의 변형이 유발된다.However, during the high temperature oxidation for forming the high dielectric constant dielectric film, a silicon oxide film is formed due to the oxidation of the polysilicon film, which is a lower wiring material, so that the dielectric film is formed of a double layer of a high dielectric constant dielectric film and a low dielectric constant silicon oxide film. At this time, since the total dielectric constant is determined by the silicon oxide film of low dielectric constant, the dielectric constant is lowered and the capacity of the capacitor is lowered. In addition, the adhesion between the lower electrode and the polysilicon film is reduced due to the silicon oxide film, causing deformation of the capacitor structure.
한편, 이러한 문제를 해결하기 위하여, 하부전극과 폴리실리콘막 사이에 TiAlN막과 같은 배리어 금속막을 적용하는 방법이 제시되었는데, TiAlN막은 TixAl 타겟을 이용하여 질소분위기에서 반응성 스퍼터링(reactive sputtering)으로 형성하는데, 증착조건에 따라 다양한 특성을 갖는다.Meanwhile, in order to solve this problem, a method of applying a barrier metal film such as a TiAlN film between the lower electrode and the polysilicon film has been proposed. It has various characteristics depending on the deposition conditions.
즉, TiAlN막의 기본적 구조는 주상정(columar) 구조로서 증착 온도에 따라 우선배향성(texture)이 다르고, 증착온도가 높을수록 비저항이 낮다.That is, the basic structure of the TiAlN film is a columnar structure (columar) structure, the preferred orientation varies depending on the deposition temperature, the higher the deposition temperature, the lower the resistivity.
또한, 원주형 사이의 그레인 바운더리의 패킹(packing)특성이 조밀하지 못하고, [111] 방향의 배향성을 갖는다. 이에 따라, 상기한 배리어 금속막을 적용하여 캐패시터를 형성한 후, 산소 또는 질소 분위기에서 진행되는 후속 열처리 공정에 의해, 캐패시터의 하부전극과 TiAlN의 계면에서 우선산화가 일어날 뿐만 아니라, 포로스 그레인 바운더리(porous grain boundary)를 타고 산화가 촉진되어, 배리어 금속막의 내산화 특성이 열화됨으로써, 결국 소자특성에 치명적인 영향을 미치게 된다.In addition, the packing characteristics of the grain boundaries between the columnar shapes are not dense and have an orientation in the [111] direction. Accordingly, after the capacitor is formed by applying the barrier metal film, a preliminary oxidation occurs at the interface between the lower electrode of the capacitor and TiAlN by a subsequent heat treatment process in an oxygen or nitrogen atmosphere, and a porous grain boundary (porous) Oxidation is promoted through the grain boundary, and the oxidation resistance of the barrier metal film is deteriorated, resulting in a fatal effect on device characteristics.
또한, TiAlN은 그의 조성(Ti1-xAlxN)에서 x가 0.25 이상이 될 때, TiN에 비하여 200 내지 300℃ 이상의 고온에서 안정성를 갖지만, 이때 TiAlN 표면에서 Al2O3막의 생성이 촉진되어 저항이 증가한다.In addition, TiAlN has stability at a high temperature of 200 to 300 ° C or higher than TiN when x is 0.25 or more in its composition (Ti 1-x Al x N), but at this time, the formation of Al 2 O 3 film is promoted on the TiAlN surface. Resistance increases.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위하여 안출한 것으로, 캐패시터와 하부배선층 사이에 배리어 금속막을 적용하는 경우에, 후속 열처리시 배리어 금속막의 내산화 특성을 향상시킬 수 있는 반도체 메모리 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and when the barrier metal film is applied between the capacitor and the lower wiring layer, the semiconductor memory device can improve the oxidation resistance of the barrier metal film during subsequent heat treatment. The purpose is to provide a manufacturing method.
도 1은 본 발명의 실시예에 따른 반도체 메모리 소자의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
10 : 반도체 기판 11 : 접합영역10 semiconductor substrate 11 junction region
12 : 층간절연막 13 : 도핑된 폴리실리콘막12 interlayer insulating film 13 doped polysilicon film
14 : 티타늄 실리사이드막 100 : 하부배선층14: titanium silicide film 100: lower wiring layer
15 : 배리어 금속막15: barrier metal film
15A, 15B, 15C : 제 1 내지 제 2 TiAlN막15A, 15B, 15C: First to Second TiAlN Films
16 : 하부전극 17 : 유전체막16: lower electrode 17: dielectric film
18 : 상부전극 200 : 캐패시터18: upper electrode 200: capacitor
상기 목적을 달성하기 위한 본 발명에 따른 반도체 메모리 소자는 하부전극과 고유전율을 갖는 유전체막과 상부전극으로 이루어진 캐패시터와, 상기 하부전극 하부의 하부배선층을 구비하고, 상기 하부전극과 상기 하부배선층 사이에 배리어 금속막을 구비한다. 여기서, 배리어 금속막은 제 1 내지 제 3 TiAlN막을 0 내지 500℃의 온도범위에서 온도를 달리하여 각각 증착하여 형성하고, 각각의 TiAlN막의 증착후에는 막에 대한 표면처리를 각각 진행한다.In accordance with another aspect of the present invention, a semiconductor memory device includes a capacitor including a lower electrode, a dielectric film having a high dielectric constant, and an upper electrode, and a lower wiring layer below the lower electrode, and between the lower electrode and the lower wiring layer. The barrier metal film is provided. Here, the barrier metal film is formed by depositing the first to third TiAlN films at different temperatures in a temperature range of 0 to 500 ° C., and after the deposition of each TiAlN film, the surface treatment is performed on the films.
또한, 제 1 TiAlN막은 100 내지 500℃의 온도에서 증착하고, 제 2 TiAlN막은 0 내지 300℃에서 증착하고, 제 3 TiAlN막은 300 내지 500℃의 온도에서 증착한다. 또한, 제 1 TiAlN막의 표면처리는 질소나 산소 플라즈마를 이용하여 진행하고, 제 2 TiAlN막의 표면처리는 산소 플라즈마를 이용하여 진행하고, 제 3 TiAlN막의 표면처리는 질소 플라즈마를 이용하여 진행한다.In addition, the first TiAlN film is deposited at a temperature of 100 to 500 ° C, the second TiAlN film is deposited at 0 to 300 ° C, and the third TiAlN film is deposited at a temperature of 300 to 500 ° C. The surface treatment of the first TiAlN film is carried out using nitrogen or oxygen plasma, the surface treatment of the second TiAlN film is performed using oxygen plasma, and the surface treatment of the third TiAlN film is performed using nitrogen plasma.
이하, 본 발명에 따른 반도체소자의 메모리소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a memory device of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 실시예에 따른 반도체 메모리 소자의 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
본 발명의 실시예에 따른 반도체메모리소자의 제조방법은, 도 1에 도시된 바와같이, 내부에 접합영역(11)이 구비되고 상부에 접합영역(11)의 일부를 노출시키는 캐패시터용 콘택홀을 구비한 층간절연막(12)이 형성되고, 상기 콘택홀에 캐패시터의 하부배선층(100)이 플러그 형태로 형성된 반도체 기판(10)을 준비한다.In the method of manufacturing a semiconductor memory device according to an embodiment of the present invention, as shown in FIG. 1, a junction region 11 is provided therein and a capacitor contact hole for exposing a portion of the junction region 11 thereon. The interlayer insulating layer 12 is formed, and the semiconductor substrate 10 having the lower wiring layer 100 of the capacitor in the form of a plug is prepared in the contact hole.
이때, 상기 하부배선층(100)은 플러그 공정에 의해 형성되고, 도핑된 폴리실리콘막(13)과 티타늄-실리사이드막(14)의 적층막으로 이루어진다. 또한, 폴리실리콘막(13)의 두께는 100 내지 4,000Å이고, 티타늄 실리사이드막(14)의 두께는 100 내지 1,000Å이다.In this case, the lower wiring layer 100 is formed by a plug process and is formed of a laminated film of the doped polysilicon film 13 and the titanium-silicide film 14. In addition, the thickness of the polysilicon film 13 is 100-4,000 kPa, and the thickness of the titanium silicide film 14 is 100-1,000 kPa.
그다음, 상기 반도체 기판(10) 상에 3층 구조의 배리어 금속막(15)을 형성한다. 이때, 본 발명에서는 배리어 금속막(15)의 고온 내산화특성을 향상시키기 위하여, 적어도 하나 이상의 TiAlN 박막의 적층막으로 형성하고, TiAlN 박막은 각각의 챔버에서 다른 온도로 증착함과 더불어 증착 후 각각의 TiAlN 박막을 질소나 산소 플라즈마를 이용하여 표면처리하여, TiAlN 박막의 그레인 바운더리를 질소나 산소로 채워줌으로써 각 계면을 비정질화시킨다. 또한, 표면에서의 Al2O3막의 형성을 최소화하기 위하여, 최상부의 TiAlN막의 Al 조성을 15 내지 25%로 하고, 최종 TiAlN막의 표면은 질소 플라즈마를 이용하여 처리한다.Next, a barrier metal film 15 having a three-layer structure is formed on the semiconductor substrate 10. At this time, in the present invention, in order to improve the high temperature oxidation resistance of the barrier metal film 15, at least one TiAlN thin film is formed of a laminated film, the TiAlN thin film is deposited at a different temperature in each chamber and after deposition, respectively The TiAlN thin film is surface-treated using nitrogen or oxygen plasma, and the grain boundary of the TiAlN thin film is filled with nitrogen or oxygen to make each interface amorphous. In addition, in order to minimize the formation of the Al 2 O 3 film on the surface, the Al composition of the uppermost TiAlN film is set to 15 to 25%, and the surface of the final TiAlN film is treated using nitrogen plasma.
즉, 먼저 하부배선층(100) 상부에 제 1 TiAlN막(15A)을 100 내지 500℃의 온도와, 5 내지 15KW의 전력과, 5 내지 30mTorr의 압력에서, 30 내지 130sccm의 N2개스 및 10 내지 50 sccm의 Ar 개스를 이용하여 증착하고, 질소나 산소 플라즈마를 이용하여 표면처리한다. 여기서, 질소 플라즈마는 N2또는 NH3를 이용하고, 산소 플라즈마는 O2또는 N2O를 이용한다.That is, first, the first TiAlN film 15A on the lower wiring layer 100 at a temperature of 100 to 500 ° C., power of 5 to 15 KW, and pressure of 5 to 30 mTorr, N 2 gas of 30 to 130 sccm and 10 to Deposition is carried out using 50 sccm of Ar gas and surface treatment using nitrogen or oxygen plasma. Here, the nitrogen plasma uses N 2 or NH 3 , and the oxygen plasma uses O 2 or N 2 O.
이어서, 상기 제 1 TiAlN막(15A) 상부에 제 2 TiAlN막(15B)을 0 내지 300℃의 온도와, 5 내지 15KW의 전력과, 5 내지 30mTorr의 압력에서, 30 내지 130sccm의 N2개스 및 10 내지 50sccm의 Ar 개스를 이용하여 증착하고, 산소 플라즈마를 이용하여 표면처리한다. 여기서, 산소 플라즈마는 O2또는 N2O를 이용한다.Subsequently, the second TiAlN film 15B is placed on the first TiAlN film 15A at a temperature of 0 to 300 ° C., power of 5 to 15 KW, pressure of 5 to 30 mTorr, and N 2 gas of 30 to 130 sccm and Deposition is carried out using Ar gas of 10 to 50 sccm and surface treatment using oxygen plasma. Here, the oxygen plasma uses O 2 or N 2 O.
그다음, 상기 제 2 TiAlN막(15B) 상부에 제 3 TiAlN막(15C)을 300 내지 500℃의 온도와, 5 내지 15KW의 전력과, 5 내지 30mTorr의 압력에서, 30 내지 130sccm의 N2개스 및 10 내지 50sccm의 Ar 개스를 이용하여 증착하고, 질소 플라즈마를 이용하여 표면처리한다. 여기서, 질소 플라즈마는 N2또는 NH3를 이용하고, 제 3 TiAlN막(15C)의 Al 조성은 15 내지 25%이다.Then, the third TiAlN film 15C was placed on the second TiAlN film 15B at a temperature of 300 to 500 ° C., power of 5 to 15 KW, pressure of 5 to 30 mTorr, and N 2 gas of 30 to 130 sccm and Deposition is carried out using Ar gas of 10 to 50 sccm and surface treatment using nitrogen plasma. Here, the nitrogen plasma uses N 2 or NH 3 , and the Al composition of the third TiAlN film 15C is 15 to 25%.
이어서, 배리어 금속막(15) 상부에 하부전극(16), 유전체막(17), 및 상부전극(18)의 적층구조로 이루어진 캐패시터(200)를 형성한다. 여기서, 하부전극(16)은 Pt, Ir, IrO2, Ru, RuO2로 구성된 그룹으로부터 선택되는 하나의 막으로 형성하고, 유전체막(17)은 Ta2O5, Al2O3, BST, SBT로 구성된 그룹으로부터 선택되는 하나의 막으로 형성한다.Subsequently, a capacitor 200 having a stacked structure of the lower electrode 16, the dielectric film 17, and the upper electrode 18 is formed on the barrier metal film 15. Here, the lower electrode 16 is formed of one film selected from the group consisting of Pt, Ir, IrO 2 , Ru, and RuO 2 , and the dielectric film 17 is formed of Ta 2 O 5 , Al 2 O 3 , BST, It is formed into one film selected from the group consisting of SBT.
또한, 상기한 실시예에서와는 달리 배리어 금속막(15)을 제 1 내지 제 3 TiAlN막(15A, 15B, 15C)의 증착순서를 변경하여 형성할 수 있다.Unlike the above-described embodiment, the barrier metal film 15 may be formed by changing the deposition order of the first to third TiAlN films 15A, 15B, and 15C.
상기한 본 발명에 따른 반도체소자의 제조방법에 있어서는, 배리어 금속막을 적어도 하나 이상의 TiAlN 박막을 서로 다른 온도로 각각의 챔버에서 형성하기 형성함과 더불어 산소나 질소 플라즈마를 이용하여 표면처리하므로써 배리어 금속막의 구조가 이퀴액스(equi-axed) 또는 아몰포스(amorphous) 구조로 변경되어, 고온내산화 특성이 향상되어 배리어로서의 장점이 극대화됨으로써, 결국 소자의 특성이 향상된다.In the above-described method of manufacturing a semiconductor device, the barrier metal film is formed by forming at least one TiAlN thin film in each chamber at different temperatures and by surface treatment using oxygen or nitrogen plasma. The structure is changed to an equi-axed or amorphous structure, thereby improving the high temperature oxidation resistance to maximize the advantages as a barrier, thereby improving the device characteristics.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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