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KR100291412B1 - Method for applying photoresist - Google Patents

Method for applying photoresist Download PDF

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Publication number
KR100291412B1
KR100291412B1 KR1019980002771A KR19980002771A KR100291412B1 KR 100291412 B1 KR100291412 B1 KR 100291412B1 KR 1019980002771 A KR1019980002771 A KR 1019980002771A KR 19980002771 A KR19980002771 A KR 19980002771A KR 100291412 B1 KR100291412 B1 KR 100291412B1
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KR
South Korea
Prior art keywords
photoresist
insulating layer
region
semiconductor substrate
peripheral region
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KR1019980002771A
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Korean (ko)
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KR19990068875A (en
Inventor
나상훈
이상원
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김영환
현대반도체 주식회사
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Priority to KR1019980002771A priority Critical patent/KR100291412B1/en
Publication of KR19990068875A publication Critical patent/KR19990068875A/en
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Publication of KR100291412B1 publication Critical patent/KR100291412B1/en

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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: A method for applying a photoresist is provided to prevent an exposure error generated from an exposure process by compensating a stepped portion generated between a center region and a peripheral region. CONSTITUTION: An insulating layer is formed by depositing a silicon oxide on a semiconductor substrate(200) having a stepped portion. The first photoresist is laminated on the insulating layer. A pattern of a mask is copied on the first photoresist by using a mask. The first photoresist pattern is formed by copying the pattern of the mask on the first photoresist. The insulating layer is removed partially by using the first photoresist pattern as an etch mask. The first photoresist pattern is removed. The second photoresist(208) is applied on a whole surface of the above structure.

Description

포토레지스트 도포방법Photoresist coating method

본 발명은 단차가 심한 반도체기판에 포토레지스트를 도포하는 방법에 관한 것으로, 특히, 소자 등이 형성된 중심영역과 중심영역의 가장자리 부위인 주변영역에 발생된 단차를 보상함으로써 이 후의 노광공정에서 야기되는 노광 불량을 방지하기에 적당한 포토레지스트 도포방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of applying a photoresist to a semiconductor substrate having a high level of step, and in particular, to compensate for a step generated in a center area where elements, etc. are formed, and a peripheral area that is an edge of the center area. A photoresist coating method suitable for preventing exposure failure.

도 1은 통상적인 반도체기판을 도시한 평면도이고, 도 2는 도 1을 l-l`선으로 절단한 단면도로, 종래기술에 따른 포토레지스트를 도포한 공정단면도이다.FIG. 1 is a plan view showing a conventional semiconductor substrate, and FIG. 2 is a cross-sectional view taken along line 1-1 of FIG. 1, and is a cross-sectional view of a process of applying a photoresist according to the prior art.

도 1 및 도 2 와 같이, 반도체기판(10)은 소자 등이 형성된 중심영역(12)(도 2에서는 Ⅰ로 표시된 영역)과, 이 중심영역의 가장자리 부위에는 소자 등이 형성되지 않은 주변영역(14)(도 2에서는 Ⅱ 로 표시된 영역)으로 나뉘어진다.1 and 2, the semiconductor substrate 10 includes a center region 12 (region indicated by I in FIG. 2) in which an element or the like is formed, and a peripheral region in which no element or the like is formed in the edge portion of the center region. 14) (the area indicated by II in Fig. 2).

통상적으로 중심영역(Ⅰ)에는 다층의 적층 또는 식각 공정이 진행됨에 따라 반도체 소자가 형성되지만, 그 가장자리 부위인 주변영역(Ⅱ)에는 소자가 형성되지 않으므로, 소자가 형성되는 중심영역(Ⅰ)에 비해 그 표면이 낮아 이들 두 영역(Ⅰ)(Ⅱ)들 사이에는 단차가 발생된다. 즉, 단면구조를 살펴보면, 도 2에서와 같이, 중심영역(Ⅰ)은 주변영역(Ⅱ)에 비해 기판 표면으로부터 볼록한 형상을 갖는다.Typically, a semiconductor device is formed as a multi-layer stacking or etching process is performed in the central area (I), but the device is not formed in the peripheral area (II), which is an edge portion thereof, and thus, in the central area (I) where the device is formed. In contrast, the surface is low, and a step is generated between these two regions (I) and (II). That is, the cross-sectional structure of the present invention, as shown in Figure 2, the central region (I) has a convex shape from the substrate surface compared to the peripheral region (II).

따라서, 종래에는 이 단차진 반도체기판(100), 정확히는, 중심영역(Ⅰ)과 주변영역(Ⅱ) 전표면에 금속층 등을 적층한 후, 이 금속층 전면에 금속층 패터닝을 위한 마스크 제조를 위한 포토레지스트(110)를 도포하였다.Therefore, conventionally, a stepped semiconductor substrate 100, or more specifically, a metal layer or the like is laminated on the entire surface of the center region (I) and the peripheral region (II), and then a photoresist for fabricating a mask for patterning the metal layer on the entire metal layer. (110) was applied.

이 후, 도면에는 도시되지는 않았지만, 반도체기판(100) 상에 도포된 포토레지스트를 노광 및 현상함으로써 하부의 금속층을 패터닝하기 위한 마스크패턴을 형성하였다.Thereafter, although not shown in the figure, a mask pattern for patterning the lower metal layer was formed by exposing and developing the photoresist applied on the semiconductor substrate 100.

그러나, 종래기술에서는 포토레지스트 표면에도 역시 금속층과 동일한 형상을 갖으면서 단차가 발생되었다. 따라서, 단차가 심한 포토레지스트를 노광할 시에, 포토레지스트의 중심영역과 주변영역에는 포커스 에러 등의 노광불량이 발생됨에 따라 패턴이 불량하게 되는 문제점이 있었다.However, in the prior art, a step is generated on the surface of the photoresist while also having the same shape as the metal layer. Therefore, when exposing a photoresist having a high level of difference, a poor pattern such as a focus error occurs in the center region and the peripheral region of the photoresist.

상기의 문제점을 해결하고자, 본 발명의 목적은 반도체기판의 중심영역과 주변영역 간의 단차로 인해 발생되는 노광불량을 방지할 수 있는 포토레지스트 도포방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a photoresist coating method that can prevent the exposure failure caused by the step between the center region and the peripheral region of the semiconductor substrate.

따라서, 본 발명의 포토레지스트 도포방법에서는 단차진 중심영역과 주변영역의 표면을 평탄화 후에 포토레지스트를 도포시킴으로써 노광 시에 발생되는 불량을 방지하려는 것이다.Therefore, in the photoresist coating method of the present invention, the defects caused during exposure are prevented by applying photoresist after flattening the surface of the stepped center region and the peripheral region.

본 발명의 포토레지스트 도포방법은 소자가 형성된 중심영역과 중심영역의 가장자리인 소자가 형성되지 않은 주변영역으로 나뉜 단차진 반도체기판 상에 중심영역과 대응된 부위는 노출되고 주변영역과 대응된 부위는 잔류되도록 절연층을 형성하는 공정과, 절연층을 포함한 반도체기판 상에 포토레지스트를 도포하는 공정을 구비한 것이 특징이다.In the photoresist coating method of the present invention, a portion corresponding to the center region is exposed and a portion corresponding to the peripheral region is divided on a stepped semiconductor substrate which is divided into a center region in which the element is formed and a peripheral region in which the element is not formed. And a step of forming an insulating layer so as to remain, and a step of applying a photoresist on the semiconductor substrate including the insulating layer.

도 1은 패턴이 형성된 통상적인 반도체기판을 도시한 평면도.1 is a plan view showing a conventional semiconductor substrate on which a pattern is formed.

도 2는 도 1을 l-l`선으로 절단한 단면도로, 종래기술에 따른 포토레지스트를 도포한 공정단면도.FIG. 2 is a cross-sectional view taken along line 1 ′ of FIG. 1 and a process cross-sectional view of applying a photoresist according to the prior art. FIG.

도 3a 내지 도 3d 는 본 발명에 따른 포토레지스트를 도포하는 단계를 보인 공정단면도이다.3A to 3D are cross-sectional views illustrating a process of applying a photoresist according to the present invention.

*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200. 반도체기판 110, 210. 포토레지스트층100, 200. Semiconductor substrate 110, 210. Photoresist layer

206. 마스크 210. 절연층206. Mask 210. Insulation layer

Ⅰ`,Ⅰ. 소자영역 Ⅱ`,Ⅱ. 주변영역Ⅰ`, Ⅰ. Device Area II and II. Surrounding area

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 3a 내지 도 3d 는 본 발명에 따른 포토레지스트를 도포하는 단계를 보인 공정단면도이다.3A to 3D are cross-sectional views illustrating a process of applying a photoresist according to the present invention.

도 3a 와 같이, 도면에 도시된 반도체기판(200)은 소자 등이 형성된 중심영역(Ⅰ`) 및 중심영역의 가장자리 부위인 주변영역(Ⅱ`)으로 나뉘어진다. 즉, 통상적으로, 중심영역(Ⅰ`)에는 다층의 적층 또는 식각 공정이 진행됨에 따라 반도체 소자가 형성되지만, 그 가장자리 부위인 주변영역(Ⅱ`)에는 소자가 형성되지 않으므로, 소자가 형성되는 중심영역(Ⅰ`)에 비해 그 표면이 낮아 이들 두 영역(Ⅰ`)(Ⅱ`)들 사이에는 단차가 발생되며, 중심영역(Ⅰ`)은 주변영역(Ⅱ`)에 비해 기판 표면으로부터 볼록한 형상을 갖는다.As shown in FIG. 3A, the semiconductor substrate 200 illustrated in the drawing is divided into a central region I ′ in which elements and the like are formed, and a peripheral region II ′ which is an edge portion of the central region. That is, in general, a semiconductor device is formed as a multi-layer stacking or etching process is performed in the central region I ′, but a device is not formed in the peripheral region II ′, which is an edge portion thereof, and thus a center is formed. The surface is lower than that of the region I ′, and a step is generated between these two regions I ′ and II ′, and the central region I ′ is convex from the substrate surface compared to the peripheral region II ′. Has

이 단차가 발생된 반도체기판(200) 상에 산화실리콘 등을 HLD(High temperature Low pressure Deposition) 방법으로 증착하여 절연층(204)을 형성한다. 이 때, 절연층(204)의 두께는 중심영역(Ⅰ`)과 주변영역(Ⅱ`) 간의 단차진 두께만큼 형성된다.Silicon oxide or the like is deposited on the stepped semiconductor substrate 200 by a high temperature low pressure deposition (HLD) method to form an insulating layer 204. At this time, the thickness of the insulating layer 204 is formed by the stepped thickness between the central region I 'and the peripheral region II'.

도 3b 와 같이, 절연층(204) 상에 제 1포토레지스트(210)를 적층하여 도포한다.As shown in FIG. 3B, the first photoresist 210 is laminated and coated on the insulating layer 204.

그리고 마스크(206)를 이용함으로써 제 1포토레지스트(210)에 이 마스크에 형성된 패턴과 동일한 형상을 전사시킨다. 상술한 마스크(206)는 반도체기판(200) 상의 중심영역(Ⅰ`)이 노출되고 주변영역(Ⅱ`)이 덮이도록 패터닝되어 있다.By using the mask 206, the first photoresist 210 is transferred to the same shape as the pattern formed in the mask. The mask 206 described above is patterned such that the central region I ′ on the semiconductor substrate 200 is exposed and the peripheral region II ′ is covered.

도 3c 와 같이, 상술한 과정에서 패터닝된 제 1포토레지스트 패턴(210a)은 도면에 도시된 바와 같이, 절연층(204) 상에 주변영역(Ⅱ`)과 대응된 부위에만 형성되어 있고, 중심영역(Ⅰ`)과 대응된 부위는 노출되어 절연층(204)의 일부를 노출시킨다.As shown in FIG. 3C, the first photoresist pattern 210a patterned in the above-described process is formed only on a portion of the insulating layer 204 corresponding to the peripheral region II ′, as shown in FIG. The portion corresponding to the region I` is exposed to expose a portion of the insulating layer 204.

이 후, 제 1포토레지스트 패턴(210a)을 식각마스크로 이용하여 중심영역(Ⅰ`)과 대응된 부위의 절연층(204)을 제거한다.Thereafter, the insulating layer 204 of the portion corresponding to the central region I ′ is removed using the first photoresist pattern 210a as an etching mask.

도 3d 와 같이, 제 1포토레지스트 패턴(210a)을 제거한다.As shown in FIG. 3D, the first photoresist pattern 210a is removed.

따라서, 반도체기판(200)상에는 주변영역(Ⅱ`)에만 절연층(204a)이 잔류되어 있고, 그 중심영역(Ⅰ`)은 노출됨으로써 표면이 평탄화되어 있는 상태이다.Therefore, the insulating layer 204a remains only in the peripheral region II 'on the semiconductor substrate 200, and the center region I` is exposed, and thus the surface is flattened.

이 후, 평탄화된 상기 구조 전면에 제 2포토레지스트(208)을 도포한다.A second photoresist 208 is then applied over the planarized structure.

본 발명에서는 단차진 주변영역에 별도로 중심영역과의 단차진 두께 차이만큼 절연층을 형성하여 표면을 평탄화시킨 후에 포토레지스트를 도포한다.In the present invention, an insulating layer is formed in the peripheral region of the stepped region by a difference in thickness from the center region, and the photoresist is applied after the surface is planarized.

즉, 주변영역의 반도체기판에 중심영역 과의 단차진 두께만큼 절연층을 형성시킴에 따라, 상술한 절연층이 중심영역과 주변영역 간의 단차를 보상하여 주는 역할을 하게 된다.That is, as the insulating layer is formed on the semiconductor substrate in the peripheral region by the thickness of the stepped region, the above-described insulating layer serves to compensate for the step difference between the central region and the peripheral region.

본 발명에서는 단차진 반도체기판의 중심영역과 주변영역 간의 단차를 보상하여 그 표면을 평탄화가 가능함으로써 노광 시 발생되는 포커스 불량을 방지할 수 있는 잇점이 있다.According to the present invention, it is possible to planarize the surface by compensating the step between the center region and the peripheral region of the stepped semiconductor substrate, thereby preventing the focus failure caused during exposure.

Claims (3)

소자 등이 형성된 중심영역과 중심영역의 가장자리 부위인 소자 등이 형성되지 않은 주변영역으로 구분되는 반도체기판 상에 포토레지스트를 도포하는 방법에 있어서,In the method of applying a photoresist on a semiconductor substrate divided into a central region in which elements, etc. are formed, and a peripheral region in which no elements, etc., which are edge portions of the center region, are formed. 상기 반도체기판 상에 상기 중심영역과 대응된 부위는 노출되고 상기 주변영역과 대응된 부위는 잔류되도록 절연층을 형성하는 공정과,Forming an insulating layer on the semiconductor substrate such that a portion corresponding to the central region is exposed and a portion corresponding to the peripheral region remains; 상기 절연층을 포함한 반도체기판 상에 포토레지스트를 도포하는 공정을 구비한 포토레지스트 도포방법.A photoresist coating method comprising the step of applying a photoresist on a semiconductor substrate including the insulating layer. 청구항 1에 있어서,The method according to claim 1, 상기 절연층은 상기 중심영역과 상기 주변영역 간의 단차진 두께만큼 형성된 것이 특징인 포토레지스트 도포방법.And the insulating layer is formed to have a stepped thickness between the central region and the peripheral region. 청구항 1 또는 청구항 2에 있어서,The method according to claim 1 or 2, 상기 절연층은 HLD(High temperature Low pressure Deposition) 방법으로 형성한 것이 특징인 포토레지스트 도포방법.The insulating layer is a photoresist coating method characterized in that formed by a high temperature low pressure deposition (HLD) method.
KR1019980002771A 1998-02-02 1998-02-02 Method for applying photoresist KR100291412B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960043027A (en) * 1995-05-04 1996-12-21 김주용 Planarization method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960043027A (en) * 1995-05-04 1996-12-21 김주용 Planarization method of semiconductor device

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