KR100290919B1 - Method for manufacturing thin film transistor - Google Patents

Abstract

PURPOSE: A fabrication method of a thin film transistor is provided to simplify a fabrication process of a thin film transistor by forming an etch stopper layer and an amorphous silicon layer simultaneously using a photo etch process, thereby enhancing a yield and a characterize of the thin film transistor. CONSTITUTION: A gate electrode(2) is formed on a transparent substrate(1). A gate insulating layer(3), a semiconductor layer(4), an etch stopper layer(5) and a photoresist layer are deposited sequentially on the substrate in which the gate electrode is formed. After patterning the photoresist layer by a back exposure using the gate electrode as a mask, the etch stopper layer(5) and the semiconductor layer(4) are taper etched at same time and the semiconductor layer is patterned in a narrower width than the gate electrode. After depositing an impurity semiconductor layer(6) and a metal on an entire surface and annealing thereof, the impurity semiconductor layer and the metal is removed selectively, a source/drain electrode(7,8) is formed.

Description

[Name of invention]

Method of manufacturing thin film transistor

[Brief Description of Drawings]

1 is a cross-sectional view of a conventional thin film transistor

2 is a cross-sectional view of a conventional thin film transistor process

3 is a cross-sectional view of a thin film transistor of the present invention

4 is a cross-sectional view of a thin film transistor process of the present invention.

5 is a cross-sectional view of a thin film transistor process according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1. Substrate 2. Gate Electrode

3. Gate insulating film 4. Semiconductor layer

5. Etch stopper 6. Impurity semiconductor layer

7,8. Source / drain electrodes 9. Photoresist

10. Metal

Detailed description of the invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor, wherein an etch stopper layer and an amorphous silicon layer are formed in one photoetch process so as to be suitable for improving thin film transistor characteristics.

Referring to the conventional thin film transistor with reference to the accompanying drawings as follows.

1 is a cross-sectional view of a structure of a conventional thin film transistor, and FIG. 2 is a cross-sectional view of a conventional thin film transistor process. The gate electrode 2 of Al, Ta, Cr, etc., which is an opaque metal, is formed on a transparent insulating substrate 1 as in drafting (a). ), A gate insulating layer 3, a semiconductor layer 4, and an etch stopper layer 5 are formed thereon by CVD (Chemical Vapor Deposition).

Here, SiNx, SiOx, etc. are used for the gate insulating film 3, and the etch stopper layer 5 is SiNx.

The etch stopper layer 5 is patterned by a photoetch process as shown in FIG. 2 (b), and the n ⁺ a-Si: H layer, which is the impurity semiconductor layer 6, is formed on the entire surface as shown in FIG. Next, as illustrated in FIG. 2D, the semiconductor layer 4 and the impurity semiconductor layer 6 are patterned.

A thin film transistor is fabricated by depositing a metal thereon and patterning the source / drain electrodes 7 and 8 by a photoetch process.

However, in the conventional thin film transistors, the width of the semiconductor layer is larger than the width of the gate electrode, so that the backlight is incident on the semiconductor layer when the TFT-LCD is driven. In particular, the LCD for OHP (Over Head Projector) is an LCD for OA. Since the light amount of the backlight is 40 times or more, electrons are excited in the semiconductor layer, thereby increasing leakage current, and as a result, the on / off ratio of the thin film transistor is reduced, thereby degrading performance.

In addition, since the etch stopper layer and the photoetch process of the semiconductor layer are separately performed, there is a problem that the process becomes complicated.

The present invention has been made to solve the above problems is to improve the characteristics of the thin film transistor.

Hereinafter, a method of manufacturing the thin film transistor of the present invention for achieving the above object will be described with reference to the curved sheet.

3 is a cross-sectional view of the thin film transistor structure of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor process of the present invention, and the gate insulating film 3 is formed on the glass substrate 1 on which the gate electrode 2 is patterned as shown in FIG. ), The semiconductor layer 4 and the etch stopper layer 5 are continuously deposited by a CVD apparatus, and then the photosensitive film 9 is deposited and back exposed to mask pattern the photosensitive film 9.

As illustrated in FIG. 4B, the etch stopper layer 5 and the semiconductor layer 4 are etched in one step.

At this time, the etching technique may wet-etch the etch stopper layer 5 first with a BOE solution, and dry-etch the semiconductor layer 4 with CF ₄ + O ₂ or C ₂ CIF ₅ : 0 ₂ gas. ) Is amorphous silicon, it is possible to perform taper etching below 20 ° by using C ₂ CIF ₅ : 0 ₂ = 5: 4 ratio gas.

Alternatively, both the etch stopper layer 5 and the semiconductor layer 4 can be patterned by dry etching. When the etch stopper layer 5 is mainly used with SiNx, C ₂ CIF ₅ : SF ₆ : Using a gas ratio of 0 ₂ = 6: 4: 3 allows the two layers to be tapered etched.

As shown in FIG. 4 (c), the impurity semiconductor layer 6 and the metal 10 are deposited on the entire surface to selectively remove the impurity semiconductor layer 6 and the metal 10 in the channel region so that the source / drain electrodes 7, 8) to form a thin film transistor of the present invention.

5 is a cross-sectional view illustrating a thin film transistor process according to another embodiment of the present invention. The gate insulating film 3 and the semiconductor layer 4 are etch stoppers on the glass substrate 1 on which the gate electrode 2 is patterned as shown in FIG. After the layer 5 is continuously deposited and the photoresist film is deposited, the back exposure is performed to taper etch the etch stopper layer 5 and the semiconductor layer 4 as shown in Figs. 5A and 5B.

As shown in FIG. 5 (b), the impurity semiconductor layer 6 is formed by ion doping a highly dynamic n-type impurity on the exposed surface of the semiconductor layer 4, and the metal 10 is deposited as shown in FIG. do.

As shown in FIG. 5 (d), heat treatment is performed to form silicide 10 a at the interface between the impurity semiconductor layer 6 and the metal 10, and then the metal 10 is removed to the height of the etch stopper layer 5. Since the drain electrodes 7 and 8 are formed, a thin film transistor is manufactured.

In the method of manufacturing the thin film transistor of the present invention as described above, since the semiconductor layer exists only on the upper portion of the gate electrode, it is possible to prevent deterioration of characteristics due to the backlight, and to simplify the patterning process of the etch stopper layer and the semiconductor layer, When thin film transistors are applied to LCDs by improving their characteristics, the image quality of LCDs can be improved.

Claims (5)

A first process of forming a gate electrode on the transparent substrate, a second process of sequentially depositing a gate insulating film, a semiconductor layer, an etch stopper layer and a photoresist film on the transparent substrate on which the gate electrode is formed, and a back exposure using the gate electrode as a mask. A third step of patterning the semiconductor layer to a width smaller than the width of the gate electrode by simultaneously tapering etching the etch stopper layer and the semiconductor layer after patterning the photoresist layer, depositing an impurity semiconductor layer and a metal on the entire surface, and performing heat treatment. And removing the impurity semiconductor layer and the metal corresponding to the channel portion to form a source / drain electrode. The method of claim 1, wherein a width of the semiconductor layer is greater than that of an etch stopper layer. 2. The method of claim 1, wherein the etch stopper layer and the semiconductor layer are tapered and then n-type ion implanted on the surface of the semiconductor layer to form an impurity semiconductor layer, followed by depositing a metal and heat treatment to form a silicide source / drain electrode. Thin film transistor manufacturing method characterized in that. The method of claim 1, wherein the simultaneous taper etching of the etch stopper layer and the semiconductor layer comprises wet etching the etch stopper layer with a BOE solution and dry etching the semiconductor layer with CF ₄ + O ₂ or C ₂ ClF ₅ + O ₂ gas. Thin film transistor manufacturing method characterized in that. The method of claim 1, wherein the etching of the etch stopper layer and the semiconductor layer is performed using an etching gas at a ratio of C ₂ ClF ₅ : SF ₆ : O ₂ = 6: 4: 3. Way.