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KR100265342B1 - Metallization process for semiconductor device using pvd method - Google Patents

Metallization process for semiconductor device using pvd method Download PDF

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KR100265342B1
KR100265342B1 KR1019970078024A KR19970078024A KR100265342B1 KR 100265342 B1 KR100265342 B1 KR 100265342B1 KR 1019970078024 A KR1019970078024 A KR 1019970078024A KR 19970078024 A KR19970078024 A KR 19970078024A KR 100265342 B1 KR100265342 B1 KR 100265342B1
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film
forming
semiconductor device
metal
interlayer insulating
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KR1019970078024A
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KR19990057945A (en
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이성권
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A forming method is to improve electric conductivity, electromigration and stress-migration so as to provide a stable PVD(physical vapor deposition) metal interconnect of a semiconductor device, thereby increasing reliability of the device. CONSTITUTION: The first and second interlayer dielectrics with etching selectivity are successively formed on a lower layer formed on a semiconductor substrate(10). The second and first interlayer dielectrics are successively selective-etched to form a recess in a metal interconnect forming region to form an undercut portion under the second interlayer dielectric. A metal layer is deposited on the entire structure using a collimated PVD process. An anti-oxidative layer(15) for metal layer is formed on the entire structure using an MOCVD process. The anti-oxidative layer and the metal layer outside the recess are removed by an etch-back process, leaving the anti-oxidative layer on the metal layer inside the recess.

Description

물리증착 방식을 사용한 반도체 장치의 금속배선 공정Metal wiring process of semiconductor device using physical vapor deposition

본 발명은 반도체 제조 분야에 관한 것으로, 특히 물리증착 방식을 사용한 초고집적 반도체 소자의 금속배선 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a metal wiring process of an ultra-high density semiconductor device using a physical vapor deposition method.

구리(Cu)는 원자의 크기가 매우 작고 화학적인 친화도가 매우 크기 때문에 쉽게 산화되고 실리콘 기판이나 산화막으로 쉽게 확산하여 들어감으로 소자의 특성을 크게 열화(degradation) 시키는 문제점이 있으며, 그 금속배선 재료로서 구리 박막을 이용할 것이 유력시되는 차세대 초고집적 소자는 매우 작은 디자인 룰(design rule)을 갖기 때문에 구리 박막의 증착시 단차피복성(step coverage)이 양호한 화학기상증착(CVD) 방식을 사용하여야 한다. 그러나, 아직까지 구리 박막의 증착 공정기술 개발은 물리증착(PVD) 방식을 사용한 구리 박막의 증착은 용이하나 화학기상증착 방식을 사용한 구리 박막의 증착은 용이하지 않은 실정이다. 이러한 문제점은 구리 금속배선에 국한되지 않고 Au, Ag, Co, Cr, Ni, Pt를 사용한 초고집적 소자의 금속배선 공정에서도 나타난다. 따라서, 물리증착 방식의 금속배선 공정을 개선하는 기술의 개발이 필요하다.Since copper (Cu) has a small atom size and a high chemical affinity, it easily oxidizes and easily diffuses into a silicon substrate or an oxide film, thereby greatly degrading device characteristics. Next-generation ultra-high density devices, which are likely to use copper thin films, have very small design rules, and therefore, a chemical vapor deposition (CVD) method having good step coverage during deposition of copper thin films should be used. However, the development of copper thin film deposition process technology is still easy to deposit a copper thin film using a physical vapor deposition (PVD) method, but the deposition of a copper thin film using a chemical vapor deposition method is not easy. This problem is not limited to copper metallization, but also occurs in the metallization process of ultra-high integration devices using Au, Ag, Co, Cr, Ni, and Pt. Therefore, there is a need for the development of a technique for improving the physical wiring metal wiring process.

본 발명은 금속배선의 산화 및 금속의 확산을 방지하며, 우수한 단차피복성을 제공하는 물리증착 방식을 사용한 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wiring in a semiconductor device using a physical vapor deposition method that prevents oxidation of metal wiring and diffusion of metal and provides excellent step coverage.

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 반도체 장치의 금속배선 형성 공정도.1A through 1E are diagrams illustrating a process of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 기판 11 : BPSG막10 substrate 11 BPSG film

12 : CVD 산화막 13 : 장벽 금속막12 CVD oxide film 13 barrier metal film

14 : 구리 박막 15 : 내산화막14 copper thin film 15 oxidation resistant film

본 발명으로부터 제공되는 반도체 장치의 금속배선 형성방법은 반도체 기판 상에 형성된 소정의 하부층 상에 식각 선택비를 가지는 제1 및 제2 층간 절연막을 차례로 형성하는 제1 단계; 상기 제2 층간 절연막 및 상기 제1 층간 절연막을 차례로 선택 식각하여 금속배선 형성 영역에 홈을 형성하되, 상기 제2 절연막 하부에 언더컷 부분을 형성하는 제2 단계; 전체구조 상부에 콜리메이티드 물리증착 방식을 사용하여 금속막을 증착하는 제3 단계; 전체구조 상부에 유기금속 화학기상증착 방식을 사용하여 상기 금속막의 산화 방지를 위한 내산화막을 형성하는 제4 단계; 및 에치백 공정을 실시하여 상기 홈 외부의 상기 내산화막 및 상기 금속막을 제거하며, 상기 홈 내부의 상기 금속막 상부에 상기 내산화막을 잔류시키는 제5 단계를 포함하여 이루어진다.The method for forming metal wirings of a semiconductor device provided by the present invention includes a first step of sequentially forming first and second interlayer insulating films having an etch selectivity on a predetermined lower layer formed on a semiconductor substrate; Forming a groove in the metal wiring formation region by sequentially etching the second interlayer insulating layer and the first interlayer insulating layer, and forming an undercut portion under the second insulating layer; Depositing a metal film on the entire structure by using a collimated physical vapor deposition method; A fourth step of forming an oxidation resistant film for preventing oxidation of the metal film by using an organometallic chemical vapor deposition method on the entire structure; And a fifth step of performing an etch back process to remove the oxidation resistant film and the metal film outside the groove, and to leave the oxidation resistant film on the metal film inside the groove.

이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

첨부된 도면 도 1a 내지 도 1e는 본 발명의 일실시예에 따른 금속배선 형성 공정을 도시한 것이다.1A to 1E illustrate a metal wiring forming process according to an embodiment of the present invention.

본 발명의 일실시예에 따른 공정은, 우선 도 1a에 도시된 바와 같이 소정의 하부층 공정을 마친 기판(10) 상에 층간 절연막인 BPSG(BoroPhospho Silicate Glass)막(11) 및 CVD 산화막(12)을 차례로 증착하고, CVD 산화막(12) 및 BPSG막(11)을 선택적으로 건식 식각하여 이후 금속배선이 배치될 부분에 홈을 형성한다. 이때, 홈의 선폭은 이후 형성될 금속배선의 선폭을 고려하여 결정한다.According to an embodiment of the present invention, first, as illustrated in FIG. 1A, a BPSG (BoroPhospho Silicate Glass) film 11 and a CVD oxide film 12, which are interlayer insulating films, are formed on a substrate 10 having a predetermined lower layer process. Are deposited in sequence, and the CVD oxide film 12 and the BPSG film 11 are selectively dry etched to form grooves in the portion where the metal wiring is to be subsequently disposed. At this time, the line width of the groove is determined in consideration of the line width of the metal wiring to be formed later.

다음으로, 도 1b에 도시된 바와 같이 불산(HF) 용액 또는 BOE(buffered Oxide Etchant)를 사용하여 습식 식각을 수행하여 CVD 산화막(12) 하부에 언더컷(undercut) 부분을 형성한다. 이때, 습식 식각을 수행하면 CVD 산화막(12)에 비해 불순물을 포함하고 있는 BPSG막(11)에 대한 식각 선택비가 높기 때문에 언더컷 부분을 형성할 수 있게 된다. 이는 후속 콜리메이티드 물리증착(collimated PVD) 방식을 사용한 장벽 금속막과 구리 박막 증착이 홈의 내부에서 측벽과 간격을 두고 이루어지도록 하기 위한 것이다.Next, as shown in FIG. 1B, wet etching is performed using a hydrofluoric acid (HF) solution or a buffered oxide etch (BOE) to form an undercut portion under the CVD oxide layer 12. In this case, when the wet etching is performed, an undercut portion may be formed because the etching selectivity of the BPSG film 11 containing impurities is higher than that of the CVD oxide film 12. This is to ensure that the deposition of the barrier metal film and the copper thin film using the subsequent collimated PVD method is performed at a distance from the side wall in the groove.

이어서, 도 1c에 도시된 바와 같이 콜리메이티드 물리증착(collimated PVD) 방식을 사용하여 장벽 금속막(13)과 구리 박막(14)을 증착한다. 콜리메이티드 물리증착 방식을 사용하면 증착 입자의 직진성이 확보되어 홈의 내부에서는 장벽 금속막(13)과 구리 박막(14)이 측벽과 이격되어 형성되도록 할 수 있다. 여기서, 장벽 금속막(13)으로는 TiN, CoN, Cr, CrN, W, WN, Cr 등이 사용될 수 있다. 이때, 홈 내부에서의 구리 박막(14)의 높이는 BPSG막(11)의 높이 보다 낮게 형성되도록 조절한다. 이는 후속 내산화막 형성시 구리 박막(14) 표면의 피복이 용이하도록 하기 위함이다.Subsequently, the barrier metal film 13 and the copper thin film 14 are deposited using a collimated PVD method as shown in FIG. 1C. When the collimated physical vapor deposition method is used, the straightness of the deposited particles may be secured so that the barrier metal film 13 and the copper thin film 14 may be formed to be spaced apart from the sidewall in the groove. Here, as the barrier metal film 13, TiN, CoN, Cr, CrN, W, WN, Cr, or the like may be used. At this time, the height of the copper thin film 14 in the groove is adjusted to be lower than the height of the BPSG film 11. This is to facilitate coating of the surface of the copper thin film 14 in the subsequent formation of the oxidation resistant film.

계속하여, 도 1d에 도시된 바와 같이 전체구조 상부에 유기금속 화학기상증착(MOCVD; Metal Organic CVD) 방식을 사용하여 금속배선의 산화를 방지하기 위한 내산화막(15)을 증착한다. 이때, 내산화막(15)은 전체구조를 덮도록 충분한 두께로 형성하며, 현재 유기금속 화학기상증착 공정이 개발되어 있고 구리에 대한 내산화성이 있는 물질인 TiN, TaN, W, SiON, CrN, WN, Mo, MoN 등을 사용할 수 있다.Subsequently, as illustrated in FIG. 1D, an oxidation resistant film 15 is deposited on the entire structure to prevent oxidation of the metal wiring by using an organic metal chemical vapor deposition (MOCVD) method. At this time, the oxidation-resistant film 15 is formed to a sufficient thickness to cover the entire structure, and the organic metal chemical vapor deposition process has been developed and the oxidation resistance to copper, TiN, TaN, W, SiON, CrN, WN , Mo, MoN and the like can be used.

다음으로, 도 1e에 도시된 바와 같이 화학·기계적 연마(CMP; Chemical Mechanical Polishing) 공정을 실시하여 홈 외부의 구리 박막(14) 및 장벽 금속막(13)을 제거한다. 이때, 화학·기계적 연마 공정은 CVD 산화막(12)의 일부가 잔류되도록 타겟을 설정하며, 일반적인 에치백 공정으로 대체할 수 있다.Next, as illustrated in FIG. 1E, a chemical mechanical polishing (CMP) process is performed to remove the copper thin film 14 and the barrier metal film 13 outside the groove. In this case, the chemical mechanical polishing process sets a target so that a part of the CVD oxide film 12 remains, and can be replaced by a general etch back process.

상기한 바와 같이 본 발명은 물리증착 방식의 금속 증착 공정을 사용하여 화학기상증착 방식의 금속배선 형성시와 같은 효과를 얻을 수 있다. 즉, 상기와 공정을 통해 장벽 금속막(13) 및 내산화막(15)이 홈 내부에 형성된 구리 박막(14)의 표면을 싸고 있는 구조의 금속배선을 형성함으로써 금속배선의 산화를 방지하고, 금속이 주변의 실리콘 기판이나 층간 절연막으로 확산되는 것을 방지할 수 있다.As described above, the present invention can obtain the same effect as the formation of the chemical vapor deposition metal wiring using the physical vapor deposition metal deposition process. That is, through the above process and the barrier metal film 13 and the oxidation resistant film 15 to form a metal wiring of the structure surrounding the surface of the copper thin film 14 formed in the groove to prevent the oxidation of the metal wiring, Diffusion to the surrounding silicon substrate or interlayer insulation film can be prevented.

상술한 본 발명의 일실시예에서 언더컷 부분을 가진 홈을 형성하기 위한 건식 및 습식 식각을 단 한번의 건식 식각으로 대체할 수 있다. 이러한 공정은 건식 식각에 대한 두 층간 절연막간의 식각 선택비를 조절함으로써 가능하다.In the above-described embodiment of the present invention, dry and wet etching for forming a groove having an undercut portion may be replaced by only one dry etching. This process is possible by adjusting the etch selectivity between the two interlayer dielectrics for dry etching.

상술한 본 발명의 실시예는 구리 금속배선을 일례로 들어 설명하였으나, 본 발명은 Au, Ag, Co, Cr, Ni, Pt등 콜리메이티드 PVD 공정이 가능한 다른 금속을 사용한 금속배선 형성시에도 적용할 수 있다. 또한, 실시예에서는 층간 절연막으로서 BPSG막 및 CVD 산화막을 일례로 들어 설명하였으나, 본 발명은 식각 선택비를 가진 다른 층간 절연막을 짝지워서 사용할 경우에도 적용할 수 있다.Although the above-described embodiment of the present invention has been described by taking copper metal wiring as an example, the present invention is also applicable to the formation of metal wirings using other metals capable of collimated PVD processes such as Au, Ag, Co, Cr, Ni, and Pt. can do. In the embodiment, the BPSG film and the CVD oxide film are described as examples of the interlayer insulating film. However, the present invention can be applied to a case where other interlayer insulating films having an etching selectivity are used in pairs.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

이상에서와 같이 구리(Cu)를 비롯한 Au, Ag, Co, Cr, Ni, Pt를 금속배선 재료로 사용한 안정된 금속배선 공정을 제공함으로써 전기 전도도, 전자 이주(electromigration) 및 스트레스 이주(stressmigration) 특성 등을 개선하여 반도체 장치의 신뢰성을 향상시킬 수 있다.As described above, by providing a stable metallization process using Au, Ag, Co, Cr, Ni, Pt including copper (Cu) as a metallization material, electrical conductivity, electron migration, stress migration characteristics, etc. By improving the reliability of the semiconductor device can be improved.

Claims (10)

반도체 기판 상에 형성된 소정의 하부층 상에 식각 선택비를 가지는 제1 및 제2 층간 절연막을 차례로 형성하는 제1 단계;A first step of sequentially forming first and second interlayer insulating films having an etch selectivity on a predetermined lower layer formed on the semiconductor substrate; 상기 제2 층간 절연막 및 상기 제1 층간 절연막을 차례로 선택 식각하여 금속배선 형성 영역에 홈을 형성하되, 상기 제2 절연막 하부에 언더컷 부분을 형성하는 제2 단계;Forming a groove in the metal wiring formation region by sequentially etching the second interlayer insulating layer and the first interlayer insulating layer, and forming an undercut portion under the second insulating layer; 전체구조 상부에 콜리메이티드 물리증착 방식을 사용하여 금속막을 증착하는 제3 단계;Depositing a metal film on the entire structure by using a collimated physical vapor deposition method; 전체구조 상부에 유기금속 화학기상증착 방식을 사용하여 상기 금속막의 산화 방지를 위한 내산화막을 형성하는 제4 단계; 및A fourth step of forming an oxidation resistant film for preventing oxidation of the metal film by using an organometallic chemical vapor deposition method on the entire structure; And 에치백 공정을 실시하여 상기 홈 외부의 상기 내산화막 및 상기 금속막을 제거하며, 상기 홈 내부의 상기 금속막 상부에 상기 내산화막을 잔류시키는 제5 단계A fifth step of performing an etch back process to remove the oxidation resistant film and the metal film outside the groove, and to leave the oxidation resistant film on the metal film inside the groove; 를 포함하여 이루어진 반도체 장치의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서The method of claim 1 상기 제2 단계 수행후After performing the second step 전체구조 상부에 콜리메이티드 물리증착 방식을 사용하여 장벽 금속막을 형성하는 제6 단계를 더 포함하여 이루어진 반도체 장치의 금속배선 형성방법.And a sixth step of forming a barrier metal film on the entire structure by using a collimated physical vapor deposition method. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 금속막이The metal film Cu, Au, Ag, Co, Cr, Ni, Pt 중 어느 하나로 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method comprising any one of Cu, Au, Ag, Co, Cr, Ni, and Pt. 제 2 항에 있어서,The method of claim 2, 상기 장벽 금속막이The barrier metal film TiN, CoN, Cr, CrN, W, WN, Cr 중 어느 하나로 이루어진 반도체 장치의 금속배선 형성방법.A method for forming metal wiring in a semiconductor device comprising any one of TiN, CoN, Cr, CrN, W, WN, and Cr. 제 3 항에 있어서,The method of claim 3, wherein 상기 내산화막이The oxidation resistant film TiN, TaN, W, SiON, CrN, WN, Mo, MoN 중 어느 하나로 이루어진 반도체 장치의 금속배선 형성방법.A method for forming metal wiring in a semiconductor device comprising any one of TiN, TaN, W, SiON, CrN, WN, Mo, and MoN. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 단계가The second step 상기 제2 층간 절연막 및 제1 층간 절연막을 건식 식각하는 제7 단계와,A seventh step of dry etching the second interlayer insulating film and the first interlayer insulating film; 불산계 습식 식각을 실시하여 상기 언더컷 부분을 형성하는 제8 단계를 포함하여 이루어진 반도체 장치의 금속배선 형성방법.And forming an undercut portion by performing hydrofluoric acid wet etching. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제3 단계에서In the third step 상기 금속막의 높이가 상기 제1 층간 절연막의 높이 보다 낮은 반도체 장치의 금속배선 형성방법.And forming a metal wiring in the semiconductor device, wherein the height of the metal film is lower than that of the first interlayer insulating film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 에치백이The etch back 화학·기계적 연마 방식을 사용하여 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method using chemical and mechanical polishing methods. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 에치백이The etch back 전면성 식각 방식을 사용하여 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method using a full-side etching method. 제 6 항에 있어서,The method of claim 6, 상기 제1 및 제2 층간 절연막이 각각The first and second interlayer insulating films 보로포스포 실리킷 글래스막 및 화학기상증착 산화막인 반도체 장치의 금속배선 형성방법.A method for forming metal wiring in a semiconductor device, which is a borophospho silicate glass film and a chemical vapor deposition oxide film.
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