KR100259088B1 - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to obtain a high current gain by forming a logic CMOS, a high resisting pressure CMOS, and a bipolar transistor on the same substrate. CONSTITUTION: The first and the second conductive well regions are formed on the first conductive type substrate. A MOS transistor region(A,B), a high resisting pressure MOS transistor(C,D), and a bipolar transistor region(E,F) are defined. The first and the second insulating layers are formed on the semiconductor substrate. The first and the second layers are selectively removed. A field ion injection region(28) and a low density source/drain region(26,27) are formed on the MOS transistor region and a high resisting pressure MOS transistor. The first and the second conductive well regions and a base region are formed on the bipolar transistor region. A field oxide layer is formed on the MOS transistor region and the bipolar transistor region. A source/drain region is formed on the MOS transistor region and an emitter region(35) is formed on the bipolar transistor region.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a logic CMOS device, a high breakdown voltage CMOS device, and a bipolar device can be formed on a same substrate without additional process.

Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views of a manufacturing process of a conventional semiconductor device.

First, as shown in FIG. 1A, n-type well regions 2 and p-type well regions 3 are alternately formed on the p-type semiconductor substrate 1. In this case, the n-type well region 2 and the p-type well region 3 may include a PMOS region A, an NMOS region B, a high breakdown voltage PMOS region C, and a high breakdown voltage NMOS region D. Define.

As shown in FIG. 1B, an oxide film 4 and a nitride film 5 are sequentially formed on the entire surface of the semiconductor substrate 1.

As shown in FIG. 1C, the nitride film 5 and the oxide film 4 are selectively patterned (photolithography process + etching process) to form a semiconductor substrate on the n-type well region 2 and the p-type well region 3. Expose (1). At this time, the oxide film 4 and the nitride film 5 above the source / drain regions of the high breakdown voltage PMOS region C and the high breakdown voltage EnMOS region D are removed to remove the high breakdown PMOS region C and the high breakdown voltage N. The n-type well region 2 of the MOS region D and the semiconductor substrate 1 of the p-type well region 3 are exposed. The n-type well region 2 and the p-type well region 3 interface are isolation regions for forming an isolation film for isolation between devices.

As shown in FIG. 1D, field ions are implanted into the exposed semiconductor substrate 1 using the nitride film 5 and the oxide film 4 as masks. In this case, low concentration n-type (n-) impurity ions are implanted into the high withstand voltage enmos region (D), and low concentration p-type (p-) impurity ions are implanted into the high withstand voltage PMOS region (C). The low concentration n-type impurity region 6 to be used as a source / drain of and the low concentration p-type impurity region 7 to be used as a source / drain of a high breakdown voltage PMOS is formed. At this time, a field ion implantation region 8 is formed at the interface between the n-type well region 2 and the p-type well region 3. Next, a field oxide film 9 is formed above the field ion implantation region 8 using a conventional LOCOS (LOCal Oxidation of Silicon) process, and then the nitride film 5 and the oxide film 4 are removed. . At this time, the field oxide film 9 is also formed above the low concentration n-type impurity region 6 and above the low concentration p-type impurity region 7.

As shown in FIG. 1E, the oxide film 10 and the polysilicon layer are sequentially formed on the entire surface of the semiconductor substrate 1 including the field oxide film 9, and then the PMOS transistor region A and the NMOS transistor region ( The gate electrode 11 is formed by selectively patterning (photolithography process + etching process) so as to remain only in a predetermined region of the active region of B), the high breakdown voltage PMOS region C and the high breakdown voltage enmos region D. FIG.

As shown in FIG. 1F, the NMOS transistor region B and the high breakdown voltage enmos region D are selectively masked, and a high concentration p is formed in the PMOS transistor region A and the high breakdown voltage PMOS region C. As shown in FIG. The implanted impurity ions are implanted to form high concentration p-type (p +) impurity regions 12a and 12b. At this time, the high concentration p-type (p +) impurity region 12a formed in the PMOS transistor region A is a source / drain region of the PMOS transistor, and the p-type (p +) formed in the high breakdown voltage PMOS region C. The impurity region 12b is formed for stable operation of the high breakdown voltage PMOS transistor in a current path of the high breakdown voltage PMOS transistor. Subsequently, the PMOS transistor region A and the high breakdown voltage PMOS region C are selectively masked, and high concentration n-type impurity ions are implanted into the NMOS transistor region B and the high breakdown voltage enmos region D. The high concentration n-type (n +) impurity regions 13a and 13b are formed. At this time, the high concentration n-type (n +) impurity region 13a formed in the NMOS transistor region B is a source / drain region of the NMOS transistor, and the n-type (n +) formed in the high breakdown voltage enMOS region D. The impurity region 13b is formed for stable operation of the high withstand voltage NMOS transistor in a current path of the high withstand voltage NMOS transistor.

Such a conventional semiconductor device drives a liquid crystal display (LCD) panel by forming a logic CMOS region and an off-set high voltage resistance CMOS on the same substrate. Mainly used for IC circuit implementation.

This logic CMOS part is the same as the standard CMOS device structure. The off-set LOCOS CMOS is a source / drain of a high breakdown voltage MOS transistor by injecting a low concentration of p-type or n-type impurities into the lower ends of the gate electrode. Is to use. The off-set LOCOS type MOS transistor has higher breakdown voltage characteristics than general CMOS logic transistors due to the low concentration of impurity junctions below the field oxide layer. In particular, the junction breakdown and the channel breakdown characteristics of the transistors are common. Since it is much higher than MOS device, it is mainly used for semiconductor devices requiring high breakdown voltage.

In the conventional method of manufacturing a semiconductor device, it is suitable to be used as an output driving device requiring high breakdown voltage by implementing a general logic CMOS and off-set LOCOS CMOS on a semiconductor substrate, but it is possible to obtain a high current gain due to the characteristics of the MOS device. There was no problem.

The present invention has been made to solve the problems of the conventional method of manufacturing a semiconductor device as described above, which is suitable for obtaining a high current gain by implementing a bipolar transistor together with a logic CMOS and a high breakdown voltage CMOS device on the same substrate without additional processing. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

1A to 1F are cross-sectional views of a manufacturing process of a conventional semiconductor device.

2 (a) to 2 (f) are cross-sectional views of the manufacturing process of the semiconductor device of the present invention.

3A is a layout diagram of a bipolar transistor region of the semiconductor device of the present invention, and FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 3A.

Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 n-type well region

23 p-type well region 24 oxide film

25 nitride layer 26 low concentration n-type impurity region

27: low concentration p-type impurity region 28: field ion implantation region

29: n-type base area 30: p-type base area

31: field oxide film 32: gate oxide film

33 gate electrode 34 high concentration p-type impurity region

35: p-type emitter region 36: high concentration n-type impurity region

37: n-type emitter area

A method of manufacturing a semiconductor device according to the present invention includes preparing a first conductive semiconductor substrate, alternately forming first and second conductive well regions on the semiconductor substrate, a MOS transistor region, and a high breakdown voltage MOS transistor region. And defining a bipolar transistor region, forming first and second insulating films on the semiconductor substrate, and selectively forming the first and second insulating films to expose an interface between the first and second conductive well regions. Injecting field ions into the exposed semiconductor substrate to form a field ion implantation region and a low concentration source / drain region in the MOS transistor region and the high breakdown voltage MOS transistor region, and in the bipolar transistor region, Forming a base region opposite to the second conductivity type well region, using the second and first insulating layers as a mask Forming a field oxide film on the exposed semiconductor substrate, removing the first and second insulating films, and forming a field oxide film on the MOS transistor region and the bipolar transistor region. Selectively implanting impurity ions to form a source / drain region in the MOS transistor region and an emitter region in the bipolar transistor region.

Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2 (a) to 2 (f) are cross-sectional views of the manufacturing process of the semiconductor device of the present invention.

First, as shown in FIG. 2A, n-type well regions 22 and p-type well regions 23 are alternately formed in the first conductive semiconductor substrate 21. In this case, the n-type well region 22 and the p-type well region 23 may be formed into a PMOS region A, an NMOS region B, a high breakdown voltage PMOS region C, and a high breakdown voltage NMOS region D. , NPN bipolar transistor region E and PNP bipolar transistor region F.

As shown in FIG. 2B, an oxide film 24 and a nitride film 25 are sequentially formed on the entire surface of the semiconductor substrate 21.

As shown in FIG. 2C, the n-type well region 22 and the p-type well region 23 are selectively patterned (photolithography process + etching process) by selectively patterning the nitride film 25 and the oxide film 24. The semiconductor substrate 21 at the interface is exposed. At this time, the oxide film 24 and the nitride film 25 above the source / drain regions of the high breakdown voltage PMOS region C and the high breakdown voltage enmos region D are removed to remove the high breakdown voltage PMOS region C and the high breakdown voltage N. The n-type well region 22 of the MOS region D and the semiconductor substrate 21 of the p-type well region 23 are exposed. The NPN bipolar transistor region E and the PNP bipolar transistor region F are exposed to the semiconductor substrate 21 to be used as the base region and the emitter region. In this case, the n-type well region 22 and the p-type well region 23 interface are isolation regions for isolation between devices.

As shown in FIG. 2D, field ions are implanted into the exposed semiconductor substrate 21 using the nitride film 25 and the oxide film 24 as a mask. In this case, low concentration n-type (n-) impurity ions are implanted into the high withstand voltage enmos region (D), and low concentration p-type (p-) impurity ions are alternately implanted into the high withstand voltage PMOS region (C). The low concentration n-type impurity region 26 to be used as a source / drain of NMOS and the low concentration p-type impurity region 27 to be used as a source / drain of a high breakdown voltage PMOS are formed. At this time, an n-type base region 29 is formed in the PNP bipolar transistor region F by the low concentration n-type impurity ion implantation, and a p-type base in the NPN bipolar transistor region E by the low concentration p-type impurity ion implantation. Region 30 is formed. At this time, a field ion implantation region 28 is formed at the interface between the n-type well region 22 and the p-type well region 23. Then, the field oxide film 31 is formed above the field ion implantation region 28 using a conventional process, and then the nitride film 25 and the oxide film 24 are removed. At this time, the field oxide film 31 is also formed above the low concentration n-type impurity region 26 and above the low concentration p-type impurity region 27.

As shown in FIG. 2E, the oxide film 32 and the polysilicon layer are sequentially formed on the entire surface of the semiconductor substrate 21 including the field oxide film 31, and then the PMOS region A and the NMOS Selectively patterning so as to remain only in predetermined regions of the active region of the region B, the high breakdown voltage PMOS region C, the high breakdown voltage EnMOS region D, the NPN transistor region E and the PNP transistor region F Process + etching) to form the gate electrode 33.

As shown in FIG. 2F, the NMOS region B and the high breakdown voltage enmos region D are selectively masked, and then the PMOS region A and the high breakdown voltage PMOS region C are masked. High concentration p-type impurity ions are implanted to form high concentration p-type (p +) impurity regions 34a and 34b. At this time, a high concentration p-type impurity region 34c is formed in the NPN bipolar transistor region E, and a high concentration p-type impurity region 34d and a p-type emitter 35 region are also formed in the PNP bipolar transistor region F. do. At this time, the high concentration p-type (p +) impurity region 34a formed in the PMOS region A is a source / drain region of the PMOS transistor, and the p-type (p +) impurity formed in the high breakdown voltage PMOS region C. The p-type impurity regions 34c and 34d formed in the region 34b, the NPN bipolar transistor region E, and the PNP bipolar transistor region F are the current paths of the high breakdown voltage PMOS transistor and the NPN, PNP bipolar transistor. ) For stable operation of the high breakdown voltage PMOS transistor and NPN, PNP bipolar transistor. Subsequently, the PMOS region A and the high breakdown voltage PMOS region C are selectively masked, and then, a high concentration n-type impurity ion is implanted into the NMOS region B and the high withstand voltage enmos region D, thereby providing a high concentration n. Formation (n +) impurity regions 36a and 36b are formed. At this time, a high concentration n-type impurity region 36c and an n-type emitter region 37 are formed in the NPN bipolar transistor region E, and a high concentration n-type impurity region 36d is formed in the PNP bipolar transistor region F. do. At this time, the high concentration n-type (n +) impurity region 36a formed in the NMOS region B is a source / drain region of the NMOS transistor, and the n-type (n +) impurity formed in the high breakdown voltage NMOS region D. The n-type impurity regions 36c and 36d formed in the region 36b, the NPN bipolar transistor region E, and the PNP bipolar transistor region F are the current paths of the high breakdown voltage MOS transistor and the NPN, PNP bipolar transistor. In order to ensure stable operation of high breakdown voltage NMOS transistors, NPN and PNP bipolar transistors. In this case, the n-type well region 22 and the p-type well region 23 are collector regions of the NPN transistor and the PNP transistor, respectively.

3A is a layout diagram of a bipolar transistor region of the semiconductor device of the present invention, and FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 3A.

That is, referring to FIGS. 3A to 3B, first, n-type and p-type low concentrations injected into the n-type well region 22 and the p-type well region 23 used as collector regions of NPN and PNP transistors during the field ion implantation process, respectively As the impurity ions, a base region 29 of a PNP bipolar transistor and a base region 30 of an NPN bipolar transistor are formed, and high concentration impurity regions 34 and 36 of a logic CMOS region are formed in each of the base regions 29 and 30. ), The emitter region 35 of the PNP bipolar transistor and the emitter region 37 of the NPN bipolar transistor are formed.

In the method of manufacturing a semiconductor device according to the present invention, bipolar transistors can be formed in the existing process without any special process addition, and thus, general logic CMOS, off-set locos CMOS, and bipolar transistors are formed on a semiconductor substrate to achieve high breakdown voltage and Since a high current gain can be obtained, a semiconductor device requiring a high current gain can be provided.

Claims (1)

Preparing a first conductive semiconductor substrate; Alternately forming first and second conductivity type well regions on the semiconductor substrate; Defining a MOS transistor region, a high breakdown voltage MOS transistor region, and a bipolar transistor region; Forming first and second insulating films on the semiconductor substrate; Selectively removing the first and second insulating layers to expose an interface of the first and second conductivity type well regions; Field ions are implanted into the exposed semiconductor substrate to form field ion implantation regions and low concentration source / drain regions in the MOS transistor region and the high breakdown voltage MOS transistor region, and the first and second conductivity types in the bipolar transistor region. Forming a base region of opposite conductivity to the well region; Forming a field oxide film on the exposed semiconductor substrate using the second and first insulating films as a mask; Removing the first and second insulating films; Selectively implanting impurity ions opposite to the first and second conductivity type well regions into the MOS transistor region and the bipolar transistor region to form a source / drain region in the MOS transistor region and an emi in the bipolar transistor region. Forming a region of the trench.

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