KR100186518B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR100186518B1 KR100186518B1 KR1019960015073A KR19960015073A KR100186518B1 KR 100186518 B1 KR100186518 B1 KR 100186518B1 KR 1019960015073 A KR1019960015073 A KR 1019960015073A KR 19960015073 A KR19960015073 A KR 19960015073A KR 100186518 B1 KR100186518 B1 KR 100186518B1
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- insulating film
- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 25
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 17
- 239000010937 tungsten Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 239000007943 implant Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61H—PHYSICAL THERAPY APPARATUS, e.g. DEVICES FOR LOCATING OR STIMULATING REFLEX POINTS IN THE BODY; ARTIFICIAL RESPIRATION; MASSAGE; BATHING DEVICES FOR SPECIAL THERAPEUTIC OR HYGIENIC PURPOSES OR SPECIFIC PARTS OF THE BODY
- A61H39/00—Devices for locating or stimulating specific reflex points of the body for physical therapy, e.g. acupuncture
- A61H39/04—Devices for pressing such points, e.g. Shiatsu or Acupressure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N5/00—Radiation therapy
- A61N5/06—Radiation therapy using light
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61H—PHYSICAL THERAPY APPARATUS, e.g. DEVICES FOR LOCATING OR STIMULATING REFLEX POINTS IN THE BODY; ARTIFICIAL RESPIRATION; MASSAGE; BATHING DEVICES FOR SPECIAL THERAPEUTIC OR HYGIENIC PURPOSES OR SPECIFIC PARTS OF THE BODY
- A61H2201/00—Characteristics of apparatus not provided for in the preceding codes
- A61H2201/01—Constructive details
- A61H2201/0173—Means for preventing injuries
- A61H2201/018—By limiting the applied torque or force
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61H—PHYSICAL THERAPY APPARATUS, e.g. DEVICES FOR LOCATING OR STIMULATING REFLEX POINTS IN THE BODY; ARTIFICIAL RESPIRATION; MASSAGE; BATHING DEVICES FOR SPECIAL THERAPEUTIC OR HYGIENIC PURPOSES OR SPECIFIC PARTS OF THE BODY
- A61H2201/00—Characteristics of apparatus not provided for in the preceding codes
- A61H2201/10—Characteristics of apparatus not provided for in the preceding codes with further special therapeutic means, e.g. electrotherapy, magneto therapy or radiation therapy, chromo therapy, infrared or ultraviolet therapy
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N2/00—Magnetotherapy
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
본 발명은 반도체 소자에 관한 것으로, 특히 소오스/드레인 및 게이트에 선택적으로 텅스텐 화학 기상 증착을 하여 소오스/드레인의 콘택 저항 및 시트(sheet)저항을 증대시키고 LATID 이온주입을 자기 정렬 (Self Align)방법으로 하여 서브마이크론 소자의 트랜지스터 특성을 향상시키도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to semiconductor devices, and in particular, to tungsten chemical vapor deposition on source / drain and gate to increase contact resistance and sheet resistance of the source / drain and to self-align LATID implants. The present invention relates to a method for manufacturing a semiconductor device in which the transistor characteristics of the submicron device are improved.
이를 위한 본 발명 일실시예의 반도체 소자는 반도체 기판 상의 활성 영역의 소정 부분에 제 1 절연막과 게이트층과 제 2 절연막을 차례로 증착하여 게이트 전극을 형성하는 단계, 상기에 형성된 게이트 전극의 양측 기판 내에 제 1 불순물 영역을 형성하는 단계, 상기 게이트 전극의 양 측벽에 측벽 절연막을 형성하는 단계, 상기 제 2 절연막 제거 후 활성 영역 상의 상기 제 1 불순물 영역과 게이트 전극 상에 선택적으로 텅스텐을 증착하는 단계, 게이트 측벽 절연막을 제거 후 제 2 불순물 주입하는 단계, 기판 전면에 층간 절연막 및 평탄화막을 증착하는 단계, 상기 제 1 불순물 영역 위에 접촉된 텅스텐 위에 컨택홀을 형성하여 금속 배선을 패터닝하는 단계를 포함하는 것을 특징으로 한다.According to an embodiment of the present invention, a semiconductor device is formed by sequentially depositing a first insulating film, a gate layer, and a second insulating film on a predetermined portion of an active region on a semiconductor substrate, and forming a gate electrode on both sides of the formed gate electrode. Forming an impurity region, forming a sidewall insulating film on both sidewalls of the gate electrode, and selectively depositing tungsten on the first impurity region on the active region and the gate electrode after removing the second insulating film Removing the sidewall insulating film, and then implanting a second impurity, depositing an interlayer insulating film and a planarization film on the entire surface of the substrate, and forming a contact hole on the tungsten in contact with the first impurity region to pattern the metal wiring. It is done.
Description
제 1 도는 종래 반도체 소자의 공정 단면도1 is a process cross-sectional view of a conventional semiconductor device
제 2 도는 본 발명 일실시예의 반도체 소자 공정 단면도2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30 : 반도체 기판 31 : 필드 산화막30 semiconductor substrate 31 field oxide film
32 : 게이트 산화막 33 : 폴리 게이트32: gate oxide film 33: poly gate
34 : 질화막 35 : 스페이스 산화막34 nitride film 35 space oxide film
35a : 측벽 산화막 36a,36b : 제1 소오스, 드레인 불순물 영역35a: sidewall oxide film 36a, 36b: first source, drain impurity region
37 : 텅스텐 38a,38b : 제 2소오스, 드레인 불순물 영역37: tungsten 38a, 38b: second source, drain impurity region
39 : 층간 절연막 40 : 평탄 보호막39: interlayer insulation film 40: planar protective film
41 : 금속층41: metal layer
[발명의 상세한 설명]Detailed description of the invention
본 발명은 반도체 소자에 관한 것으로, 특히 소오스/드레인 및 게이트에 선택적으로 텅스텐 화학 기상 증착(Selective W -CVD)을 하여 소오스/드레인의 콘택 저항 및 시트(Sheet) 저항을 감소시키고 LATID 이온주입을 자기 정렬(Self Align) 방법으로 하여 서브마이크론 소자의 트랜지스터특성을 향상시키도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, in particular, by selectively tungsten chemical vapor deposition (Selective W-CVD) on the sources / drains and gates to reduce the contact resistance and sheet resistance of the source / drain and to induce LATID ion implantation. A method of manufacturing a semiconductor device in which the transistor characteristics of a submicron device are improved by a self alignment method.
이하, 첨부도면을 참조하여 종래의 반도체 소자를 설명하면 다음과 같다.Hereinafter, a conventional semiconductor device will be described with reference to the accompanying drawings.
제 1 도는 종래 반도체 소자의 공정 단면도이다.1 is a cross-sectional view of a conventional semiconductor device.
먼저 제 1 도(a)와 같이, 반도체 기판(1) 상에 필드 영역과 활성 영역을 정의하여 필드 영역에 필드 산화막(2)을 형성한 후, 상기 전면에 게이트 산화막(3)과 폴리게이트(4) 그리고, 고온 저압 절연막(5)을 증착한다.First, as shown in FIG. 1A, a field oxide layer 2 is formed on a field region by defining a field region and an active region on the semiconductor substrate 1, and then the gate oxide layer 3 and the poly gate ( 4) Then, the high temperature low pressure insulating film 5 is deposited.
제 1 도 (b)와 같이, 상기 전면에 감광막 증착후(도시하지 않았음) 사진 식각으로 활성 영역의 소정 영역만 남도록 패터닝한다. 이후에 식각되고 남은 감광막을 마스크로 폴리 게이트와(4) 게이트 산화막(3)을 차례로 식각하여 게이트 전극을 형성한다.As shown in FIG. 1 (b), after the photoresist film is deposited on the entire surface (not shown), only a predetermined region of the active region remains by photolithography. After that, the poly gate and the gate oxide layer 3 are sequentially etched using the remaining photoresist as a mask to form a gate electrode.
그리고 게이트 전극을 마스크로반도체 기판(1)의 활성 영역 상에 저농도 소오스/드레인 불순물 영역(6a/6b)을 이온 주입한다.The low concentration source / drain impurity regions 6a / 6b are ion implanted onto the active region of the semiconductor substrate 1 using the gate electrode as a mask.
제 1 도(c)와 같이, 상기 전면에 스페이스 산화막(7)을 증착한다.As shown in FIG. 1C, a space oxide film 7 is deposited on the entire surface.
제 1 도(d)와 같이, 스페이스 산화막(7)을 게이트 측벽만 남도록 이방성 식각한 후 게이트 측벽 산화막(7a)과 게이트를 마스크로 하여 고농도 소오스/드레인 불순물(8a/8b)을 주입한다.As shown in FIG. 1D, the space oxide film 7 is anisotropically etched so that only the gate sidewalls remain, and then a high concentration source / drain impurity 8a / 8b is implanted using the gate sidewall oxide film 7a and the gate as a mask.
제 1 도 (e)와 같이, 배선 공정 및 표면 평탄화를 위해서 층간 절연막(ILD : Inter Layer Dielectric)(9)및 평탄 보호막(BPSG)(10)을 증착한다.As shown in FIG. 1E, an interlayer insulating film (ILD) 9 and a planar protective film (BPSG) 10 are deposited for the wiring process and the surface planarization.
제 1 도 (f)와 같이, 사진 식각 방법으로 반도체 기판(1)의 소오스/드레인 불순물 영역(8a,8b)이 노출되도록 콘택홀을 형성한 후, 전면에 금속층(11)을 증착한 다음 콘택 부분만 남도록 패터닝한다.As shown in FIG. 1 (f), after forming contact holes to expose the source / drain impurity regions 8a and 8b of the semiconductor substrate 1 by a photolithography method, a metal layer 11 is deposited on the entire surface, and then contact is formed. Pattern so that only parts remain.
그러나 이와 같은 종래의 반도체 소자의 제조 방법에는 다음과 같은 문제점이 있었다.However, such a conventional method of manufacturing a semiconductor device has the following problems.
첫째, 채널 길이가 감소할수록 채널과 드레인 사이에 접합 전계가 증가하여 게이트 산화막으로 전자가 유기되거나 기판의 누설 전류가 생기는 등의 핫 캐리어(Hot Carrier)문제가 생긴다.First, as the channel length decreases, a hot field problem occurs such that the junction electric field increases between the channel and the drain, so that electrons are induced into the gate oxide film or a leakage current of the substrate is generated.
그러나 기존의 LDD만으로는 이러한 문제를 해결하기가 어렵다However, existing LDD alone is difficult to solve this problem.
둘째, 얕게 확산된 소오스와 드레인의 접합에 컨택홀을 형성할 때 과도 식각 (Over Etch)에 의한 접합 스파이크(Junction Spike)에 의해 접합 누설 전류가 발생될 수 있으며, 시트(Sheet) 저항 자체도 보증할 수가 없게 된다.Second, when forming a contact hole in a junction of a shallowly diffused source and drain, a junction leakage current may be generated by a junction spike caused by over etching, and also guarantees sheet resistance itself. I can't do it.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써, 소오스/드레인 및 게이트에 선택적 텅스텐 화학 기상 증착을 하여 소오스/드레인의 콘택저항 및 시트(Sheet)저항을 증대시키고 LATID 이온주입을 자기정렬(Self Align)방법으로 하여 고집적 트랜지스터의 특성을 향상시키는데 그 목적이 있다.In order to solve this problem, the present invention provides selective tungsten chemical vapor deposition on source / drain and gate to increase the contact resistance and sheet resistance of the source / drain and to self-align LATID ion implantation. The purpose of the self-alignment method is to improve the characteristics of the highly integrated transistor.
상기와 같은 목적을 달성하기 위한 본 발명 일실시예의 반도체 소자는 반도체 기판상의 활성 영역의 소정 부분에 제 1 절연막과 게이트층과 제 2 절연막을 차례로 증착하여 게이트 전극을 형성하는 단계, 상기에 형성된 게이트 전극의 양측 기판 내에 제 1 불순물 영역을 형성하는 단계, 상기 게이트 전극의 양 측벽에 측벽 절연막을 형성하는 단계, 상기 제 2 절연막 제거 후 활성 영역 상의 상기 제 1 불순물 영역과 게이트 전극 상에 선택적으로 텅스텐을 증착하는 단계, 게이트 측벽 절연막을 제거후 제 2 불순물 주입하는 단계, 기판 전면에 층간 절연막 및 평탄화막을 증착하는 단계, 상기 제 1 불순물 영역 위에 접촉된 텅스텐 위에 컨택홀을 형성하여 금속 배선을 패터닝하는 단계를 포함하는 것을 특징으로 한다 .In the semiconductor device of an embodiment of the present invention for achieving the above object, forming a gate electrode by sequentially depositing a first insulating film, a gate layer, and a second insulating film on a predetermined portion of an active region on a semiconductor substrate, the gate formed above Forming a first impurity region in both substrates of the electrode, forming a sidewall insulating film on both sidewalls of the gate electrode, and selectively removing tungsten on the first impurity region on the active region and the gate electrode after removing the second insulating film Depositing a second impurity after removing the gate sidewall insulating film, depositing an interlayer insulating film and a planarization film on the entire surface of the substrate, and forming a contact hole on the tungsten in contact with the first impurity region to pattern the metal wiring. Characterized in that it comprises a step.
상기와 같은 본 발명 일실시예의 반도체 소자의 제조 방법을 첨부 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a semiconductor device of an embodiment of the present invention as described above in detail as follows.
제 2 도는 본 발명 일실시예의 반도체 소자의 공정 단면도이다.2 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.
제 2 도(a)와 같이, 반도체 기판 (30)상체 필드영역과 활성영역을 정의하여 필드 영역에 필드 산화막(31)을 형성한 후, 전면에 게이트 산화막(32)과 폴리 게이트(33) 및 질화막(34)을 차례대로 증착시킨다.As shown in FIG. 2A, after forming the field oxide film 31 in the field region by defining the field region and the active region on the semiconductor substrate 30, the gate oxide film 32, the poly gate 33, and The nitride film 34 is deposited in order.
다음에 제 2 도(b)와 같이, 전면에 감광막을 증착하여(도시하지 않았음) 사진 식각 및 열공정으로 게이트를 형성시킬 위부분만 남도록 패터닝한다. 그리고, 이 감광막을 마스크로 하여 질화막(34)과 폴리 게이트(33)와 게이트 산화막을 식각하여 게이트 전극을 형성한 후 감광막을 제거한다.Next, as shown in FIG. 2 (b), a photoresist film is deposited on the entire surface (not shown) and patterned so that only the upper portion where the gate is formed is formed by photolithography and thermal processes. Using the photoresist film as a mask, the nitride film 34, the poly gate 33, and the gate oxide film are etched to form a gate electrode, and then the photoresist film is removed.
다음에 제 2 도(c)와 같이 전면에 스페이스 산화막(35)을 증착시킨다.Next, a space oxide film 35 is deposited on the entire surface as shown in FIG.
그후, 제 2 도(d)와 같이 , 질화막(34)과 폴리게이트(33) 양 측면에 이방성 식각으로 측벽 산화막(35a)을 형성한 후 게이트 전극과 측벽 산화막을 마스크로 하여 양 활성 영역 상에 제 1 소오스/드레인 불순물 영역(36a/36b)을 형성한다.Thereafter, as shown in FIG. 2D, the sidewall oxide film 35a is formed on both sides of the nitride film 34 and the polygate 33 by anisotropic etching, and then the gate electrode and the sidewall oxide film are used as masks on both active regions. First source / drain impurity regions 36a / 36b are formed.
다음에 제 2 도(e)와 같이, 전면에 감광막 도포후 (도시하지 않았음) 게이트 전극 위 부분의 상기 감광막을 제거한 후, 남은 감광막을 마스크로하여 노출된 질화막(34)을 식각한 후 감광막을 제거한다.Next, as shown in FIG. 2 (e), after the photoresist film is applied to the entire surface (not shown), the photoresist film on the upper portion of the gate electrode is removed, and the exposed nitride film 34 is etched using the remaining photoresist film as a mask, followed by etching. Remove it.
제 2 도(f)와 같이, 상기 폴리 게이트(33)와 활성 영역상의 제 1 소오스/드레인 불순물 영역(36a/36b) 위에 화학 기상 증착에 의해 선택적으로 텅스텐(37)(Selective W -CVD)을 형성한다.As shown in FIG. 2 (f), tungsten 37 (Selective W-CVD) is selectively deposited on the poly gate 33 and the first source / drain impurity regions 36a / 36b on the active region by chemical vapor deposition. Form.
여기서 텅스텐 대신 티타늄 실리사이드(TiSi₂)를 사용하여도 된다.Titanium silicide (TiSi2) may be used instead of tungsten.
다음에, 제 2 도 (g)와 같이, 게이트 전극 양측의 측벽 산화막을 제거한다.Next, as shown in FIG. 2 (g), sidewall oxide films on both sides of the gate electrode are removed.
제 2 도(h)와 같이, 상기 측벽 산화막(35a)이 제거된 게이트 전극 양측의 드러난 기판 상에 기판과 다른형의 제 2 소오스/드레인 불순물 영역(38a/38b)을 각도(Tilt)를 주어 주입한다.As shown in FIG. 2 (h), the second source / drain impurity regions 38a / 38b different from the substrate are angled on the exposed substrates on both sides of the gate electrode from which the sidewall oxide layer 35a is removed. Inject.
이것은 핫 캐리어(Hot carrier) 효과를 줄여주는 역할을 한다.This serves to reduce the hot carrier effect.
다음에 제 2 도(i)와 같이, 전면에 고온 및 저압 층간 절연막(HLD)(39)을 형성한 후 평탄 보호막(BPSG)(40)을 증착한다.Next, as shown in FIG. 2 (i), a high temperature and low pressure interlayer insulating film (HLD) 39 is formed on the entire surface, and then a flat protective film (BPSG) 40 is deposited.
제 2 도(j)와 같이, 감광막을 증착후 (도시하지 않았음) 사진 식각으로 상기 제 1 소오스/드레인 불순물상(36a/36b)의 텅스텐(37)이 드러나도록 패터닝한 후 감광막을 마스크로 하여 평탄 보호막(40)과 층간 절연막을 식각하여 콘택홀을 형성한다.As shown in FIG. 2 (j), after the photoresist film is deposited (not shown), the photoresist is patterned to reveal the tungsten 37 of the first source / drain impurity phases 36a / 36b and then the photoresist film is used as a mask. The planar protective layer 40 and the interlayer insulating layer are etched to form contact holes.
이후 금속 배선을 위해 알루미늄을 증착한 후 패턴하여 제 1 소오스/드레인 불순물(36a/36b)상의 텅스텐에 금속층이 접촉되도록 알루미늄 배선을 형성한다.Thereafter, aluminum is deposited for metal wiring and then patterned to form aluminum wiring so that the metal layer contacts the tungsten on the first source / drain impurities 36a / 36b.
이상에서 설명한 바와 같이 본 발명 일실시예의 반도체 소자 제조 방법은 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of an embodiment of the present invention has the following effects.
첫째, 소오스와 드레인이 텅스텐으로 구성되었으므로 소오스/드레인의 시트(Sheet)저항이 감소하고 알루미늄과 소오스/드레인의 콘택저항도 감소하게 된다.First, since the source and drain are made of tungsten, the sheet resistance of the source / drain is reduced and the contact resistance of aluminum and the source / drain is also reduced.
둘째, 소오스와 드레인에 기판과 다른형의 불순물 농도를 조절하여 LATID 주입을 해 주므로 핫 캐리어(Hot Carrier) 특성이 개선된다.Second, hot carrier characteristics are improved because LATID is implanted by adjusting impurities and other types of impurities in the source and drain.
이때 마스크는 필요에 따라 사용해 줄수도 있다.The mask can be used as needed.
셋째, 소오스와 드레인의 구조가 실리콘이 노출되지 않고 텅스텐으로 형성되었기 때문에 얕은 접합에서 콘택 과도식각(Over Etch)으로 생길 수 있는 접합누전의 문제가 해결된다.Third, since the source and drain structures are formed of tungsten without exposing silicon, the problem of junction leakage that may occur due to contact overetch in shallow junctions is solved.
Claims (4)
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