JPWO2009034601A1 - Plasma display panel - Google Patents

Abstract

The plasma display panel has a first substrate and a second substrate facing each other. The first substrate has first and second bus electrodes, first and second display electrodes connected to the first and second bus electrodes, a dielectric layer, and an address electrode, respectively. For example, the first display electrode is disposed in each cell, protrudes from the first bus electrode toward the second bus electrode, and decreases in width toward the tip. The first display electrode has a first side along a partition wall that is located away from the address electrode, and a first oblique side that obliquely opposes the first side. The second display electrode is disposed in each cell, protrudes from the second bus electrode toward the first bus electrode, and decreases in width toward the tip. The second display electrode has a second side along the address electrode and a second hypotenuse opposite to the first hypotenuse. As a result, erroneous discharge can be prevented.

Description

  The present invention relates to a plasma display panel used for a display device.

  A plasma display panel (PDP) consists of two glass substrates (a front glass substrate and a back glass substrate) bonded together, and generates discharge light in a space (discharge space) formed between the glass substrates. To display an image. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

  In general, the back glass substrate has a partition wall coated with the above-described phosphor, and the surface of the front glass substrate is covered with a protective layer that protects the dielectric layer from electric discharge. Note that the protective layer is formed of a material having a high secondary electron emission characteristic due to the collision of cations in order to easily generate discharge. In the PDP, in order to display an image with multiple gradations, a field for displaying one screen includes, for example, a plurality of subfields having a reset period, an address period, and a sustain period.

  A three-electrode PDP having an X electrode, a Y electrode, and an address electrode displays an image by generating a sustain discharge between the X electrode and the Y electrode in the sustain period. A cell that generates a sustain discharge (cell to be lit) is selected by, for example, selectively generating an address discharge between the Y electrode and the address electrode in the address period.

  In recent years, a PDP in which three electrodes, that is, an X electrode, a Y electrode, and an address electrode are arranged on a front glass substrate has been proposed (for example, see Patent Document 1). In this type of PDP, a partition is provided on the back glass substrate along the address electrode. For example, the X electrode is constituted by an X bus electrode and an X transparent electrode provided in each cell, and the Y electrode is constituted by a Y bus electrode and a Y transparent electrode provided in each cell. Here, the cell is formed in a region surrounded by the X bus electrode, the Y bus electrode, and the partition.

In the PDP of Patent Document 1, the Y transparent electrodes of two cells adjacent to each other along the X bus electrode are adjacent to each other with the address electrode interposed therebetween. In order to prevent erroneous discharge between the Y transparent electrode and the address electrode, in the PDP of Patent Document 1, the distance between the other Y transparent electrode and the address electrode is set between the two Y transparent electrodes adjacent to each other with the address electrode interposed therebetween. The distance between the one Y transparent electrode and the address electrode is longer. For example, by disposing the address electrode in the cell corresponding to itself, the distance between the Y transparent electrode that does not generate address discharge (the Y transparent electrode of the cell adjacent to the cell corresponding to the address electrode) and the address electrode is increased. ing.
JP 2006-302866 A

  In recent years, the number of pixels per screen has increased due to high definition of the PDP, and the cell area of each PDP tends to be small. When the technique of Patent Document 1 is applied to a PDP having a small cell width in the extending direction of the X bus electrode, it becomes difficult to increase the distance between the Y transparent electrode that does not generate address discharge and the address electrode. There is a risk of erroneous discharge between the transparent electrode and the address electrode. In addition, since the cell width is reduced, the discharge region formed between the X and Y transparent electrodes facing each other is reduced, and a high voltage is required to generate a sustain discharge.

  An object of the present invention is to prevent erroneous discharge in a PDP having three electrodes on a front glass substrate. In particular, in a PDP having three electrodes on a front glass substrate, erroneous discharge is prevented without increasing the voltage necessary for generating sustain discharge.

  The plasma display panel has a first substrate and a second substrate facing each other. The first substrate includes first and second bus electrodes extending in a first direction, first and second display electrodes connected to the first and second bus electrodes, a dielectric layer, and an address electrode, The second substrate has a partition wall extending in a second direction intersecting the first direction. For example, the address electrode extends in the second direction through each cell and is disposed adjacent to one partition wall disposed on both sides of the cell. The first display electrode is disposed in each cell, protrudes from the first bus electrode toward the second bus electrode, and decreases in width toward the tip. The first display electrode has a first side along the other partition wall and a first oblique side diagonally opposed to the first side. The second display electrode is disposed in each cell, protrudes from the second bus electrode toward the first bus electrode, and decreases in width toward the tip. The second display electrode has a second side along the address electrode and a second hypotenuse opposite to the first hypotenuse.

  In the present invention, erroneous discharge can be prevented in a PDP having three electrodes on the front glass substrate. In particular, in a PDP having three electrodes on a front glass substrate, erroneous discharge can be prevented without increasing the voltage necessary for generating sustain discharge.

It is a disassembled perspective view of the principal part of PDP in the 1st Embodiment of this invention. It is explanatory drawing of PDP shown in FIG. It is sectional drawing which follows the A-A 'line | wire of PDP shown in FIG. It is a disassembled perspective view which shows an example of the plasma display apparatus comprised using PDP shown in FIG. FIG. 5 is a block diagram illustrating an outline of a circuit unit illustrated in FIG. 4. It is a wave form diagram which shows the example of the discharge operation | movement of the subfield for displaying an image on PDP shown in FIG. It is explanatory drawing of the principal part of PDP in the 2nd Embodiment of this invention. It is explanatory drawing of the principal part of PDP in the 3rd Embodiment of this invention. It is explanatory drawing which shows the electrode structure of PDP in the modification of this invention. FIG. 10 is an explanatory diagram illustrating an example in which one corner of each transparent electrode illustrated in FIG. 9 is chamfered. FIG. 10 is an explanatory diagram illustrating another example in which one corner of each transparent electrode illustrated in FIG. 9 is chamfered. FIG. 10 is an explanatory diagram illustrating an example in which two corners of each transparent electrode illustrated in FIG. 9 are chamfered. It is explanatory drawing which shows the electrode structure of PDP in another modification of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a main part of a plasma display panel (hereinafter also referred to as PDP) in a first embodiment of the present invention. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. The PDP 10 includes a front substrate portion 12 that forms an image display surface, and a rear substrate portion 14 that faces the front substrate portion 12. A discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, a concave portion of the rear substrate portion 14).

  The front substrate portion 12 is formed in parallel along the first direction D1 on the glass substrate FS (first substrate) (lower side in the figure), and is alternately formed along the second direction D2. Xb (first bus electrode) and Y bus electrode Yb (second bus electrode) are provided. An X transparent electrode Xt (first display electrode) extending in the second direction D2 from the X bus electrode Xb to the Y bus electrode Yb is connected to the X bus electrode Xb. Further, a Y transparent electrode Yt (second display electrode) extending in the second direction D2 from the Y bus electrode Yb to the X bus electrode Xb is connected to the Y bus electrode Yb.

  Here, the X bus electrode Xb and the Y bus electrode Yb are opaque electrodes formed of a metal material or the like, and the X transparent electrode Xt and the Y transparent electrode Yt are transparent to transmit light formed of an ITO film or the like. Electrode. The X electrode XE (first electrode, sustain electrode) is composed of the X bus electrode Xb and the X transparent electrode Xt, and the Y electrode YE (second electrode, scan electrode) is the Y bus electrode Yb and the Y transparent electrode Yt. And is paired with the X electrode XE. A discharge (sustain discharge) is repeatedly generated at the electrode pair (more specifically, between the X transparent electrode Xt and the Y transparent electrode Yt) constituted by the X electrode XE and the Y electrode YE.

  Further, the transparent electrodes Xt and Yt may be disposed on the entire surface between the bus electrodes Xb and Yb to which the transparent electrodes Xt and Yt are connected and the glass substrate FS. Note that an electrode integral with the bus electrodes Xb and Yb may be formed in place of the transparent electrodes Xt and Yt, using the same material (metal material or the like) as the bus electrodes Xb and Yb.

  The electrodes Xb, Xt, Yb, Yt are covered with the dielectric layer DL1. For example, the dielectric layer DL1 is an insulating film such as a silicon dioxide film formed by a CVD method. A plurality of address electrodes AE extending in a direction (second direction D2) perpendicular to the bus electrodes Xb and Yb are provided on the dielectric layer DL1 (lower side in the drawing). Thus, the PDP of this embodiment has three electrodes (electrodes XE, YE, AE) on the front substrate portion 12.

  The address electrode AE and the dielectric layer DL1 are covered with a protective layer PL. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collisions in order to facilitate discharge. A dielectric layer that covers the address electrode AE may be formed separately from the dielectric layer DL1 between the address electrode AE and the dielectric layer DL1 and the protective layer PL. In this case, the surface of the dielectric layer covering the address electrode AE is covered with the protective layer PL.

  The back substrate portion 14 facing the front substrate portion 12 through the discharge space DS extends on the glass base RS (second substrate) in a direction (second direction D2) orthogonal to the bus electrodes Xb and Yb. , Partition walls (barrier ribs) BR formed in parallel to each other. A part of the barrier rib BR faces the address electrode AE. In other words, the address electrode AE is adjacent to the partition wall BR. A partition wall BR constitutes a side wall of the cell. Further, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall BR and the glass substrate RS between the adjacent partition walls BR by being excited by ultraviolet rays. Phosphors PHr, PHg, and PHb are respectively applied.

  One pixel of the PDP 10 includes three cells that generate red, green, and blue light. Here, one cell (one color pixel) is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR as shown in FIG. 2 described later. As described above, the PDP 10 is configured by arranging cells in a matrix to display an image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes Xb and Yb.

  The PDP 10 is configured by bonding the front substrate portion 12 and the rear substrate portion 14 so that the protective layer PL and the partition wall BR are in contact with each other, and enclosing a discharge gas such as Ne or Xe in the discharge space DS.

  FIG. 2 shows an outline of the PDP 10 shown in FIG. 2 shows the state of the electrodes Xb, Xt, Yb, Yt, AE, and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). As described above, the cell C1 is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR (region surrounded by a broken line in the drawing). That is, when viewed from the image display surface side, the discharge space DS of each cell C1 is formed between the adjacent barrier ribs BR.

  The address electrode AE extends in the second direction through each cell C1, and is disposed adjacent to one of the partition walls BR (on the left side of the cell C1 in the figure) on both sides of the cell C1. ing. In this embodiment, a part of the address electrode AE is located on the partition wall BR.

  The transparent electrode Xt is disposed in each cell C1, is formed in a shape that protrudes from the bus electrode Xb toward the bus electrode Yb and decreases in width toward the tip. In the example shown in the figure, the transparent electrode Xt is formed in a trapezoidal shape including a side SD10 (first side), SD12 (first oblique side), SD14, and SD16. That is, in this embodiment, the transparent electrode Xt has a side SD10 (first side) along the partition BR (the other partition, the right partition BR in the figure) positioned away from the address electrode AE, and the side SD10. And a side SD12 (first oblique side) that is diagonally opposed.

  The transparent electrode Yt is disposed in each cell C1, and is formed in a shape that protrudes from the bus electrode Yb toward the bus electrode Xb and decreases in width toward the tip. In the example shown in the figure, the transparent electrode Yt is formed in a trapezoidal shape including a side SD20 (second side), SD22 (second oblique side), SD24, and SD26. That is, in this embodiment, the transparent electrode Yt has a side SD20 (second side) along the address electrode AE and a side SD22 (second oblique side) facing the side SD12 of the transparent electrode Xt. In other words, in the transparent electrode Yt (scanning electrode YE), the side SD20 faces the address electrode AE, and the side SD22 faces the transparent electrode Xt (sustain electrode XE).

  Thus, by applying a voltage between the address electrode AE and the transparent electrode Yt, an address discharge can be generated in the discharge space DS of the cell C1 of interest. Further, by applying a voltage between the transparent electrode Xt and the transparent electrode Yt, a sustain discharge can be generated in the discharge space DS of the cell C1 selected by the address discharge. Note that, in the transparent electrodes Xt and Yt, the sides SD12 and SD22 extending obliquely with respect to the bus electrodes Xb and Yb face each other. Therefore, even when the width of the cell C1 in the first direction D1 is narrow, the facing portion is made long. it can. Thereby, in this embodiment, the minimum voltage (discharge start voltage) for generating a discharge between the transparent electrodes Xt and Yt can be lowered, and the voltage necessary for generating the sustain discharge can be lowered.

  Here, in order to prevent erroneous discharge without increasing the voltage necessary for generating the sustain discharge, the transparent electrodes Xt and Yt having sides opposite to each other along the second direction D2 are formed according to the present invention. Thought in the process. However, in this case, since each transparent electrode Xt, Yt is formed thin with the same width from the root to the tip, there is a risk of disconnection from the root. For example, when the transparent electrodes Xt and Yt are disconnected from the base, the portions functioning as the transparent electrodes Xt and Yt (portions connected to the bus electrodes Xb and Yb) become smaller or function as the transparent electrodes Xt and Yt. The part disappears and the PDP does not operate normally.

  If the transparent electrodes Xt, Yt are disconnected from the vicinity of the tip, the remaining part (the part connected to the bus electrodes Xb, Yb) is large, so that the remaining part functions normally as the transparent electrodes Xt, Yt. The PDP may operate normally. Therefore, in the PDP having the transparent electrodes Xt and Yt formed thin with the same width from the base to the tip, there is a possibility of disconnection from the base, so that the manufacturing yield or the reliability is lowered. On the other hand, in this embodiment, since the bases of the transparent electrodes Xt and Yt are wide, it is possible to prevent disconnection from the bases of the transparent electrodes Xt and Yt. Thereby, in this embodiment, the manufacturing yield of PDP or the reliability of PDP can be improved.

  Further, in the transparent electrode Yt of each cell C1, the side SD20 facing the address electrode AE that generates the address discharge is the address electrode AE that does not generate the address discharge (in the figure, the address electrode of the cell C1 on the right side of the cell C1 of interest). It is longer than side SD24 facing AE). Thus, in this embodiment, in the target cell C1, the discharge start voltage between the transparent electrode Yt and the address electrode AE in the cell C1 is set to the address electrode AE in the cell C1 adjacent to the transparent electrode Yt and the target cell C1. It can be lower than the discharge start voltage between. As a result, in this embodiment, in the two cells C1 adjacent to each other in the first direction D1, when the address discharge is generated in one cell C1 (address period), the transparent electrode Yt of one cell C1 and the other It is possible to prevent erroneous discharge from occurring between the address electrodes AE of the cell C1.

  Further, the transparent electrode Yt is disposed on the address electrode AE side. Therefore, in the two cells C1 adjacent to each other in the first direction D1, the distance W1 between the transparent electrode Yt of one cell C1 and the address electrode AE is equal to the transparent electrode Yt of one cell C1 and the address electrode of the other cell C1. It is shorter than the distance W2 between AEs. For this reason, in this embodiment, the discharge start voltage between one transparent electrode Yt and the address electrode AE can be made lower than the discharge start voltage between one transparent electrode Yt and the address electrode AE of the other cell C1.

  As a result, in this embodiment, when the address discharge is generated in one cell C1 in two cells C1 adjacent to each other in the first direction D1, the address of the transparent electrode Yt of one cell C1 and the other cell C1 It is possible to reliably prevent erroneous discharge from occurring between the electrodes AE. As described above, by making the side SD20 longer than the side SD24, erroneous discharge between the transparent electrode Yt that does not generate address discharge and the address electrode AE can be prevented. Therefore, the transparent electrode Yt includes the distance W1 and the distance W2. May be arranged to be the same.

  FIG. 3 shows a cross section of the PDP 10 shown in FIG. FIG. 3 shows a cross section of the PDP 10 taken along the line A-A ′ of FIG. 2.

  A part of the address electrode AE is located on the discharge space DS of the cell C1 in which the transparent electrode Yt that generates the address discharge with itself is disposed, and the transparent electrode Yt that does not generate the address discharge with the address electrode AE is disposed. It is not located on the discharge space DS of the cell C1. That is, the electric field between the address electrode AE and the transparent electrode Yt of the target cell C1 is generated without passing through the partition BR, and the address electrode AE of the target cell C1 and the transparent electrode Yt of the cell C1 adjacent to the target cell C1. An electric field therebetween is generated through the partition wall BR.

  Thereby, the discharge start voltage between the transparent electrode Yt of the target cell C1 and the address electrode AE is determined by the discharge start voltage between the address electrode AE of the target cell C1 and the transparent electrode Yt of the cell C1 adjacent to the target cell C1. Can be lowered. As a result, it is possible to prevent erroneous discharge between the address electrode AE of the target cell C1 and the transparent electrode Yt of the cell C1 adjacent to the target cell C1.

  FIG. 4 shows an example of a plasma display device configured using the PDP 10 shown in FIG. The plasma display device (hereinafter also referred to as a PDP device) includes a PDP 10, an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, and a front housing 30 disposed on the image display surface 16 side of the PDP 10. The rear housing 40 and the base chassis 50 disposed on the back surface 18 side of the PDP 10, the circuit unit 60 for driving the PDP 10 attached to the rear housing 40 side of the base chassis 50, and the PDP 10 are attached to the base chassis 50. A double-sided adhesive sheet 70 for attaching is provided. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

  FIG. 5 shows an outline of a circuit unit 60 for driving the PDP 10 shown in FIG. The circuit unit 60 includes an X driver XDRV that applies a common pulse to the bus electrode Xb, a Y driver YDRV that selectively applies a pulse to the bus electrode Yb, an address driver ADRV that selectively applies a pulse to the address electrode AE, and a driver. It has a control unit CNT and a power supply unit PWR that control the operation of XDRV, YDRV, and ADRV. The drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10. The power supply unit PWR generates power supply voltages Vsc, Vs / 2, −Vs / 2, Vsa and the like to be supplied to the drivers YDRV, XDRV, and ADRV.

  The control unit CNT selects a subfield to be used based on the image data R0-7, G0-7, B0-7, and outputs control signals YCNT, XCNT, and ACNT to the drivers YDRV, XDRV, and ADRV. Here, the subfield is a field obtained by dividing one field for displaying one screen of the PDP 10, and the number of sustain discharges is set for each subfield. A multi-tone image is displayed by selecting a subfield to be used for each cell C1 constituting the pixel.

  FIG. 6 shows an example of the discharge operation in the subfield for displaying an image on the PDP 10 shown in FIG. The star in the figure indicates the occurrence of discharge. Each subfield SF includes a reset period RST, an address period ADR, a sustain period SUS, and an erase period ERS. Note that the erase period ERS is defined as being included in the sustain period SUS because it is a period for generating a discharge for reducing the wall charge of only the lit cells.

  First, in the reset period RST, a negative voltage (blunt wave) that gently falls is applied to the sustain electrode XE (bus electrode Xb and transparent electrode Xt), and a positive voltage is applied to the scan electrode YE (bus electrode Yb and transparent electrode). Applied to the electrode Yt) (FIG. 6A). The sustain electrode XE is maintained at a negative write voltage, and a positive write voltage (write blunt wave) that gradually increases is applied to the scan electrode YE (FIG. 6B). As a result, positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively, while suppressing light emission of the cell. Next, a positive adjustment voltage is applied to the sustain electrode XE, and a negative adjustment voltage (adjusted obtuse wave) is applied to the scan electrode YE (FIG. 6C). This reduces the amount of positive and negative wall charges accumulated in the sustain electrode XE and the scan electrode YE, respectively, and makes the wall charges of all cells equal. For example, the positive adjustment voltage is a voltage lower than the voltage Vs / 2, and the minimum value of the negative adjustment voltage is a voltage higher than the voltage −Vs / 2.

  In the address period ADR, a scan voltage that serves as an anode during address discharge is applied to the sustain electrode XE, a scan pulse that serves as a cathode during address discharge is applied to the scan electrode YE, and an address pulse (voltage Vsa) that serves as an anode during address discharge. The voltage is applied to the address electrode AE corresponding to the lighted cell (FIG. 6D). In the cell selected by the scan pulse and the address pulse, an address discharge is temporarily generated.

  That is, a voltage equal to or higher than the lowest voltage (discharge start voltage) for generating discharge is applied between the scan electrode YE and the address electrode AE, and a voltage lower than the discharge start voltage is applied between the sustain electrode XE and the address electrode AE. Is done. Thereby, when the address discharge is generated between the address electrode AE and the scan electrode YE of the cell of interest, it is possible to prevent the erroneous discharge from occurring between the sustain electrode XE and the address electrode AE of the adjacent cell. The second address pulse shown in the waveform of the address electrode AE is applied to select the discharge cells of other display lines (FIG. 6 (e)).

  In the sustain period SUS, negative and positive sustain pulses are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 6 (f, g)). Thereby, the discharge state of the lighted cell is maintained. Sustain pulses having different polarities are repeatedly applied to the sustain electrode XE and the scan electrode YE, so that the discharge of the cells lit in the sustain period SUS (sustain discharge) is repeatedly performed.

  In the erase period ERS, a negative pre-erase pulse and a positive high-voltage pre-erase pulse are applied to the sustain electrode XE and the scan electrode YE, respectively, and discharge is generated (FIG. 6 (h)). As a result, wall charges are accumulated in sustain electrode XE and scan electrode YE. At this time, since a voltage higher than the voltage Vs / 2 is applied to the scanning electrode YE, the amount of accumulated wall charges is relatively large. Next, a positive erase pulse and a negative erase pulse are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 6 (i)). As a result, discharge occurs, but since the difference in voltage value applied between the two electrodes is lower than the difference in voltage value in the sustain period SUS, the amount of wall charges is reduced compared to the sustain period SUS.

  As described above, in the first embodiment, the transparent electrode Yt is disposed in each cell C1, and protrudes from the bus electrode Yb toward the bus electrode Xb. The transparent electrode Yt is formed in a shape that decreases in width toward the tip. The transparent electrode Yt (scanning electrode YE) has a side SD20 facing the address electrode AE and a side SD22 facing the transparent electrode Xt (sustain electrode XE). Further, the transparent electrode Yt is formed such that the side SD20 facing the address electrode AE corresponding to itself is longer than the side SD24 facing the address electrode AE not corresponding to itself. As a result, erroneous discharge between the transparent electrode Yt and the address electrode AE can be prevented. Further, in the transparent electrodes Xt and Yt, since the sides SD12 and SD22 extending obliquely with respect to the bus electrodes Xb and Yb face each other, erroneous discharge can be performed without increasing the voltage necessary for generating the sustain discharge. Can be prevented.

  FIG. 7 shows an overview of the PDP 10 in the second embodiment of the present invention. FIG. 7 shows the state of the electrodes Xb, Xt, Yb, Yt, AE, and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the position where the address electrode AE is arranged is different from that of the first embodiment described above. Other configurations are the same as those of the first embodiment. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The address electrodes AE are arranged so as to be entirely located on the discharge space DS in each cell C1. Accordingly, in this embodiment, the volume (amount) of the partition wall BR interposed between the address electrode AE of the target cell C1 and the transparent electrode Yt of the cell C1 adjacent to the target cell C1 is compared with that of the first embodiment. Can be bigger. As a result, in this embodiment, the difference between the discharge start voltage between the transparent electrode Yt and the address electrode AE corresponding to each other and the discharge start voltage between the transparent electrode Yt and the address electrode AE not corresponding to each other can be increased. Thereby, in this embodiment, the erroneous discharge between the transparent electrode Yt and the address electrode AE can be reliably prevented as compared with the first embodiment. As mentioned above, also in 2nd Embodiment, the effect similar to 1st Embodiment mentioned above can be acquired.

  FIG. 8 shows an overview of the PDP 10 in the third embodiment of the present invention. FIG. 8 shows the state of the electrodes Xb, Xt, Yb, Yt, AE, and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the position at which the transparent electrode Yt is arranged is different from the second embodiment described above. Other configurations are the same as those of the second embodiment. The same elements as those described in the second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  When viewed from the image display surface side, the transparent electrode Yt is disposed so as to partially overlap the address electrode AE. That is, a part of the transparent electrode Yt overlaps the address electrode AE via the dielectric layer (dielectric layer DL1 shown in FIG. 3 described above). The transparent electrode Yt may be arranged such that the side SD20 is at the same position as the edge EG1 of the address electrode AE. In this embodiment, the distance between the transparent electrode Yt and the address electrode AE that do not correspond to each other can be increased, and erroneous discharge between the transparent electrode Yt and the address electrode AE that do not correspond to each other can be prevented. The position where the address electrode AE is disposed may be the same as that in the first embodiment (FIG. 2) described above. As described above, also in the third embodiment, the same effects as those of the first and second embodiments described above can be obtained.

  In the above-described embodiment, an example in which one pixel is configured by three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), Cells that generate colors other than blue (B) may be included.

  In the above-described embodiment, the example in which the partition wall BR is disposed only at the position facing the address electrode AE has been described. The present invention is not limited to such an embodiment. For example, a partition extending in the vertical direction of the address electrode AE (the first direction D1 shown in FIG. 1 described above) may be provided on the glass substrate RS. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the transparent electrodes Xt and Yt are formed in a trapezoidal shape has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 9, the transparent electrodes Xt and Yt may be formed in a triangular shape. FIG. 9 shows the state of the electrodes Xb, Xt, Yb, Yt, AE, and the partition wall BR viewed from the image display surface side (upper side in FIG. 1). In this example, the shapes of the transparent electrodes Xt and Yt are different from those of the first embodiment described above. Other configurations are the same as those of the first embodiment. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The transparent electrode Xt is formed in a triangular shape composed of a side SD10 (first side), SD12 (first oblique side), and SD16 with the side SD16 along the bus electrode Xb as a base. Further, the transparent electrode Yt is formed in a triangular shape including the side SD20 (first side), SD22 (first oblique side), and SD26 with the side SD26 along the bus electrode Yb as the bottom side. Thereby, in this example, compared with the first embodiment, the sides SD12, SDt 22 facing each other of the transparent electrodes Xt, Yt can be lengthened, so that the discharge start voltage between the transparent electrodes Xt, Yt can be lowered. As a result, in this example, the voltage required for generating the sustain discharge can be made lower than that in the first embodiment. Also in this case, the same effect as the above-described embodiment can be obtained.

  Note that the position where the address electrode AE is disposed may be the same as in the second embodiment (FIG. 7) described above. Further, the position where the transparent electrode Yt is arranged may be the same as in the third embodiment (FIG. 8) described above. Also in this case, the same effect as the above-described embodiment can be obtained. Further, the transparent electrode Xt may be formed in a shape in which at least one of the corners CR10 and CR12 is chamfered, and the transparent electrode Yt may be formed in a shape in which at least one of the corners CR20 and CR22 is chamfered.

  For example, FIG. 10 shows an outline of the PDP 10 in which the corners CR10 and CR20 shown in FIG. 9 are chamfered. FIG. 11 shows an outline of the PDP 10 in which the corners CR12 and CR22 shown in FIG. 9 are chamfered. The shape of the transparent electrodes Xt and Yt in the cell C1 may be a triangle as in the example shown in FIG. 11 or a trapezoid as shown in FIG. Further, FIG. 12 shows an outline of the PDP 10 in which the corners CR10, CR12, CR20, and CR22 shown in FIG. 9 are chamfered. The corners CR10 and CR20 may be arcuate rather than linear chamfers.

  That is, the above-described transparent electrode Xt shown in FIGS. 2, 10, 11, and 12 has the side SD16 (third side) along the bus electrode Xb, the side SD12 (first oblique side), and the remaining sides. Are formed in a shape in which at least one of the two corners (corners CR10 and CR12) is chamfered. The transparent electrode Yt has a side SD26 (fourth side) along the bus electrode Yb, and at least two corners (corners CR20 and CR22) formed by the side SD22 (second oblique side) and the remaining side. One is formed into a chamfered shape. Also in these cases, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the transparent electrode Xt has the side SD10 along the partition BR at a position away from the address electrode AE and the transparent electrode Yt has the side SD20 along the address electrode AE has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 13, the transparent electrode Xt has a side SD11 extending in an oblique direction with respect to the partition wall BR at a position away from the address electrode AE (right partition wall BR in FIG. 13) instead of the side SD10. You may have. Further, the transparent electrode Yt may have SD21 extending in an oblique direction with respect to the address electrode AE instead of the side SD20. FIG. 13 shows the state of the electrodes Xb, Xt, Yb, Yt, AE, and the partition wall BR viewed from the image display surface side (upper side in FIG. 1).

  Instead of the side SD10 (first side), the transparent electrode Xt is a side that extends in an oblique direction with respect to the partition wall BR (the other partition BR, the right partition wall BR in FIG. 13) located away from the address electrode AE. It has SD11 (fifth side). The acute angle AG10 formed by the extension line of the side SD11 and the other partition wall BR is smaller than the angle of the acute angle AG12 formed by the extension line of the side SD12 (first oblique side) and the other partition wall BR. Further, the transparent electrode Yt has SD21 (sixth side) extending in an oblique direction with respect to the address electrode AE, instead of the side SD20 (second side). The acute angle AG20 formed by the extension line of the side SD21 and the address electrode AE is smaller than the acute angle AG22 formed by the extension line of the side SD22 (second oblique side) and the address electrode AE. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  The present invention can be applied to a plasma display panel used in a display device.

Claims (7)

A first substrate and a second substrate facing each other through a discharge space;
A first electrode comprising a first bus electrode disposed on the first substrate and extending in a first direction; and a first display electrode connected to the first bus electrode;
A second bus electrode disposed on the first substrate and extending in the first direction; and a second display electrode connected to the second bus electrode and paired with the first electrode. Electrodes,
A plurality of partition walls extending in a second direction intersecting the first direction and spaced apart on the second substrate;
A cell formed in a region surrounded by the first and second bus electrodes and the partition;
A dielectric layer provided on the first substrate and covering the first and second electrodes;
One of the partition walls and the other partition wall provided on the dielectric layer, extending in the second direction through each cell, and disposed on both sides of the cell. A plurality of address electrodes arranged adjacent to each other;
The first display electrode is disposed in each cell, protrudes from the first bus electrode toward the second bus electrode, and has a shape that becomes narrower toward the tip, and extends along the other partition wall. A first side and a first hypotenuse that diagonally opposes the first side;
The second display electrode is disposed in each of the cells, protrudes from the second bus electrode toward the first bus electrode, and has a shape with a width that decreases toward the tip. The second display electrode extends along the address electrode. A plasma display panel having two sides and a second hypotenuse opposite to the first hypotenuse. The plasma display panel according to claim 1, wherein
Each said 2nd display electrode is arrange | positioned at the said address electrode side of each said cell, The plasma display panel characterized by the above-mentioned. The plasma display panel according to claim 1, wherein
A part of the second display electrode overlaps with the address electrode through the dielectric layer. The plasma display panel according to claim 1, wherein
The plasma display panel, wherein the address electrode is located on the discharge space of the cell. The plasma display panel according to claim 1, wherein
The plasma display panel according to claim 1, wherein a part of the address electrode is located on the one partition wall. The plasma display panel according to claim 1, wherein
Each of the first display electrodes is formed in a triangular shape having a side along the first bus electrode as a base.
Each of the second display electrodes is formed in a triangular shape having a side along the second bus electrode as a base. The plasma display panel according to claim 1, wherein
Each of the first display electrodes is
Having a third side along the first bus electrode;
At least one of two corners formed by the first oblique side and the remaining side is formed into a chamfered shape,
Each of the second display electrodes is
Having a fourth side along the second bus electrode;
A plasma display panel, wherein at least one of two corners formed by the second oblique side and the remaining side is chamfered.

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