JPS639978A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPS639978A JPS639978A JP15438886A JP15438886A JPS639978A JP S639978 A JPS639978 A JP S639978A JP 15438886 A JP15438886 A JP 15438886A JP 15438886 A JP15438886 A JP 15438886A JP S639978 A JPS639978 A JP S639978A
- Authority
- JP
- Japan
- Prior art keywords
- source
- thin film
- film transistor
- film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010408 film Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 9
- 238000000137 annealing Methods 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 150000004678 hydrides Chemical class 0.000 abstract 1
- 230000037230 mobility Effects 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタの製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor.
従来、液晶ディスプレイまたは密着型イメージセンサ等
で用いられる薄膜トランジスタの多くは、アモルファス
シリコンか或いは多結晶シリコンの基板上に形成される
。特に、アモルファスシリコンは大面積にわたって一様
にしかも低温で成膜できるのでトランジスタ素子を大面
積に集積するのに適している。しかし、アモルファスシ
リコンの電子移動度はせいぜい1cm 2/V −S
e c程度でバルクシリコンの100分の1以下と小さ
いのでこれを用いたトランジスタはマトリックスのスイ
ッチング用としては充分でも駆動用周辺回路を同時に繰
込んで製造しようとすると充分なスピードをもたせるこ
とができない。また、多結晶シリコンを用いれば移動度
はかなり大きなものが得られ駆動回路の繰込みも可能と
なるが、製造工程に比較的高温のプロセスを含むので使
用できる絶縁基板等に材質上の制限を受ける。すなわち
、高価なガラス基板しか使用できない。これは大面積の
絶縁基板を用いる場合にはコスト上大きな問題を生じる
。Conventionally, most thin film transistors used in liquid crystal displays, contact image sensors, and the like are formed on amorphous silicon or polycrystalline silicon substrates. In particular, amorphous silicon is suitable for integrating transistor elements over a large area because it can be formed uniformly over a large area and at low temperatures. However, the electron mobility of amorphous silicon is at most 1 cm 2 /V −S
It is about 100 times smaller than bulk silicon, so a transistor using this is sufficient for matrix switching, but cannot be manufactured at sufficient speed if peripheral driving circuits are included at the same time. . In addition, if polycrystalline silicon is used, a considerably high mobility can be obtained and it is possible to renormalize the drive circuit, but since the manufacturing process involves a relatively high temperature process, there are material limitations on the insulating substrates etc. that can be used. receive. That is, only expensive glass substrates can be used. This poses a major cost problem when using a large-area insulating substrate.
従って、ガラス基板を低温に保ちつつ非晶質の半導体膜
の表面部分のみを局所的に加熱溶解し高移動度の多結晶
薄膜を得る手段として紫外レーザ光照射による技術が提
案された。(例えば、プロシーディング オブ 第16
回 個体素子材料コンファレンス、C−3−8,p12
>。これは、波長400nm以下の光の半導体層に対す
る吸収深さは約数百Aであり半導体層表面のみを加熱さ
せることができるという考えから生れたものである。Therefore, a technique using ultraviolet laser light irradiation has been proposed as a means of locally heating and melting only the surface portion of an amorphous semiconductor film while keeping the glass substrate at a low temperature to obtain a polycrystalline thin film with high mobility. (For example, Proceedings of the 16th
3rd Solid State Element Materials Conference, C-3-8, p12
>. This is based on the idea that the absorption depth of light with a wavelength of 400 nm or less into a semiconductor layer is about several hundred amps, and that only the surface of the semiconductor layer can be heated.
第4図(a)〜(d)および第5図は紫外レーザ光をも
ちいた従来の薄膜トランジスタの製造工程図を示すもの
である。ここで第4図の製造方法によれば、ガーラス基
板1上の非晶質半導体膜2には紫外パルスレーザ光10
.J・照もさn多結晶化、高移動度1ヒが、まず(a)
図の如く行われる。ついでゲート絶縁膜3およびゲート
電極4から成るゲート部が成膜パターニングにより形成
されたあと、更に自己整合技術によりイオン11が注入
されることによってソースおよびドレインの各領域がそ
れぞれ形成される。〔第4図(b)参照〕。4(a) to 5(d) and FIG. 5 show a manufacturing process diagram of a conventional thin film transistor using ultraviolet laser light. According to the manufacturing method shown in FIG. 4, the amorphous semiconductor film 2 on the glass substrate 1 is exposed to ultraviolet pulsed laser
.. J. Terumosa n Polycrystalline, high mobility 1st first (a)
This is done as shown in the figure. After a gate portion consisting of a gate insulating film 3 and a gate electrode 4 is formed by film formation and patterning, ions 11 are further implanted by a self-alignment technique to form source and drain regions, respectively. [See Figure 4(b)].
この後、イオン注入層の活性化のため紫外レーザ10が
再び照射され、ついでソース電極6およびドレイン電極
7をそれぞれ設けることによって完成品となる! 〔第
4図(c)および(d)参照〕。従って、この製造方法
によると2回の紫外レーザ光による熱処理工程が含まれ
る。After this, the ultraviolet laser 10 is irradiated again to activate the ion-implanted layer, and then a source electrode 6 and a drain electrode 7 are provided, respectively, resulting in a completed product! [See Figures 4(c) and (d)]. Therefore, this manufacturing method includes two heat treatment steps using ultraviolet laser light.
また、第5図は所謂スタッガート構造の薄膜トランジス
タの製造方法を示すものであるが、この場合には紫外レ
ーザ光10が上下より一度に照射される。この方法によ
ると熱処理工程は1回ですむが、半導体膜2とガラス基
板1との境界面が加熱されるためガラス基板として使用
出来るものに材質上制限が加わるという欠点がある。Further, FIG. 5 shows a method of manufacturing a thin film transistor having a so-called staggered structure, and in this case, ultraviolet laser light 10 is irradiated from above and below at once. According to this method, only one heat treatment step is required, but the interface between the semiconductor film 2 and the glass substrate 1 is heated, so there is a drawback that there are restrictions on the materials that can be used as the glass substrate.
本発明の目的は、上記の状況に鑑み、少なくともゲート
電極を透明金属で形成することによってこの透明電極か
らの唯一回の紫外光レーザの照射により電極層のアニー
ル、チャネル部分の高移動化及びソース、ドレイン領域
の活性化を同時に行い得るようにした薄膜トランジスタ
の製造方法を提供することである。In view of the above-mentioned circumstances, an object of the present invention is to form at least the gate electrode with a transparent metal, thereby annealing the electrode layer, increasing the mobility of the channel portion, and increasing the mobility of the source through a single ultraviolet laser irradiation from the transparent electrode. Another object of the present invention is to provide a method for manufacturing a thin film transistor in which the drain region can be activated at the same time.
本発明によれば、薄膜トランジスタの製造方法は、絶縁
基板上の非晶質半導体膜を紫外レーザ光の照射により多
結晶化し且つアニールする半導体結晶膜の熱処理工程を
含む薄膜トランジスタの製造方法において、前記薄膜ト
ランジスタのゲートおよび或いはソース、ドレイン電極
をそれぞれ透明金属で形成し、前記ゲートおよび或いは
ソース、ドレイン電極の透過光を介しチャネルおよび或
いはソース、トレイン領域の非晶質半導体膜を熱処理す
る紫外レーザ光照射工程を備えることを含む。According to the present invention, a method for manufacturing a thin film transistor includes a heat treatment step for a semiconductor crystal film in which an amorphous semiconductor film on an insulating substrate is polycrystallized by irradiation with ultraviolet laser light and annealed. an ultraviolet laser beam irradiation step in which the gate and/or source and drain electrodes are each made of a transparent metal, and the amorphous semiconductor film in the channel and/or source and train regions is heat-treated through the transmitted light of the gate and/or source and drain electrodes; including having
ここで、透明金属には酸化インジウム・スズ合金を用い
ることができ、またその膜厚は800〜1000Aの範
囲に設定される。Here, an indium tin oxide alloy can be used as the transparent metal, and its film thickness is set in a range of 800 to 1000 Å.
通常、アモルファスシリコンおよび多結晶シリコンはバ
ルクシリコンに比べ電子移動度がかなり低い。これは主
にアモルファスシリコンでは未結合手によるダングリン
グボンド、多結晶シリコンでは結晶中の粒界界面等に数
多く存在するダングリングボンドにトラップされたキャ
リアによるバリアの影響であるといわれている。従って
、非晶質のアモルファスシリコンでは純粋なアモルファ
スシリコンでなく、一般には水素化されたものが使われ
ている。この水素が膜中に存在するダングリングボンド
を不活性化してバリアのポテンシャルを下げるので実用
可能な膜となる。多結晶シリコンにおいても水素化し結
晶粒界でのダウンリングポンドを不活性化することによ
って結晶粒界のバリアを下げることができればかなりの
高移動度が期待できる。しかし通常の方法では水素化し
た多結晶シリコンを成膜することはむずかしい。そこで
、水素化されたアモルファスシリコンをまず成膜しこれ
に短時間のパルスレーザアニールを行えば水素が抜ける
間もなぐ多結晶化せしめ得るので膜中に水素を残した水
素化多結晶膜として成膜することができる。この方法に
よると基板温度を土げずに多結晶化することができると
共に、水素化されているので従来の多結晶膜よりも高移
動度な膜が得られる。Amorphous silicon and polycrystalline silicon typically have significantly lower electron mobilities than bulk silicon. This is said to be mainly due to the barrier effect of carriers trapped in dangling bonds caused by dangling bonds in amorphous silicon, and in polycrystalline silicon, which exist in large numbers at grain boundary interfaces in crystals. Therefore, amorphous silicon is not pure amorphous silicon, but hydrogenated silicon is generally used. This hydrogen inactivates the dangling bonds present in the film and lowers the barrier potential, making the film usable for practical use. Even in polycrystalline silicon, considerably high mobility can be expected if the barrier at the grain boundaries can be lowered by hydrogenating and inactivating the down-ring ponds at the grain boundaries. However, it is difficult to deposit hydrogenated polycrystalline silicon using conventional methods. Therefore, by first forming a film of hydrogenated amorphous silicon and then subjecting it to short-time pulsed laser annealing, it becomes polycrystalline as soon as the hydrogen is released, so the film can be formed as a hydrogenated polycrystalline film with hydrogen remaining in the film. It can be membraned. According to this method, it is possible to form a polycrystalline film without lowering the substrate temperature, and since it is hydrogenated, a film with higher mobility than conventional polycrystalline films can be obtained.
従って本発明による通常の薄膜トランジスタ(FET)
の製造プロセスでは、絶縁基板ガラス上に水素化アモル
ファス半導体薄膜、ゲート絶縁膜、およびゲート電極用
としての透明金属がまず基板温度300℃以下において
それぞれ成膜される。Therefore, the conventional thin film transistor (FET) according to the present invention
In the manufacturing process, a hydrogenated amorphous semiconductor thin film, a gate insulating film, and a transparent metal for a gate electrode are first formed on a glass insulating substrate at a substrate temperature of 300° C. or lower.
この透明金属はスパッタ法により基板温度100℃程度
で約1000Aの厚さに成膜されるにの厚さはゲータ電
極としてのパターニングのしやすさと電極としての抵抗
率、紫外光の透過エネルギー量およびイオン注入に対し
て必要となるマスクの厚さとのかね合いで決まる。従っ
てこの透明金属の厚さはこの製造方法にあっては重要な
要素である。ついで、この成膜をパターニングすること
によってゲート電極が形成され、更にこのゲート電極を
用い、自己整合によりイオン注入を行ないソース、ドレ
イン領域がそれぞれ形成される。この後全面に紫外パル
スレーザ光が照射され、チャネル部は透明なゲート電極
を通して光アニールされると共に高移動度化される。ま
たソースおよびトレイン領域のイオン注入層の活性化も
同時に行なわれる。従ってプロセスの簡略化および再現
性が著しく向上する。勿論、ゲート電極だけでなくソー
ス、トレインの各電極も同じように透明金属で形成して
もよい、この際、光アニールに用いる紫外パルスレーザ
光としては、例えばXeClエキシマレーザ、波長30
8nmがある。This transparent metal is formed into a film with a thickness of about 1000A using a sputtering method at a substrate temperature of about 100℃. It is determined by the balance between the thickness of the mask required for ion implantation. Therefore, the thickness of the transparent metal is an important factor in this manufacturing method. Next, a gate electrode is formed by patterning this film, and further, using this gate electrode, ion implantation is performed by self-alignment to form source and drain regions, respectively. Thereafter, the entire surface is irradiated with ultraviolet pulsed laser light, and the channel portion is optically annealed through a transparent gate electrode and its mobility is increased. The ion implantation layers in the source and train regions are also activated at the same time. Process simplification and reproducibility are therefore significantly improved. Of course, not only the gate electrode but also the source and train electrodes may be made of transparent metal. In this case, the ultraviolet pulsed laser beam used for optical annealing may be, for example, a XeCl excimer laser with a wavelength of 30 nm.
There is 8 nm.
いま、透明金属として例えば酸化インジウム・スズ合金
(ITO>を用いた場合には、この金属の透過率は30
%程度と低いが、この透過率は熱処理の経過と共に向上
する。従ってゲート電極部の光アニールと共に半導体膜
のアニールも効率的に行なうことができる。この場合、
酸化インジウム・スズ合金(ITO>の透過率は波長が
短くなるとともに悪くなるのでこれより短い波長はあま
り適当ではない。従来のようにゲート電極をCr等の不
透明な通常金属で形成すると紫外光に対する吸収係数が
余りにも大きいため、紫外光レーザを強くあてた場合に
はゲート電極が蒸散するか、或いは電極層と絶縁膜との
間の熱膨張率の差で電極層のみならず半導体膜までが蒸
散的に飛散するといった現象がおこる。従ってこのよう
な現象がおこらない程度のレーザパワーでは半導体膜を
充分には熱処理できないこととなる。すなわち、本発明
によればこれらの問題を含めた従来技術の諸問題を一挙
に解決し得る。以下図面を参照して本発明の詳細な説明
する。For example, if an indium tin oxide alloy (ITO) is used as a transparent metal, the transmittance of this metal is 30.
%, but this transmittance improves as the heat treatment progresses. Therefore, both the photo-annealing of the gate electrode portion and the annealing of the semiconductor film can be efficiently performed. in this case,
The transmittance of indium tin oxide alloy (ITO) worsens as the wavelength becomes shorter, so wavelengths shorter than this are not very suitable.If the gate electrode is made of an opaque normal metal such as Cr as in the past, it will not be able to withstand ultraviolet light. Because the absorption coefficient is so large, if the ultraviolet laser is applied strongly, the gate electrode may evaporate, or the difference in thermal expansion coefficient between the electrode layer and the insulating film may damage not only the electrode layer but also the semiconductor film. A phenomenon such as evaporative scattering occurs.Therefore, the semiconductor film cannot be sufficiently heat-treated with a laser power that does not cause such a phenomenon.In other words, the present invention overcomes the conventional technology including these problems. The following problems will be solved at once.The present invention will be described in detail below with reference to the drawings.
第1図(a)〜(c)は本発明の一実施例を示す工程図
である。本実施例によればゲート電極のみが透明金属(
例えば酸化インジウム・スズ合金)で形成される。すな
わち、第1図(a>に示すように、ガラス基板1の水素
化アモルファス半導体薄膜2上にはゲート絶縁膜3およ
び透明金属からなるゲート電極9がまずパターニングさ
れる。この際、水素化アモルファス半導体薄膜2はプラ
ズマCVD法により成膜され、また、ゲート絶縁膜、は
同じくプラズマ法からなる二酸化シリコンもしくは窒化
シリコンの成膜からそれぞれ成膜される。FIGS. 1(a) to 1(c) are process diagrams showing one embodiment of the present invention. According to this embodiment, only the gate electrode is made of transparent metal (
For example, it is made of an indium tin oxide alloy). That is, as shown in FIG. 1 (a), a gate insulating film 3 and a gate electrode 9 made of transparent metal are first patterned on the hydrogenated amorphous semiconductor thin film 2 of the glass substrate 1. At this time, the hydrogenated amorphous semiconductor thin film 2 is patterned. The semiconductor thin film 2 is formed by a plasma CVD method, and the gate insulating film is formed from silicon dioxide or silicon nitride, which is also formed by a plasma method.
このときの基板温度は共に300℃程度である。The substrate temperature at this time is approximately 300°C.
また、透明金属には酸化インジウム・スズ合金(ITO
)が使用され、スバ・ツタ法により基板温度100℃程
度において約1000A程度の厚さに成膜される。この
厚さは酸化インジウム・スズ合金膜のパターニングのし
やすさと電極としての抵抗率とのかねあいできめたちの
である。In addition, indium tin oxide alloy (ITO) is used as a transparent metal.
) is used, and the film is formed to a thickness of about 1000 Å at a substrate temperature of about 100° C. by the Suba-Tsuta method. This thickness is determined by the tradeoff between ease of patterning the indium tin oxide alloy film and resistivity as an electrode.
このゲート電極部のパターニング形成後イオン注入法に
よりP−たけ、B′イオン11が10 / cm程度打
ち込まれ自己整合的にソース、ドレイン領域がそれぞれ
形成される。ついで第1図(b)に示す如く紫外パルス
レーザ光10が透明電極9側より照射され、この熱処理
によってまず透明電極9のアニールついでチャネル領域
の多結晶化、高移動度化およびソース、トレイン領域に
おけるキャリアの活性化が同時に行なわれる。この熱処
理工程では紫外パルスレーザ光10としてXeC1エキ
シマレーザの波長308n−mをもちいた。After patterning the gate electrode portion, P- and B' ions 11 are implanted at a thickness of about 10 cm by ion implantation to form source and drain regions in a self-aligned manner. Next, as shown in FIG. 1(b), an ultraviolet pulsed laser beam 10 is irradiated from the transparent electrode 9 side, and this heat treatment first anneals the transparent electrode 9, then polycrystallizes the channel region, increases the mobility, and transforms the source and train regions. Activation of carriers in is performed at the same time. In this heat treatment process, a XeC1 excimer laser having a wavelength of 308 nm was used as the ultraviolet pulsed laser beam 10.
紫外光としてこれを用いるのはこれより短かい波長では
、透明ゲート電極9に対する透過率が落ちるためであり
また、これより長い波長では半導体膜2に対して深く浸
透するため局所加熱ができなくなるなめであり、更にほ
この波長域で比較的強いパワーがとり得るからである。This is used as ultraviolet light because at wavelengths shorter than this, the transmittance to the transparent gate electrode 9 decreases, and at wavelengths longer than this, it penetrates deeply into the semiconductor film 2, making local heating impossible. This is because relatively strong power can be obtained in this wavelength range.
この波長域では半導体膜2の吸収深さは約200久であ
り表面部分のみが加熱される。この後パッシベーション
膜8として二酸化シリコンまたは窒化シリコンを成膜し
、必要部分に穴開けをしてソース電極6およびドレイン
電極7をそれぞれ通常の電極材を用いて形成すれば、第
1図(c)の如き薄膜トランジスタを得る。この電極材
にはC「の抵抗加熱蒸着膜或いはスパッタ膜を用い得る
。In this wavelength range, the absorption depth of the semiconductor film 2 is approximately 200 degrees, and only the surface portion is heated. After that, silicon dioxide or silicon nitride is formed as a passivation film 8, holes are made in the necessary parts, and a source electrode 6 and a drain electrode 7 are formed using ordinary electrode materials, as shown in FIG. 1(c). A thin film transistor like this is obtained. For this electrode material, a resistance heating vapor deposited film or a sputtered film of C' can be used.
以上のプロセスでは紫外光アニール工程をのぞき池の全
ては300 ’C以下の温度であり、また、紫外光の照
射もただの1度で済む。In the above process, except for the ultraviolet light annealing process, the temperature of all the ponds is below 300'C, and the ultraviolet light irradiation only needs to be done once.
第2図(a)〜(b)は本発明の池の実施例を示す工程
図である。本実施例によれば、ゲート電極、ソース電極
およびドレイン電極の全てが透明電極で形成される。本
実施例によれば、第2図(a)に示すように、自己整合
によるイオン注入後パッシベーション膜8を被着させ、
これを窓明けして透明金属からなるソース電極12およ
びドレイン電極13が光アニール工程前にそれぞれ形成
される。従って紫外レーザ光10によるアニール工程は
完成された素子の透明電極側より第2図(b)に示す如
く行なわれる。本実施例によれば、熱処理される半導体
膜2は大気にさらされることがなく汚染等の問題から解
放されるので信頼性高き薄膜トランジスタを製造し得る
。FIGS. 2(a) to 2(b) are process diagrams showing an embodiment of the pond of the present invention. According to this embodiment, the gate electrode, source electrode, and drain electrode are all formed of transparent electrodes. According to this embodiment, as shown in FIG. 2(a), after ion implantation by self-alignment, a passivation film 8 is deposited,
By opening a window, a source electrode 12 and a drain electrode 13 made of transparent metal are formed, respectively, before a photo-annealing process. Therefore, the annealing step using the ultraviolet laser beam 10 is performed from the transparent electrode side of the completed device as shown in FIG. 2(b). According to this embodiment, the semiconductor film 2 to be heat-treated is not exposed to the atmosphere and is free from problems such as contamination, so that a highly reliable thin film transistor can be manufactured.
第3図は本発明のその池の実施例を示す部分工程図であ
る0本実施例によれば、スタ・ソガード構造の薄膜トラ
ンジスタを唯一回、の紫外レーザ光照射で製造し得る。FIG. 3 is a partial process diagram showing an embodiment of the present invention. According to this embodiment, a thin film transistor having a star-so-guard structure can be manufactured by only one irradiation with ultraviolet laser light.
すなわち、ソース、トレインの各12および13を透明
金属でそれぞれ形成したのち半導体膜2を成膜し、改め
て透明ゲート電極9を介し自己整合的にソース、ドレイ
ン領域を形成する。この後に紫外パルス光10を用いて
熱処理し完成せしめる。このように本実施例によればス
タッガード楕遺の薄膜トランジスタもより簡易な工程で
製造し得る。That is, after each of the source and train 12 and 13 is formed of transparent metal, the semiconductor film 2 is formed, and the source and drain regions are again formed in a self-aligned manner via the transparent gate electrode 9. Thereafter, heat treatment is performed using ultraviolet pulsed light 10 to complete the process. As described above, according to this embodiment, a staggered elliptical thin film transistor can also be manufactured through a simpler process.
以上詳細に説明したように、本発明によれば、紫外レー
ザ光を用いた薄膜トランジスタの製造方法を、ゲート電
極または全ての電極を透明金属で形成せしめることによ
りガラス基板を低温に保ちつつ且つ従来より簡易な工程
に改善し得る。すなわち、薄膜トランジスタの生産効率
を著しく改善し得るのみならずその信頼性の向上に順著
なる効果を有する。As described in detail above, according to the present invention, the method for manufacturing a thin film transistor using ultraviolet laser light is improved by forming the gate electrode or all electrodes from a transparent metal, while keeping the glass substrate at a low temperature, and by forming the gate electrode or all the electrodes from a transparent metal. The process can be improved to a simpler one. That is, not only can the production efficiency of thin film transistors be significantly improved, but also the reliability thereof can be significantly improved.
第1図(a)〜(c)は本発明の一実施例を示す工程図
、第2図(a)〜(b)は本発明の他の実施例を示す工
程図、第3図は本発明のその池の実施例を示す部分工程
図、第4図(a)〜(d)および第5図は紫外レーザ光
を用いた従来の薄膜トランジスタの製造工程図である。FIGS. 1(a) to (c) are process diagrams showing one embodiment of the present invention, FIGS. 2(a) to (b) are process diagrams showing another embodiment of the present invention, and FIG. Partial process diagrams showing an embodiment of the invention, FIGS. 4(a) to 4(d) and FIG. 5 are manufacturing process diagrams of a conventional thin film transistor using ultraviolet laser light.
Claims (3)
射により多結晶化し且つアニールする半導体結晶膜の熱
処理工程を含む薄膜トランジスタの製造方法において、
前記薄膜トランジスタのゲートおよび或いはソース、ド
レイン電極をそれぞれ透明金属で形成し、前記ゲートお
よび或いはソース、ドレイン電極の透過光を介しチャネ
ルおよび或いはソース、ドレイン領域の非晶質半導体膜
を熱処理する紫外レーザ光照射工程を備えることを特徴
とする薄膜トランジスタの製造方法。(1) A method for manufacturing a thin film transistor including a heat treatment step for a semiconductor crystal film in which an amorphous semiconductor film on an insulating substrate is polycrystallized by irradiation with ultraviolet laser light and annealed,
The gate and/or source and drain electrodes of the thin film transistor are each made of a transparent metal, and an ultraviolet laser beam heat-treats the amorphous semiconductor film in the channel and/or source and drain regions through transmitted light of the gate and/or source and drain electrodes. A method for manufacturing a thin film transistor, comprising an irradiation step.
O)であることを特徴とする特許請求の範囲第(1)項
記載の薄膜トランジスタの製造方法。(2) The transparent metal is an indium tin oxide alloy (IT
O) The method for manufacturing a thin film transistor according to claim (1).
00Åの範囲にそれぞれ設定されることを特徴とする特
許請求の範囲第(1)項記載の薄膜トランジスタの製造
方法。(3) The film thickness of the electrode made of the transparent metal is 800 to 10
The method for manufacturing a thin film transistor according to claim (1), wherein each of the thin film transistors is set in a range of 00 Å.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15438886A JPS639978A (en) | 1986-06-30 | 1986-06-30 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15438886A JPS639978A (en) | 1986-06-30 | 1986-06-30 | Manufacture of thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS639978A true JPS639978A (en) | 1988-01-16 |
Family
ID=15583044
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15438886A Pending JPS639978A (en) | 1986-06-30 | 1986-06-30 | Manufacture of thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS639978A (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02143559A (en) * | 1988-11-25 | 1990-06-01 | Mitsubishi Electric Corp | Image sensor and manufacture thereof |
JPH02245739A (en) * | 1989-03-20 | 1990-10-01 | Hitachi Ltd | Active matrix substrate and production thereof |
JPH05235038A (en) * | 1992-02-19 | 1993-09-10 | Casio Comput Co Ltd | Method of manufacturing thin film transistor |
JPH05235039A (en) * | 1992-02-19 | 1993-09-10 | Casio Comput Co Ltd | Method of manufacturing thin film transistor |
JPH06188268A (en) * | 1992-12-16 | 1994-07-08 | Casio Comput Co Ltd | Manufacture of thin film transistor |
JPH0791488A (en) * | 1993-09-21 | 1995-04-04 | Hayakawa Rubber Co Ltd | Tubular composite body and manufacture thereof |
JPH0791487A (en) * | 1993-09-21 | 1995-04-04 | Hayakawa Rubber Co Ltd | Tubular composite body |
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US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
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JP2002025906A (en) * | 2000-07-06 | 2002-01-25 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
KR100343307B1 (en) * | 1996-06-20 | 2002-08-22 | 가부시끼가이샤 도시바 | A method for manufacturing a thin film transistor |
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-
1986
- 1986-06-30 JP JP15438886A patent/JPS639978A/en active Pending
Cited By (21)
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---|---|---|---|---|
JPH02143559A (en) * | 1988-11-25 | 1990-06-01 | Mitsubishi Electric Corp | Image sensor and manufacture thereof |
JPH02245739A (en) * | 1989-03-20 | 1990-10-01 | Hitachi Ltd | Active matrix substrate and production thereof |
US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
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US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
JPH05235039A (en) * | 1992-02-19 | 1993-09-10 | Casio Comput Co Ltd | Method of manufacturing thin film transistor |
JPH05235038A (en) * | 1992-02-19 | 1993-09-10 | Casio Comput Co Ltd | Method of manufacturing thin film transistor |
US5917225A (en) * | 1992-03-05 | 1999-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor having specific dielectric structures |
US6624450B1 (en) * | 1992-03-27 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
JPH06188268A (en) * | 1992-12-16 | 1994-07-08 | Casio Comput Co Ltd | Manufacture of thin film transistor |
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JPH0791487A (en) * | 1993-09-21 | 1995-04-04 | Hayakawa Rubber Co Ltd | Tubular composite body |
JPH08242004A (en) * | 1995-12-22 | 1996-09-17 | Semiconductor Energy Lab Co Ltd | Insulated-gate electric field effect semiconductor device and its production |
KR100343307B1 (en) * | 1996-06-20 | 2002-08-22 | 가부시끼가이샤 도시바 | A method for manufacturing a thin film transistor |
KR100305527B1 (en) * | 1998-07-09 | 2001-11-01 | 니시무로 타이죠 | Method and apparatus for manufactu ring semiconductor device |
JP2002025906A (en) * | 2000-07-06 | 2002-01-25 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
CN109037076A (en) * | 2018-08-16 | 2018-12-18 | 北京大学深圳研究生院 | The method of metal oxide thin-film transistor preparation |
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