JPS6350031A - Trouble diagnostic for logic integrated circuit - Google Patents

Abstract

PURPOSE:To diagnose trouble quickly and precisely by detecting the input/output signal row of a functional block for a logic IC during operation in a noncontact manner, conducting logic simulation by an input signal row obtained and analyzing mismatch information with a noncontact output signal row. CONSTITUTION:A functional block 2 for an IC chip 1 during operation is irradiated with electron beams, and signal potential is observed 3, and converted 4 into logic information. Conversion timing is displayed by phase difference with a fundamental clock, and indicated by a general purpose computer. Relative movement is acquired from the absolute coordinates where mask information existing in the computer 7 is obtained, and the shifting of a sample base and a beam deflection angle are controlled, thus determining 5 an observation point. A general purpose tester 6 outputs test information memorized to the IC 1 according to timing control information. The computer 7 stores test information, the mask pattern information of the chip 1 and logic connection information, and has a program, from which the positional coordinates of a signal line are acquired, and a logic simulator. According to the constitution, troubles can be diagnosed rapidly by predetermined operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for diagnosing failures in logic integrated circuits, and in particular, diagnosing failures for each functional block in a logic integrated circuit using a non-contact tester. It is about how it can be done.

[Conventional technology]

Diagnosis of failures in logic integrated circuits is becoming increasingly difficult as the number of integrated elements increases.

As one effective method for solving the above problems, a technique has been developed that uses an electron beam or a laser beam to observe the signal potential of an internal element.

Examples of the above-mentioned technologies include 1, "online strobe SEM" (Japan Society for the Promotion of Science, 132nd Committee, 89th Research Meeting Materials, P. 19-25, November 9, 1980) or I, E, E, E. , “Design and Test of Computers” Volume 2, No. 5 (IEE
E, Design & Te5t of Co+np
uters.

Vol.2. No.5.1985.10. p, 74
-82).

In the above method, first, the logic operation of the integrated circuit to be observed is stopped at a certain point in time, and the chip surface of the integrated circuit at that time is observed using a strobe SEM (scanning electron microscope).

The SEM image obtained at this time is a top layer wiring image corresponding to the logical state of the integrated circuit at that time.

For example, the wiring with logic "0" appears to be shining, and the wiring with logic 111" is dark and invisible, so that it is possible to obtain a wiring image corresponding to the logic state of the integrated circuit.

Next, failure diagnosis can be performed by comparing the above-mentioned actually obtained wiring image with the expected wiring image reproduced by logic simulation and mask data.

[Problem that the invention seeks to solve]

In the conventional fault diagnosis method as described above, it is necessary to stop the logic operation at a certain point and inspect it, so there is a problem that it is not possible to detect defective logic operations related to timing such as delay time and hazards. There is. or,
As the logic scale of integrated circuits increases, the time required for logic simulation and the time required to reproduce the expected wiring image from the mask pattern also increases, resulting in a problem that the time required for fault diagnosis becomes extremely long. be.

The present invention has been made to solve the problems of the prior art as described above, and is capable of detecting timing-related malfunctions, requires less time for simulation, etc., and performs fault diagnosis quickly and accurately. It is an object of the present invention to provide a method for diagnosing failures of logic integrated circuits.

[Means to solve the problem]

The above objective is achieved as follows.

First, a non-contact tester detects an input signal string and an output signal string of a functional block included in a logic integrated circuit operating on an LSI tester or an actual device. An electron beam tester or a laser beam tester is used as the non-contact tester, and by irradiating a specific signal line of the functional block with an electron beam or laser beam, temporal changes in the signal of that part are observed.

Next, a logic simulation is performed using the input signal string detected by the non-contact tester as input data for the logic simulation, which has been set in advance to correspond to the normal function of the functional block.

Next, the output signal string obtained by the above logic simulation and the output signal string obtained by the non-contact tester are compared and verified. Fault diagnosis can be performed by analyzing the discrepancy data obtained through this comparison and verification.

[Effect]

As mentioned above, in the present invention, since the electron beam or laser beam is focused on a specific point,
The time change of the signal in that part can be easily determined.

In addition, logic simulation does not need to be performed on the entire integrated circuit, but only on the functional blocks to be tested, such as functional blocks that are expected to fail, so only a small portion can be tested. Therefore, the time required for fault diagnosis is shortened. Furthermore, since there is no need to reproduce the expected wiring image from the logic simulation results and mask pattern data, failure diagnosis can be easily and quickly performed from this point of view as well.

〔Example〕

FIG. 1 is an overall configuration diagram of an apparatus used in the failure diagnosis method of the present invention.

In FIG. 1, reference numeral 1 indicates a logic integrated circuit chip to be observed, and reference numeral 2 indicates a functional block included in the logic integrated circuit chip to be observed 1, and a failure diagnosis of this portion is performed.

Next, the electron beam tester 3 irradiates an observation point with an electron beam and detects the amount of secondary electrons generated there, thereby observing the signal potential at that part.

Next, the observation signal processing device 4 is a device that converts the waveform data of the observation point obtained by the electron beam tester 3 into logical information of "0"'1".The conversion timing is the same as the base clock. It is indicated by a phase difference and is usually instructed by a general-purpose computer 7, which will be described later.

Next, the position control device 5 is a device for determining the observation point by the electron beam tester 3, and determines the amount of movement of the sample stage and the deflection angle of the beam in order to determine the position to be irradiated with the electron beam. This is sent to the electron beam tester 3. The amount of movement at this time is a relative amount for moving the sample stage. Further, the observation position is usually given by absolute coordinates determined from mask data existing in the general-purpose computer 7. Therefore, the position control device 5 can also be said to be a device that calculates relative movement amount from absolute coordinates.

In addition, in order to convert between absolute coordinates and relative movement amount,
It is necessary to establish a correspondence between the coordinate system of the mask data and the coordinate system of the sample stage in advance.

Since this correspondence must be made manually, the position control device 5 is equipped with adjustment knobs for moving in the X and Y directions, and this correspondence is made by selecting at least three points.

Next, the general-purpose tester 6 is a device that supplies a test pattern for operating the observed logic integrated circuit 1, and has a test pattern memory and timing control information inside, and the data stored in the test pattern memory. is output to the outside according to timing control information. This output signal is applied to the observed logic integrated circuit 1 to be tested.

Note that the data in the test pattern memory is generated by the host general-purpose computer 7 and sent to the general-purpose tester 6 using a magnetic tape or a communication line.

Next, a large general-purpose computer 7 stores mask pattern information and logical connection information of the observed logic integrated circuit chip 1, and also has a program and a logic simulator for determining the position coordinates of signal lines. .

Next, FIG. 2 is a flowchart showing an example of the processing order for fault diagnosis in the apparatus of FIG. 1.

In FIG. 2, first, in process z1, a test pattern for operating the observed logic integrated circuit 1 is set in the general-purpose tester 6. This pattern is usually created in advance using a logic simulator such as the general-purpose computer 7. and,
By operating the general-purpose tester 6, a test pattern is supplied to the logic integrated circuit 1 to be observed. The observed logic integrated circuit 1 starts operating in accordance with this test pattern.

Next, in process 22, a functional block 2 for which a failure diagnosis is to be performed, a functional block 2 that is predicted to cause a failure if it collapses.
is selected, and the coordinate axis of one of its input or output signals is determined within the general-purpose computer 7.

The information is then sent to the position control device 5, thereby focusing the electron beam of the electron beam tester 3 on the position of the signal to be observed.

Next, in process 23, the electron beam tester 3 reproduces the time waveform of the signal level at the observation point by detecting the amount of secondary electrons generated at the observation point.

This is converted into a logic level by the observation signal processing device 4 and sent to the general-purpose computer 7.

The above processes 22 and 23 are performed on all input signals and output signals of the functional block to be observed. In process 24, it is determined whether all the above observations have been completed,
If the observation has not been completed, the process returns to step 22 and continues until all observations are completed.

Next, in process 25, input data for the description of the logic simulation of this functional block is edited using the input signal of the functional block 2 acquired by the general-purpose computer 7.

Next, in process 26, a logic simulation of the functional block is executed based on the above input data.

The logic simulation of process 26 will be described in detail below.

The general-purpose computer 7 stores the following items.

(1) The logic circuit of the functional block to be tested is expressed in a simulation circuit description language.

(2) Logic data of the input signal of the functional block to be tested (“
OII and “1”) column.

(3) A string of logical data of the output signal of the functional block to be tested.

(4) Logical simulation program.

Note that (2) and (3) above were obtained from data observed using an electron beam tester.

In the logical simulation of process 26, the above (2)
) and the circuit description in (1) above are input to operate the logic simulation program in (4) above. That is, the circuit (1) is operated in a simulated manner on a computer using the input signal (2).

As a result of this simulation run, a logical data string of the output signal of the circuit (1) can be obtained.

Next, in process 27, the observed data of the output signal obtained in process 23 and the output signal of the simulation value obtained in process 26 are compared and verified.

Next, in process 28, a failure diagnosis is performed by analyzing test patterns in which a mismatch occurs in the above matching results.

Note that if all of the above verification results match, it means that there was no failure.

In addition, in process 28, if the scale of the functional block is large when performing fault diagnosis, the functional block is further divided into a plurality of blocks, and the above processes 21 to 21 are performed on the functional block.
If step 28 is performed, failure diagnosis can be performed for each small circuit, making the failure diagnosis easier.

〔Effect of the invention〕

As described above, according to the present invention, it is not necessary to stop the operation of the logic integrated circuit for observation, and therefore it is possible to detect defective logic operations related to timing such as circuit delay time and hazards. Furthermore, there is no need to obtain the expected pattern of the wiring image. Furthermore, since logic simulation and fault diagnosis can be performed for each small functional block, it is only necessary to perform fault diagnosis for the functional blocks that require fault diagnosis, for example, the functional blocks that are expected to have a fault. Therefore, the time required for failure diagnosis is extremely shortened, and many excellent effects can be obtained, such as being able to accurately diagnose which part of the logic integrated circuit is at fault.

[Brief explanation of drawings]

FIG. 1 is an embodiment diagram showing the overall configuration of an apparatus for executing the failure diagnosis method of the present invention, and FIG. 2 is an embodiment diagram of the processing procedure of the failure diagnosis method of the present invention. <Explanation of symbols> 1...Logic integrated circuit chip to be observed 2...Functional block to be tested 3...Electron beam tester 4...Observation signal processing device 5...Position control device 6...General purpose Tester 7...General-purpose computer

Claims (1)

[Claims] 1. Detecting input signal sequences and output signal sequences of functional blocks included in a logic integrated circuit operating on a general-purpose LSI tester or an actual device with a non-contact tester,
A logic simulation is performed using the above input signal train as input data for a logic simulation that has been set in advance to correspond to the normal function of the above functional block, and the output signal train obtained by the logic simulation and the above non-contact tester are 1. A method for diagnosing a fault in a logic integrated circuit, characterized in that the fault is diagnosed by comparing and comparing output signal sequences obtained in the above.