JPS6328341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a resistive element in a semiconductor integrated circuit element.

Conventionally, methods for forming high resistance elements of polycrystalline silicon in semiconductor integrated circuit devices have been as follows. That is, a silicon oxide film is formed on a substrate, and a polycrystalline silicon layer is formed thereon by low pressure CVD. Next, impurity ions such as As ⁺ are implanted into this polycrystalline silicon layer.
Perform impurity doping. Next, ion implantation is performed to recover the polycrystalline silicon in which crystal defects have occurred, and annealing is performed by heat treatment in order to activate the implanted ions. A resistance element is formed on a substrate using such a polycrystalline silicon layer.

With the conventional method as above, the sheet resistance value can be reduced from 10 to several
When forming a high resistance element of 10 (GΩ/□), it is extremely difficult to precisely control the resistance value.
There was a problem with poor reproducibility. for example,
As shown in Figure 1, the objective value of the sheet resistance value is 10 to a number.
10 (GΩ/□), when comparing the sheet resistance value of the final high-resistance element among four lots of integrated circuit elements manufactured with the same ion implantation amount per unit area, it is ±20 within the same lot. Although the variation was ~30%, there was a variation of up to three orders of magnitude between different lots. In such a situation, the sheet resistance value of the element will vary greatly due to differences in manufacturing lots during mass production, resulting in the problem of not being able to stably supply products with constant performance. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a high resistance element that can improve the problems of the prior art as described above, and can control the resistance value with high accuracy and has good reproducibility.

In the present invention, an insulating film is formed on a substrate, and a polycrystalline silicon film is deposited on the insulating film by low pressure CVD. Thereafter, the polycrystalline silicon film is first heat-treated and annealed, and then impurity ions are implanted. Next, heat treatment is performed again to recover lattice defects in polycrystalline silicon and to activate impurity ions. By employing a manufacturing process with such a configuration, a high resistance element that is easy to control and has a resistance value with good reproducibility can be formed on the insulating film.

This is based on the following considerations. That is, as shown in Figure 2, the crystal grain size in polycrystalline silicon depends on the dose of impurity ion implantation, especially
10 ¹³ (ions/cm ² ) level with almost no change 10 ¹⁵
(ions/cm ² ) or more, a remarkable change in particle size appears.

Furthermore, when forming a polycrystalline silicon film on an insulating film, conventionally, a low pressure CVD method is generally used. At this time, the flow rate of monosilane gas, temperature, degree of vacuum, etc. are controlled in the vapor phase growth apparatus in which the element is placed. However, the conditions change slightly due to dirt in the equipment, minute leaks in the atmosphere, etc., and the estimated average crystal grain size changes each time.
Due to differences in production lots, variations in average crystal grain size occur. Controlling this variation is extremely difficult. Moreover, this variation in average crystal grain size between production lots is considered to be the main cause of variation in final resistance value. In other words, the impurity ions implanted into the polycrystalline silicon film are activated by replacing Si atoms at the same time as the crystal grains grow through subsequent heat treatment, but the shape of the crystal boundary surface of the polycrystalline silicon changes. As a result, the degree of activation is greatly affected, and crystal grain growth occurs simultaneously, resulting in an unstable situation. Therefore, when the crystal grain size differs, the structure of the crystal boundary surface also differs, and in the end,
This will also affect the resistance value. However, if heat treatment is performed before implanting impurities, the crystal grains will grow and the crystal grain size will become uniform as a whole. If impurity ions are then implanted and annealed again, the impurity ions can be activated in a safe state because the crystal boundary structure is simplified and crystal grains no longer grow. If the doped impurities can be activated in a stable manner at all times, the resistance value can be easily controlled and a high resistance element with good reproducibility can be obtained.

Next, one embodiment of the present invention will be described in detail using the drawings. First, as shown in FIG. 3a, a semiconductor substrate 1 has functional elements such as transistors formed in a part thereof.
An insulating film 2 made of a thermally oxidized silicon film or the like having a thickness of about 7500 Å is formed thereon by, for example, a thermal oxidation method. Next, on this insulating film 2, a polycrystalline silicon film 3 is uniformly deposited to a thickness of about 3000 Å in monosilane gas at about 620° C. using, for example, a low pressure CVD method. Next, on this polycrystalline silicon layer 3, for example, a CVD
A silicon oxide film 4 having a thickness of about 3000 Å is deposited by a method. Then, the polycrystalline silicon film 3 is heat-treated at 900° C. for 10 minutes to perform pre-annealing. By this pre-annealing, as described above, crystal grains are grown and the grain sizes are made uniform. Silicon oxide film 4
is deposited to prevent the inert gas N2 used as an atmosphere and surrounding impurities from diffusing into the polycrystalline silicon film 3 and changing the resistance value during this pre-annealing. . The temperature and time of pre-annealing are determined to prevent re-diffusion of sources and drains in functional elements such as transistors formed on the silicon substrate 1.
900℃, 10 minutes is optimal. Next, the silicon oxide film 4 is removed in ammonium fluoride to expose the surface of the polycrystalline silicon film 3.
As ions are implanted at 100 KV and 3×10 ¹³ (ions/cm ² ). The target value of sheet resistance value is 2 to 5×10 ⁹ (Ω/
□). Then, by photolithography, unnecessary portions of the polycrystalline silicon layer 3 are removed by etching using nitric acid or the like to form a predetermined shape. In this way, the high resistance element portion 5 is formed as shown in FIG. 3b. Here, an insulating film 6 made of a silicon oxide film is deposited over the entire surface again by the CVD method. Next, annealing is performed again at 900°C for 10 minutes in an inert gas such as N2. At this time, impurity ions are activated and crystal defects are also recovered. However, grain growth does not occur again. Also, at this time, the insulating film 6
is integrated with the insulating film 2 on the surface of the substrate.

Next, as shown in FIG. 3c, contact holes 7 are formed in the insulating film 6 at both ends of the high resistance element section 5 by etching. In this portion, a diffusion layer 8 is formed by diffusing As at a high concentration for ohmic contact. Next, electrode 9 is formed by depositing Al. The above-mentioned diffusion into the contact hole is caused by the Al electrode 9
This is to improve the electrical connection between the high-resistance element section 5 and the high-resistance element section 5. The high resistance element section 5 is connected to the Al electrode 9,
It is connected to other element parts on the substrate.

Four lots of integrated circuit devices having high resistance elements were manufactured using the above process, and the sheet resistance values (Ω/□) were compared. As shown in Figure 4, the resistance value was 1×10 ⁹ to 5×10 ⁹ (Ω/□), which greatly reduces the conventional 3-digit variation to 1
It is now possible to reduce the number to within an order of magnitude. As described above, by the manufacturing method of the present invention, a high-resistance element with good controllability and reproducibility of resistance value can be formed. Moreover, since the process is simple, it is suitable for mass production and has great effects.

In the above example, pre-annealing was performed at 900℃10
Although the temperature is not limited to this, if the post-annealing temperature is 1000°C, the pre-annealing temperature is preferably 1000°C.

Further, the silicon substrate used in this example may be an insulating substrate, and can also be applied to SOS technology. Further, polycrystalline silicon doped with impurities at a high concentration may be used for connection between the high resistance element and other functional elements. In this case, the part to be made into a high resistance element and the connection part are simultaneously formed from the polycrystalline silicon layer, and the connection part is first coated with SiO ₂ etc. to form the high resistance element using the procedure described above. This high-resistance element portion is covered with a SiO ₂ film or the like, and impurity ions are implanted at a high concentration into the connection portion. If you do this,
No Al electrodes are required, and no diffusion is required for ohmic contact. Furthermore, pre-annealed polycrystalline silicon layers can be used not only for the purpose of manufacturing high-resistance elements, but also for forming low-resistance connecting parts, and in this case, it is possible to control the resistance value with high precision. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the conventional relationship between dose amount and sheet resistance value, FIG. 2 is a diagram showing the relationship between dose amount and grain size, and FIGS. 3 a to c are an example of the present invention. FIG. 4 is a schematic cross-sectional view of the manufacturing process of FIG. 4, and is a diagram showing the relationship between dose amount and sheet resistance value according to the present invention. In the figure, 1... semiconductor substrate, 2, 4, 6... insulating film, 3
...Polycrystalline silicon film, 5...High resistance element section, 7
...Contact hole, 8...Diffusion layer, 9...Electrode.

Claims (1)

[Claims] 1. A step of forming a polycrystalline silicon film on an insulating material, a step of depositing an insulating film on the polycrystalline silicon film, and a step of covering the polycrystalline silicon film with the insulating film. The present invention is characterized by comprising the steps of: pre-annealing the polycrystalline silicon film in a pre-annealed state; removing the insulating film and doping the polycrystalline silicon film with a predetermined impurity; and annealing the polycrystalline silicon film doped with the impurity. A method for manufacturing a semiconductor resistance element. 2. When doping a polycrystalline silicon film with a predetermined impurity, cover the area other than the part where the resistance element is to be formed with a second insulating film, and use this second insulating film as a mask to dope the impurity at a low concentration. After removing this second insulating film, a third insulating film is formed on the part where the resistor element is to be formed, and using this third insulating film as a mask, the impurity is highly concentrated in the part where the connection wiring is to be formed. 2. The method of manufacturing a semiconductor resistance element according to claim 1, wherein the semiconductor resistance element is doped at a high concentration.