JPS63283166A - Gate electrode structure - Google Patents

Abstract

PURPOSE:To eliminate the deterioration of gate breakdown strength characteristic even if it is heat treated at a high temperature by forming an amorphous carbon layer between a polysilicon layer for forming a gate electrode and a high melting point metal layer or a high melting point metal silicide layer. CONSTITUTION:A gate electrode structure is formed of a polysilicon layer 43 formed on an Si oxide film 41, an amorphous carbon layer 45 formed on the layer 43, and an upper layer 49 of a high melting point metal layer or a high melting point metal silicide layer formed on the layer 45. When thus constructed, even if it is heat treated at a high temperature, a reaction of the high melting point metal or high melting point metal silicide, a reaction with a doped polysilicon, and a diffusion of metal element contained in the high melting point metal or high melting point metal silicide in the polysilicon layer can be prevented. Thus, even if a low resistance gate electrode is heat treated at a high temperature, its gate breakdown strength characteristic is not deteriorated.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is a MOS (metal-Ox) using silicon.
ide-Semiconductor) type semiconductor devices, especially 51M0 SFET (Field Ef
The present invention relates to the gate electrode structure of the Fect Transistor.

(Prior Art) Phosphorus-doped polysilicon (hereinafter sometimes referred to as polysilicon gate) has been commonly used as a gate electrode of a silicon MOS field effect transistor. On the other hand, the degree of integration of semiconductor devices is increasing more and more, and along with this, the wiring width of the gate electrode of the FET provided in this device is becoming increasingly finer and the wiring length is becoming longer and longer. In such a situation, signal delay due to the high resistance value of the polysilicon gate becomes a problem, and therefore a gate electrode wiring metal with lower resistance is required.

Although the gate electrode has a lower resistance than polysilicon, the electrical characteristics of silicon MOSFETs constructed using this are equivalent to those of EETs with polysilicon gates, and the manufacturing process is similar to that of polysilicon gates. A high melting point metal polycide gate electrode, in which a high melting point metal silicide is laminated on polysilicon, has been proposed as a gate electrode compatible with the above-mentioned polysilicon, and some have been put into practical use.

FIG. 2 is a sectional view schematically showing the structure of a Ti (titanium) polycide gate electrode, which is a type of high melting point metal polycide gate electrode as described above. In Figure 2, 1
1 is a Ti silicide (TiS i x ) layer, 13 is a polysilicon layer, 15 is a gate binding film, 17 is an n+ diffusion layer, 19 is a field oxide film, and 21 is a silicon substrate.

This T1 polycide gate electrode exhibits the lowest resistivity among high-melting point metal polycide gate electrodes, and is expected to be put into practical use.
8: There was a problem with its heat resistance, as problems were caused by heat treatment performed during the silicon MOSFET manufacturing process, such as an annealing process after ion implantation. The results of a subsequent investigation into the heat resistance of Ti silicide can be found in, for example, the literature (Journal Electrochemical Science (J.

Electrochemical 5ociety)
133 [12] P, 2621-2625).

Silicon MOSFE with T1 polycide gate electrode
T is formed by the following manufacturing process. After selectively oxidizing the P-type silicon substrate 21 to form an isolation oxide film (field oxide film) 19, a silicon oxide film (gate binding film) 15 of about 20 OA is formed by thermal oxidation. Next, on the substrate including this silicon oxide film 15, using the CVD method,
A polysilicon layer is formed to a thickness of about 2500 to 3000 A. Next, this polysilicon layer is doped with p(l-non) by thermal diffusion to make this layer%n+ polysilicon layer. A Ti layer with a thickness of about 50 OA is formed on the polysilicon layer by a suitable method, and heat treatment is performed at a temperature of 600 to 900°C for about 30 minutes in an inert gas atmosphere to separate Ti and Si. React, Ti
Next, photolithography and dry etching techniques were used to form the TiSi2 layer and the n÷
The polysilicon layer is processed into a gate electrode shape to obtain a T1 polycide electrode structure (portions 11 and 13 in FIG. 2).

Next, As (arsenic) is implanted into a predetermined portion of the silicon substrate by ion implantation to form an n+ diffusion layer to obtain a source train region 17.

In the above-mentioned literature, a silicon MOS capacitor is manufactured by a process similar to the process up to the formation of the source train region in the above-mentioned manufacturing process, and the leakage current of this capacitor is reduced by changing the heat treatment temperature for this capacitor. Measuring. According to the measurement results, the leakage current increases when the heat treatment temperature is 800 to 900'C. The reason for the increase in leakage current is that Ti in the Ti silicide layer passes through the underlying polysilicon layer due to heat treatment, destroys the underlying oxide film, and short-circuits the capacitor.

Further, the silicon MOSFET shown in FIG. 2 can also be obtained by the manufacturing process described below.

Oxide film +9. +5 and phosphorus doped polysilicon layer 13
A method in which Ti polycide formation after forming 2 is performed by sputtering using a TlSix alloy target, simultaneous sputtering using each target of T1 and Si, or using a suitable method such as electron beam evaporation method. It is.

According to such a method, unlike the method described above, it is possible to reduce the reaction between the polysilicon layer and the TiSix layer. However, according to experiments conducted by the inventor of this application, even if a MOSFET is formed in this way, if it is heat-treated at a temperature of 900°C or higher in an inert atmosphere, the gate electrode and silicon substrate will be separated. It was found that the leakage current between the two increased, making it impossible to use it as a MOSFET. Roughly speaking, when this MOS FET is heat-treated in an oxidizing atmosphere, a more severe increase in leakage current is observed than the increase in leakage current in an inert atmosphere when heat-treated at the same temperature as mentioned above. Ta.

By the way, as a method for preventing the increase in leakage current and deterioration of gate breakdown voltage due to the problem of heat resistance ゛i of Ti silicide, for example, Japanese Patent Laid-Open No. 61-10585
Some of them are disclosed in Publication No. 6. FIG. 3 shows a gate electrode structure specifically showing the method disclosed in this publication. This method consists of polysilicon layer 13 and T i
A feature is that a silicon layer 23 is provided between the SIX layer 11 and the silicon layer 23 as a diffusion prevention layer of T1. This silicon layer 23 is formed using a sputtering method, and a TiSix layer 11 is deposited on this silicon layer 23 using a sputtering method. According to this publication, the silicon layer t400
It is said that by forming the film with a thickness of ~600A, deterioration of gate breakdown voltage can be prevented. However, according to experiments as described by the inventor of this application, when a structure as shown in FIG. 3 is used in which a polysilicon layer and a Ti silicide layer are interposed on a silicon layer, However, it was confirmed that the gate breakdown voltage deteriorates due to heat treatment in an inert atmosphere and heat treatment in an oxidizing atmosphere.

This experimental method and experimental results will be briefly explained.

A P-type Si substrate with a specific resistance of 4 Ωcm was thermally oxidized to form an oxide film of 300 A, and then a polysilicon layer with a thickness of 1700 Å was formed on this Si substrate by the CVD method. This polysilicon layer is doped with P (phosphorus) using POCff3, and the phosphorus concentration of this layer is 1 x 1020c.
It was set as m-3. A large number of such wafers are prepared. Next, using a sputtering method, the phosphorus-doped polysilicon layer of these wafers is sputtered.
00, 300, and 600 A, respectively, to form a plurality of sample wafers having different silicon layer thicknesses. Thereafter, a TiSix (x=2.5) layer was placed on the silicon layer of each sample wafer using the same sputtering equipment. Each film was formed with a film thickness of 250 OA. Next, these sample wafers were
A large number of capacitors (MOS capacitors) each having an electrode area of 2 were formed.

Next, each sample wafer was processed in an Ar (argon) atmosphere.
Or 02 (oxygen) atmosphere and mild treatment! 800,8
50,900,950. or 1000℃, and
The heat treatment was performed by assigning each heat treatment condition to a treatment time IFi of 60 minutes.

The gate breakdown voltage of 50 MOS capacitors of each heat-treated sample wafer was measured, and the average value was taken as the gate breakdown voltage.

The results of this experiment were as follows.

In heat treatment performed at a temperature of 800°C in an Ar atmosphere, the gate breakdown voltage was 7.5 MV/cm regardless of the thickness of the silicon layer.
It was about cm. However, the temperature of heat treatment is 1t900"c
In the above case, the gate breakdown voltage after heat treatment at a temperature of 800°C and in an Ar atmosphere is /2 to 1/6, regardless of the thickness of the silicon layer in both Ar and 02 atmospheres.
Therefore, it was not possible to prevent the gate breakdown voltage from deteriorating. However, it was found that the thicker the silicon layer, the slower the deterioration of the gate withstand voltage, and the degree of deterioration was more severe after heat treatment in an 02 atmosphere than after heat treatment in an Ar atmosphere.

(Problems to be Solved by the Invention) As described above, T1 polycide formation is performed by sputtering using a TiSix alloy target, simultaneous sputtering using Ti and Sl targets, or electron beam evaporation. Regardless of whether it is a gate electrode obtained by using a polycide film or a gate electrode constructed by providing a silicon layer between a polysilicon layer and a Ti5IX layer, conventional high-melting point metal polycide gate electrodes are defective. When heat treatment is performed at high temperatures in an active gas atmosphere or an oxidizing atmosphere, there is a problem in that leakage current between the gate electrode and the substrate increases, that is, gate breakdown voltage deteriorates.

If we estimate the causes of such problems, we can think of the following.

The reason why the gate breakdown voltage deteriorates in the conventional gate electrode structure shown in Figure 2 is that Ti in the Ti silicide diffuses into the polysilicon due to heat treatment and reaches the gate oxide film, reducing this oxide film and causing oxidation. This is because the film no longer functions as an insulating film, resulting in a short circuit between the gate electrode and the substrate.

Furthermore, as in the gate electrode structure disclosed in Japanese Patent Application Laid-Open No. 61105856 described with reference to FIG. In the case of an electrode structure, while the silicon layer is an amorphous layer, this silicon layer acts as a layer to prevent the diffusion of T1, but when this silicon layer is crystallized by heat treatment, Ti diffusion occurs through its grain boundaries. As a result, the gate breakdown voltage deteriorates.

Therefore, the conventional structure of high melting point metal polycide gate is
This method could not be applied to conventional semiconductor device manufacturing processes that include many heat treatment steps.

An object of the present invention is to solve the above-mentioned problems and to provide a gate electrode with low resistivity, which does not cause deterioration of gate breakdown voltage characteristics even after being subjected to high-temperature heat treatment in the manufacturing process of semiconductor device 1. No faith! The object of the present invention is to provide a gate electrode structure with high I-coupling.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, in the gate electrode structure of a silicon MOS semiconductor device, the gate electrode is made of polysilicon formed on a silicon oxide film. an amorphous carbon layer formed on this polysilicon layer, and a high melting point metal layer or a high melting point metal silicide layer formed on this amorphous carbon layer.

(Function) According to the gate electrode structure of the present invention, an amorphous carbon layer is provided between the polysilicon layer and the high melting point metal layer or the high melting point metal silicide layer.

The amorphous carbon film has a crystallization (graphitization) temperature of 1000'C or higher (Inorganic Chemistry Complete Book X-2P,
252 (Maruzen Co., Ltd., 1965), the heat treatment temperature (1
000℃ or less), and amorphous carbon and a high melting point metal such as Ti or S
Since the reaction salinity with i is known to be very high,
It is considered that compounds such as TiC, SiC, etc. are not generated at the temperature of the heat treatment step during the manufacturing process as described above. Therefore, both the interface between the high melting point metal layer or the high melting point metal silicide layer and the amorphous carbon layer, and the interface between the polysilicon layer and the amorphous carbon layer are considered to be chemically stable. Therefore, Ti is blocked by the amorphous carbon layer and cannot diffuse into layers below this layer.

(Example) Hereinafter, an example of the gate electrode structure of the present invention will be described with reference to FIG. FIG. 1 is a sectional view schematically showing a silicon MOSFET having the gate electrode structure of the present invention. It should be noted that this figure is merely a schematic representation to facilitate understanding of the present invention, and therefore, it should be understood that the present invention is not limited to the illustrated example.

Guni Σ! The gate electrode structure of the present invention includes a polysilicon layer 43 formed on a silicon oxide film 41, an amorphous carbon layer 45 formed on this polysilicon layer 43, and a polysilicon layer 45 formed on this amorphous carbon layer 45. The structure includes an upper layer 49 of a high melting point metal layer or a high melting point metal silicide layer.

In such a structure, the conductivity type of the polysilicon layer 43 can be set to a suitable conductivity type depending on whether the channel of the MOSFET is n or p. Further, the conductivity type of the amorphous carbon layer 47 is preferably changed according to the conductivity type of the polysilicon layer 43, such as p type when the polysilicon layer 43 is p+.

Further, the gate electrode structure of the present invention is designed to solve the problems caused by heat treatment when a refractory metal or a refractory metal silicide is directly laminated on a polysilicon layer. Therefore, it is known that the gate breakdown voltage deteriorates due to oxidation treatment not only when the upper layer 49 shown in FIG. 1 is a Ti silicide layer but also when the polysilicon layer in contact with the silicide is thin. (tungsten) silicide, Mo (molybuken) silicide, Z
Even when using r (zirconium) silicide, Go (cobalt) silicide, etc., the amorphous carbon layer effectively acts as a diffusion prevention layer for each metal element.
9! Even when a high melting point metal layer such as Ti, W, Mo, Zr, or Co is used, the amorphous carbon layer 45 is effective as a layer for blocking the wrinkling reaction that occurs between the polysilicon 43 and the high melting point metal layer 49. to work.

Gate electrode restraint method Below, in order to deepen the understanding of the gate electrode structure of this invention,
An example of the manufacturing method of the silicon MO8FET shown in FIG. 1 will be explained using an example in which the upper layer 49 is a kind of Ti silicide of high melting point metal sisosite.

For example, a p-type silicon substrate 31 is prepared. This silicon substrate 31 is selectively oxidized to form an isolation oxide film (field oxide film) 33, and thermally oxidized to a predetermined film thickness, e.g.
00-200A silicon oxide film (gate insulating film) 41
Next, on the substrate 31 including this silicon oxide film 41, a film with a thickness of 300 to 200
A 0A polysilicon layer is formed, and then this polysilicon layer is doped with P (phosphorus) by thermal diffusion using POCl2 to a concentration of about 2 x 1020/Cm3, and this layer is made of n+ polysilicon. Next, a phosphorus-doped amorphous carbon layer is formed to have a thickness of 10 to 1000 Å using PH3 and C2H2 as raw material gases by plasma CVD as a silicon layer. Note that the method for forming this amorphous carbon layer is not limited to this example (1. If the CVD method is used similarly to this example, the raw material gas may be any other suitable method containing carbon and hydrogen. It may also be a suitable gas containing fluorine or chlorine in addition to carbon and hydrogen.

Furthermore, instead of the plasma CVD method, a sputtering method or an electron beam evaporation method can also be used.

Next, TiSix was formed as a high melting point metal silicide layer by sputtering using an alloy target of T1 and 81.
(x=2.0~3.0) The film thickness of the layer is several 100 to several 1
000A.

Next, a resist pattern with a predetermined shape is formed using photolithography, and using the remaining resist portion as a mask, the TiS I The silicon layer is processed into a gate electrode shape to obtain the gate electrode structure of the present invention (indicated by 41 in FIG. 1).
~The part indicated by 49. ).

Next, using this gate electrode as a mask, As (arsenic) is implanted into a predetermined portion of the silicon substrate by ion implantation to form an n+ diffusion layer 51 that will become a source and train region. Then, heat treatment is performed for about 1 hour at a temperature of 800 to 1000"C in an inert gas atmosphere using an electric furnace. Through this heat treatment, As in the As-doped region 51 is activated and becomes n+ doped silicon. Furthermore, the Ti silicide layer 49 is crystallized and becomes a layer exhibiting a low specific resistance of about 20 uΩcm.

In the gate electrode structure of the present invention, the film thickness of the amorphous carbon layer 45 is tioOA, and the gate length is %1u.
Assuming that the m gate wiring length is 1 cm and the resistivity of the Ti silicide layer 49 is 3000 A and its resistivity is 20 μΩcm, the wiring resistance of this gate electrode is 6.7Ω, whereas the T1 silicide and poly The resistance of the amorphous carbon layer between silicon and silicon is 0. ]Ω, and it can be seen that the increase in resistance due to the presence of this amorphous carbon layer can be ignored in normal VLSI.

As described above, according to the gate electrode structure of the present invention, since the amorphous carbon layer 45 is provided between the polysilicon layer 43 and the high melting point metal layer or the high melting point metal silicide layer 49, the above-mentioned problems in the VLSI manufacturing process can be avoided. The advantage is that the gate breakdown voltage does not deteriorate even when subjected to such heat treatment.

In order to confirm the effects of this invention, experiments as described below were conducted.

A plurality of sample wafers with gate oxide films having a thickness of 30 OA were prepared. Polysilicon was formed on these sample wafers to a film thickness of 170 OA. Next, phosphorus was added to the polysilicon layer of these sample wafers at 1 x 102
These sample wafers doped at a concentration of 0 cm-3 were then divided into three groups, first to third, and
Pz3 in 2H2! An amorphous carbon layer with a thickness of 100A was formed on the polysilicon of the wafers of the first group, and an amorphous carbon layer of 30A was formed on the polysilicon of the wafers of the second group by plasma CVD using a mixture of 1% in flow rate ratio as a raw material gas.
All sample wafers in the first, second and third groups TiSix (x=2.5) was formed to a thickness of 250 OA on the amorphous carbon layer by sputtering using an alloy target of T1 and 81. Thereafter, a gate electrode having an electrode area of 10 mm2 was formed using a photoetching technique and a dry etching method to form a MOS capacitor.

After measuring the gate breakdown voltage of each of the M'OS capacitors obtained in this way,
The 0th order was heat treated for 60 minutes in an Ar atmosphere at a temperature of 0°C.
The gate breakdown voltage of each capacitor after heat treatment was measured. When comparing the gate breakdown voltage before and after heat treatment, no deterioration in gate breakdown voltage was observed at each level. From this, it can be seen that according to the gate electrode structure of the present invention, there is no deterioration in gate breakdown voltage due to heat treatment that may be performed during the VLSI manufacturing process.

(Effects of the Invention) As is clear from the above description, according to the present invention, silicon MO8 having a laminated structure of a doped polysilicon layer and a high melting point metal layer or a high melting point metal silicide layer.
In the gate electrode structure of an FET, an amorphous carbon layer is provided between a doped polysilicon layer and a high melting point metal layer or a high melting point metal silicide layer. Therefore, even if heat treatment is performed at a high temperature, there will be a reaction between the refractory metal or refractory metal silicide and doped polysilicon, and a reaction of the metal element contained in the refractory metal or refractory metal silicide into the polysilicon layer. It will be possible to stop the spread. Furthermore, a gate electrode can be obtained which has a lower resistance than a conventional polysilicon gate but has the same threshold voltage as that of the polysilicon gate.

Therefore, it is a gate electrode with low resistivity, and V
It is possible to provide a highly reliable gate electrode structure in which the gate breakdown voltage characteristic (1) does not deteriorate even when subjected to high-temperature heat treatment performed during the manufacturing process of LSI.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view schematically showing a gate electrode structure according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an example of a conventional gate electrode structure, and FIG. 3 is a cross-sectional view of a conventional gate electrode structure. It is a sectional view showing other examples. 31...Silicon substrate, 33-...Field oxide film 41...Silicon oxide film (gate oxide film) 43-
...Polysilicon layer 45...Amorphous carbon layer 49...Upper layer (high melting point metal layer or high melting point metal silicide layer) 51-n+ diffusion layer (source/train region). Patent Applicant: Oki Electric Industry Co., Ltd. 31 Niji 1-no-contact substrate 33: Field oxide film 4 Silicon oxide film (gate oxide @) 43: Polysilicon layer 45 Nearmorphous carbon layer 49: Upper layer (high melting point total layer or high melting point layer) (metal sinosite layer) 51: n+ diffusion layer (source/train region) Cross-sectional view showing the gate electrode structure of the present invention Figure 1 Cross-sectional view showing an example of the conventional gate electrode structure Figure 2 1γ Conventional gate electrode structure Fig. 3 is a sectional view showing another example of

Claims (1)

[Claims] (1) In the gate electrode structure of a silicon MOS semiconductor device, a polysilicon layer formed on a silicon oxide film, an amorphous carbon layer formed on the polysilicon layer, and a high carbon layer formed on the amorphous carbon layer A gate electrode structure comprising a melting point metal layer or a high melting point metal silicide layer.