JPS63232456A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a bipolar transistor and a C0M5 transistor.

[Conventional technology]

Conventionally, an N-type epitaxial layer is grown on a P-type semiconductor substrate, and a bipolar transistor and a C
A semiconductor device forming a MOS transistor has a structure in which the impurity concentration of the bipolar transistor forming region is determined by the N-type epitaxial layer 2, as shown in FIG. 5, for example.

The manufacturing method will be explained below using FIG. 6.

First, as shown in FIG. 6(a), a thin oxide film 9 is formed on the N-type epitaxial layer 2 on the P-type semiconductor substrate 1 by thermal oxidation treatment, and a portion corresponding to a portion where an N-channel MOS transistor is to be formed is formed. A mask 10 made of photoresist with holes formed by photolithography is formed, and this mask 1
A P+ type well layer 5 is formed by implanting boron ions using 0. The impurity concentration of this boron is determined according to the impurity concentration of the N-type epitaxial layer 2 so that it can be connected to the P'' type buried layer 4 in the heat treatment in the subsequent process, and so as not to deteriorate the back gate characteristics of the MOS transistor. Mold embedding N
The impurity concentration was controlled to be lower than the impurity concentration in No. 4.

Next, as shown in FIG. 6(b), after removing the mask 10, a mask 10A made of photoresist with holes formed by photolithography in the portion corresponding to the portion where the P-channel MOS transistor is to be formed is formed. An N'''' type well layer 7 is formed by ion implantation. The impurity concentration of this phosphorus was also controlled to a value lower than the impurity concentration of the N+ type buried layer 3 in accordance with the impurity concentration of the N type epitaxial layer 2 so as not to deteriorate the short channel effect, back gate characteristics, etc.

According to such a manufacturing method, the impurity concentration of the bipolar transistor forming region is determined by the N-type epitaxial layer 2.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, an N-channel MO
S) Transistor and P-channel MO3) Although consideration has been given to the characteristics of the transistor, the impurity concentration in the bipolar transistor formation region is determined by the impurity concentration in the N-type epitaxial layer, which adversely affects the characteristics of the bipolar transistor. There were many cases. For example, if the impurity concentration of the N-type epitaxial layer is low, problems such as deterioration of the frequency characteristics of the bipolar transistor and increase in collector saturation resistance may occur, resulting in a composite circuit of a bipolar transistor and a CMOS (CMOS) transistor. This was causing the speed to slow down.

One way to solve these problems is to increase the impurity concentration in the N-type epitaxial layer itself, but if the N-type epitaxial layer is as thin as 2 μm or less, the impurity concentration is controlled so that the resistivity is 1Ω.1 or less. It is difficult to do this, and there is a problem in that it increases the variation in concentration.

An object of the present invention is to provide a semiconductor device having a bipolar transistor with excellent frequency characteristics and low collector saturation resistance, and a CMOS transistor.

[Means for solving problems]

The semiconductor device of the present invention has an N
Bipolar transistor and CMO type epitaxial layer
This is a semiconductor device in which an S transistor is formed, and the impurity concentration in a bipolar transistor formation region is equal to or higher than the impurity concentration in a P channel MoS transistor formation region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, an N+ type buried layer 3 and a P'' type buried layer 4.4A are formed on a P type semiconductor substrate 1, and an N+ type buried layer 4.4A is formed on the P type semiconductor substrate 1.
A type epitaxial layer 2A is formed, and a P+ type well layer 5 and a P+ type layer 6 for insulation isolation are formed in this N+ type epitaxial layer 2A. An N-channel MOS transistor (not shown) is formed in this P1 type well layer 5, and a P1 type well layer 5 is formed in the N+ type epitaxial layer 2A.
Channel MO3) A P-channel MOS transistor and a bipolar transistor (not shown) are formed in the transistor and bipolar transistor forming regions, respectively.

In the first embodiment configured in this manner, the bipolar transistor is formed in the N'' type epitaxial layer having the same high impurity concentration as the P channel MOS transistor formation region, so the frequency characteristics are good. Collector saturation resistance also becomes small.

FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 2(a), a layer with a thickness of 1.5 μm and a specific resistance of 1Ω is placed on the N+ type buried layer 3 and the P+ type buried layer 4.4A buried in advance of the P type semiconductor substrate/board 1.・After growing an N-type epitaxial layer 2 with a thickness of 50 cm, a thin oxide Jl of 500 cm is applied to its surface by thermal oxidation treatment. form 9 and N
Phosphorus, which is an impurity of the same type as the type epitaxial layer, is ion-implanted into the entire surface.

Next, as shown in FIG. 2(b), a mask IOB made of photoresist is formed in which a portion corresponding to a portion where an N-channel MOS transistor is to be formed is opened by photolithography, and then boron ions are implanted.

The ion-implanted phosphorus and boron are diffused by heat treatment in a subsequent step to form a P+ type well layer 5 and an N'' type well layer 2A having a uniform impurity concentration.

Incidentally, the impurity concentration of phosphorus needs to be set within a range such that the short channel effect can be suppressed and furthermore, the threshold voltage of the P channel MOS transistor can be controlled.

Normally, the Linnean obtuse concentration to satisfy such characteristics is limited to about 5×10 12 ion implantation dose when the resistivity of the N-type epitaxial layer 2 is 1Ω·1. Therefore, the impurity concentration of the bipolar transistor forming region is also the same as that of the P channel MOS transistor forming region. Furthermore, in the N-channel MOS transistor formation region, the impurity concentration during boron ion implantation can be increased by the amount of Linnean obtuse ions implanted, and the characteristics will not be affected at all.

Next, a P+ type layer 6 for insulation isolation is formed by ion implantation, and then transistors are formed in each transistor forming region by conventional techniques, thereby completing the semiconductor device shown in FIG. 1.

FIG. 3 is a cross-sectional view of the second embodiment of the present invention, which differs from the first embodiment shown in FIG. It is formed at a higher concentration than the impurity concentration.

That is, in FIG. 3, a P+ type well layer 5 and an N+ type well layer 8 are formed in an N+ type epitaxial layer 2A formed on a P type semiconductor substrate 1, and each well layer has an N channel MOS. A transistor and a bipolar transistor (not shown) are formed. Further, a P channel MOS transistor (not shown) is formed in the P channel formation region of the N+ type epitaxial layer 2A.

Similarly to the first embodiment, the second embodiment configured in this manner has the advantage that the frequency characteristics of the bipolar transistor are good and the collector saturation resistance is further reduced.

FIG. 4 is a sectional view for explaining the manufacturing method of the second embodiment of the present invention. Figure 1(a).

As described in (b), the N+ type epitaxial layer 2A and the P+ type well N6 are formed on the P type semiconductor substrate 1.

Next, as shown in FIG. 4, after forming a mask 10C made of photoresist in which a portion corresponding to the portion where the bipolar transistor is to be formed is opened by photolithography,
Phosphorus ions are implanted and heat treated to form an N+ type well layer 8.

In the first embodiment, phosphorus was only injected into the entire surface of the N-type epitaxial layer, whereas in the second embodiment, phosphorus is again injected into the bipolar transistor forming region. Therefore, unlike the first embodiment, the impurity concentration is not limited by the characteristics of the P-channel MOS transistor.

Thereafter, a conventional process is performed to form a transistor in the P+ type layer 6 for insulation isolation and each transistor formation region, thereby completing the semiconductor device shown in FIG. 3.

〔Effect of the invention〕

As explained above, the present invention provides a bipolar transistor with excellent frequency characteristics and low collector saturation resistance by making the impurity concentration of the bipolar transistor formation region equal to or higher than the impurity concentration of the P channel MOS transistor formation region. A semiconductor device having a CMOS transistor is obtained.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
, (b) is a sectional view of a semiconductor chip for explaining the manufacturing method of the first embodiment, FIG. 3 is a sectional view of the second embodiment of the present invention, and FIG. 4 is a sectional view of the second embodiment. FIG. 5 is a cross-sectional view of an example of a conventional semiconductor device, and FIGS. 6(a) and (b) are cross-sectional views of a semiconductor chip for explaining the manufacturing method of the conventional semiconductor device. FIG. 2 is a cross-sectional view of a semiconductor chip. 1... P type semiconductor substrate, 2... N type epitaxial layer, 2A... N+ type epitaxial layer, 3... N+
Type buried layer, 4,4A...P+ type buried layer, 5...P+
type well layer, 6... P+ type layer for insulation isolation, 7...N
4 type well layer, 8... N++ type well layer, 9... oxide film, 10, IOA, IOB, IOC... mask. ′! e5 + solid summer Z eye 3 old 4th old member 5 figure million Z concave

Claims (1)

[Claims] In a semiconductor device formed on a P-type semiconductor substrate and having a bipolar transistor and a CMOS transistor formed in an N-type epitaxial layer, the impurity concentration of the bipolar transistor formation region is equal to the impurity concentration of the P-channel MOS transistor formation region, or A semiconductor device characterized by being formed high.