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JPS63181330A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63181330A
JPS63181330A JP62012497A JP1249787A JPS63181330A JP S63181330 A JPS63181330 A JP S63181330A JP 62012497 A JP62012497 A JP 62012497A JP 1249787 A JP1249787 A JP 1249787A JP S63181330 A JPS63181330 A JP S63181330A
Authority
JP
Japan
Prior art keywords
groove
substrate
silicon substrate
etching mask
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62012497A
Other languages
Japanese (ja)
Inventor
Masa Kase
雅 加瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62012497A priority Critical patent/JPS63181330A/en
Publication of JPS63181330A publication Critical patent/JPS63181330A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To shorten the process by cleaning the inner surface of a groove formed in a silicon substrate using a cleaning liquid which is faster in the etch rate of the etching mask of the silicon substrate than in the etch rate of the substrate, thereby beveling the opening part of the groove. CONSTITUTION:With a silicon dioxide film 22 on a silicon substrate 21 as a mask, the silicon substrate 21 is etched to form a groove 25 in the substrate 21, and thereafter the inner surface of the groove 25 is cleaned using a cleaning liquid which is faster in the etch rate of the etching mask 22 than in the etch rate of the silicon substrate 21, e.g., a mixed liquid of hydrofluoric acid, acetic acid and pure water. As a result, in a groove opening part 24, the silicon substrate 21 surface surrounding the opening part 24 is exposed. And, when the substrate 21 surface surrounding the groove opening part 24 is exposed in this way, the substrate silicon of the corner section of the groove opening part 24 is etched from the lateral and vertical directions, so the corner section becomes a taper 28, whereby a groove with a taper 28 in the opening part 24 is formed. With this, the etching of the substrate can be shortened.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体素子の製造方法、特に溝形成技術に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a groove forming technique.

(従来の技術) 従来の溝形成技術を第3図を参照して説明する。(Conventional technology) A conventional groove forming technique will be explained with reference to FIG.

まず、シリコン基板11上に7000λの酸化シリコン
@12を形成する(第3図(a))。次に、酸化シリコ
ン膜12上にレジスト13を塗布し、パターニングを行
う(第3図(b))。次に1パターニングされfcVシ
スト13をマスクとして酸化シリコン[12をRIE法
によりエッチングマスク層をし、酸化シリコン膜12に
溝形成用の開口部14を形成し、その後レジスト13を
除去する(第3図(C))。その後、酸化シリコンM1
2をマスクとしてシリコン基板11をRIE法によりエ
ッチングし、該基板11に溝工5を形成する(第3図(
d))。次いで、形成した溝15の内壁表面に発生して
いる堆積膜やダメージ層16をウェット法によp除去し
、その後、溝15内壁の酸化を行って酸化膜17を形成
する(第3図(e))。
First, silicon oxide @12 having a thickness of 7000λ is formed on a silicon substrate 11 (FIG. 3(a)). Next, a resist 13 is applied onto the silicon oxide film 12 and patterned (FIG. 3(b)). Next, using the fcV cyst 13 as a mask, the silicon oxide film 12 is etched as an etching mask layer by the RIE method, an opening 14 for forming a groove is formed in the silicon oxide film 12, and then the resist 13 is removed (third Figure (C)). After that, silicon oxide M1
2 as a mask, the silicon substrate 11 is etched by the RIE method to form a groove 5 in the substrate 11 (see FIG.
d)). Next, the deposited film and damaged layer 16 generated on the inner wall surface of the formed groove 15 are removed by a wet method, and then the inner wall of the groove 15 is oxidized to form an oxide film 17 (see FIG. 3). e)).

しかしながら、上記の方法では、溝15内壁を酸化する
時、溝15の開口部において応力が発生し、耐圧の劣化
を招く。
However, in the above method, when the inner wall of the groove 15 is oxidized, stress is generated at the opening of the groove 15, leading to deterioration of the withstand voltage.

そこで、酸化時に発生する応力を緩和するために、第3
図<C)の終了後、ウェットエッチングマスク層をやフ
ツ素系のガスを用いたグラズマエッチングにより第4図
(a)に示すようにシリコン基板11をエッチングマス
ク層をし、さらに続いてHIE法でシリコン基板11を
エッチングマスク層をすることにより、第4図(b)に
示すように開口部に傾斜のつい九溝15aを形成してい
る。第4図(c)は、その溝15aに、洗浄後、酸化膜
171Lを形成し次状態を示す。
Therefore, in order to alleviate the stress generated during oxidation, a third
After the completion of the process shown in FIG. 4(C), the silicon substrate 11 is etched as an etching mask layer as shown in FIG. By using the silicon substrate 11 as an etching mask layer using a method, nine inclined grooves 15a are formed at the openings as shown in FIG. 4(b). FIG. 4(c) shows the next state in which an oxide film 171L is formed in the groove 15a after cleaning.

(発明が解決しようとする問題点) しかるに1上記の方法では、傾斜付きの溝15aとする
九めにシリコン基板11を2度に分けてエッチングマス
ク層をする必要があり、工程が長くなる問題点があつ九
(Problems to be Solved by the Invention) However, 1. In the above method, it is necessary to divide the silicon substrate 11 into two parts to form an etching mask layer in order to form the inclined groove 15a, which lengthens the process. Nine points.

この発明は上記の点に鑑みなされたもので、その目的は
、開口部に傾斜のついた溝を少ない工程数で形成するこ
とのできる半導体素子の製造方法を提供することにある
The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a semiconductor device that can form a groove with an inclined opening in a reduced number of steps.

(問題点を解決するための手段) この発明では、シリコン基板表面のエッチングマスク層
をマスク層をマスクとしてシリコン基板をエッチングマ
スク層をすることにより該基板に溝を形成し次後、洗浄
液、特にシリコン基板とエッチングマスク層をマスク層
ヲエッチングし、しかもエッチングマスク層をマスク層
のエッチングマスク層を速度の万がシリコン基板のエッ
チングマスク層を速度より速い洗浄液を用いて前記溝内
壁の洗浄を行う。
(Means for Solving the Problems) In the present invention, grooves are formed in the silicon substrate by using an etching mask layer on the surface of the silicon substrate as a mask. Etching the silicon substrate and the etching mask layer, and cleaning the inner wall of the groove using a cleaning solution faster than the etching speed of the etching mask layer of the silicon substrate. .

(作用) 前記洗浄液を用いて溝内壁の洗浄を行うと、シリコン基
板とエッチングマスク層をマスク層もエッチングマスク
層をされるようになるが、この時、シリコン基板よりエ
ッチングマスク層をマスク層の万がエッチングマスク層
を速度が速いため、溝開口部においては、第2図(b)
に示すように、溝開口部周辺のシリコン基板表面が露出
する。そして、このようにして溝開口部周辺の基板底面
が露出すると、溝開口部角部の基板シリコンが横方向と
縦方向からエッチングマスク層をされるため、該部分は
第2図(c)に示すようにチー・々となり、開口部にテ
ーパ(傾斜)のついた溝が形成されることになる。
(Function) When the inner wall of the groove is cleaned using the cleaning liquid, the silicon substrate and the etching mask layer become the same as the etching mask layer, but at this time, the etching mask layer is removed from the silicon substrate. In the unlikely event that the etching mask layer is etched at a high speed, at the groove opening, the
As shown in , the silicon substrate surface around the trench opening is exposed. When the bottom surface of the substrate around the trench opening is exposed in this way, the substrate silicon at the corner of the trench opening is covered with an etching mask layer from both the horizontal and vertical directions, so that this area is exposed as shown in FIG. 2(c). As shown, the groove becomes tapered (slanted) at the opening.

(実施例) 以下この発明の一実施例を第1図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

まず、第1図(+L)に示すように、シリコン基板21
上に熱酸化法によや酸化シリコン膜22を1000^成
長させる。
First, as shown in FIG. 1 (+L), the silicon substrate 21
A silicon oxide film 22 with a thickness of 1000^ is grown thereon by a thermal oxidation method.

次に、その酸化シリコン膜22上にVシスト23を塗布
し、露光・現像を行い、レジスト23のパターニングを
行う(第1図(b))。
Next, a V cyst 23 is applied onto the silicon oxide film 22, exposed and developed, and the resist 23 is patterned (FIG. 1(b)).

次に、パターニングされ次レジスト23をマスクとして
酸化シリコン膜22をRIE法によりエッチングマスク
層をし、酸化シリコン膜22に溝形成用の開口部24を
形成し、その後レジスト23を除去する(第1図(C)
)。
Next, using the patterned resist 23 as a mask, the silicon oxide film 22 is etched by RIE to form an opening 24 for forming a groove in the silicon oxide film 22, and then the resist 23 is removed (first Diagram (C)
).

その後、酸化シリコン膜22をエッチングマスク層をマ
スクとしてシリコン基板21を塩素系のガスでRIE法
によタエッチングし、該基板21に$25を形成する(
第1図(d)〕。
Thereafter, using the silicon oxide film 22 as an etching mask layer as a mask, the silicon substrate 21 is etched using a chlorine-based gas by the RIE method to form a $25 layer on the substrate 21 (
Figure 1(d)].

次いで、7ツ酸、硝酸および純水の混合液を用いて溝2
5内壁の洗浄を行い、第2図(a)に示すように$25
の内壁表面に発生している堆積膜26やダメージ層27
を除去する。この時、上記混合液を洗浄液として用い、
しかも堆積膜26やダメージ層27の除去後も更にエッ
チングマスク層をを続けると、酸化シリコン膜22とシ
リコン基板21がエッチングマスク層をされ、しかもそ
の際シリコン基板21より酸化シリコン膜22の方がエ
ッチングマスク層を速度が速いため、溝25の開口部に
おいては、第2図(b)に示すように、溝25開口部周
辺のシリコン基板21表面が露出する。そして、このよ
うにして溝25開口部周辺の基板21表面が露出すると
、溝25開口部角部の基板シリコンが横方向と縦方向か
らエッチングマスク層をされるため、該部分は第2図(
a)に示すようにテーパ28となり、開口部にテーパ(
傾斜)28のついた溝25が第1図(e)に示すように
形成されることになる。
Next, groove 2 was prepared using a mixture of hepturic acid, nitric acid, and pure water.
5. Clean the inner wall, as shown in Figure 2 (a).
Deposited film 26 and damaged layer 27 occurring on the inner wall surface of
remove. At this time, using the above mixed solution as a cleaning solution,
Moreover, if the etching mask layer is continued even after the deposited film 26 and the damaged layer 27 are removed, the silicon oxide film 22 and the silicon substrate 21 will be used as the etching mask layer, and in this case, the silicon oxide film 22 will be larger than the silicon substrate 21. Since the etching mask layer is etched at a high speed, the surface of the silicon substrate 21 around the opening of the groove 25 is exposed at the opening of the groove 25, as shown in FIG. 2(b). When the surface of the substrate 21 around the opening of the groove 25 is exposed in this way, the substrate silicon at the corner of the opening of the groove 25 is covered with an etching mask layer from both the horizontal and vertical directions, so that this area is removed as shown in FIG.
As shown in a), it becomes a taper 28, and the opening has a taper (
A groove 25 with a slope 28 is formed as shown in FIG. 1(e).

そして、このようにして洗浄と傾斜の形成を同時に行っ
たならば、最後に、溝25内壁の酸化を行って酸化膜2
9を形成する(第1図(f))。
After cleaning and forming the slope are performed simultaneously in this way, the inner wall of the groove 25 is finally oxidized to form an oxide film 2.
9 (FIG. 1(f)).

なお、上記一実施例では、シリコン基板エッチングマス
ク層をマスク材料として熱酸化による酸化シリコン膜2
2を用いたが、CVD法で堆積し次酸化シリコン膜や不
純物(P 、 B 、 Asなど)を添加し几酸化シリ
コン膜を用いることもできる。
In the above embodiment, the silicon oxide film 2 is formed by thermal oxidation using the silicon substrate etching mask layer as a mask material.
2 was used, but it is also possible to use a sub-silicon oxide film deposited by the CVD method or a phosphoric oxide film added with impurities (P, B, As, etc.).

マ友、シリコン基板エッチングマスク層をマスク材料と
してレジストや窒化シリコン膜などを用いることができ
、その場合には、フッ酸、硝酸に1マスク材料をエッチ
ングマスク層をできる液あるいは混合液(硫酸。
A resist or a silicon nitride film can be used as the mask material for the silicon substrate etching mask layer. In that case, a solution or mixed solution (sulfuric acid) that can form the etching mask layer by adding one mask material to hydrofluoric acid or nitric acid.

熱リン酸など)を混ぜることにより上記一実施例と同様
にし得る。
The same method as in the above embodiment can be achieved by mixing hot phosphoric acid, etc.).

また、エッチングマスク層をやエッチングマスク層を後
に発生する堆積膜26がフッ酸、硝酸でエッチングマス
ク層をできない場合には、該堆積膜26をエッチングマ
スク層をできる液あるいは混合液を混ぜることにより上
記−実施例と同様にし得る。
In addition, if the etching mask layer or the deposited film 26 generated after the etching mask layer cannot be formed into an etching mask layer with hydrofluoric acid or nitric acid, the deposited film 26 can be mixed with a liquid or mixed solution that can be formed into an etching mask layer. It can be similar to the above-example.

さらに1フツ酸および硝酸に、酸化シリコン膜やシリフ
ン基板のエッチングマスク層を速度を制御する友めに、
他の液あるいは混合液を混ぜてもよい。
Furthermore, the etching mask layer of the silicon oxide film and the silicon substrate was added to monofluoric acid and nitric acid to control the speed.
Other liquids or mixed liquids may be mixed.

また、シリコン基板エッチングマスク層をマスク構造を
多層構造(酸化シリコン膜−窒化シリコン膜−酸化シリ
コン膜など)にした場合は、シリコン基板と接している
膜をエッチングマスク層をできる液あるいは混合液をフ
ッ酸、硝酸に混ぜることにより上記一実施例と同様にし
得る(友だし、シリコン基板と接している膜がフッ酸と
硝酸でエッチングマスク層をできる場合には、フッ酸と
硝酸のみでよい)。
In addition, when the silicon substrate etching mask layer has a multilayer mask structure (silicon oxide film - silicon nitride film - silicon oxide film, etc.), the film in contact with the silicon substrate can be coated with a solution or mixed solution that forms the etching mask layer. By mixing it with hydrofluoric acid and nitric acid, it can be done in the same way as in the above embodiment (if the film in contact with the silicon substrate can be etched as an etching mask layer with hydrofluoric acid and nitric acid, only hydrofluoric acid and nitric acid are sufficient) .

(発明の効果) 以上詳細に説明したように、この発明の方法によれば、
洗浄工程を利用して溝開口部に傾斜をつけることができ
るので、基板のエッチングマスク層を工程は次だ一回で
よく、第3図の傾斜なしの溝形成法と同一の少ない工程
数で傾斜つきの溝を形成することができる。ま友、この
方法によれば、洗浄液の組成により、溝開口部の傾斜角
度を任意に制御することができる。
(Effect of the invention) As explained in detail above, according to the method of this invention,
Since the groove opening can be sloped using the cleaning process, only one step is required to remove the etching mask layer of the substrate, and the process is performed using the same reduced number of steps as the non-slanted groove forming method shown in Figure 3. A sloped groove can be formed. According to this method, the inclination angle of the groove opening can be arbitrarily controlled by changing the composition of the cleaning liquid.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の半導体素子の製造方法の一実施例を
示す工程断面図、第2図は上記一実施例の一部工程を取
出して示す詳細断面図、第3図は従来の溝形成技術を示
す工程断面図、第4図は従来の改良溝形成技術を示す工
程断面図である。 21・・・シリコン基板、22・・・酸化シリコン膜、
24・・・開口部、25・・・溝、26・・・堆積膜、
27・・・ダメージ層、28・・・テーパ(傾斜)。 第2図
FIG. 1 is a process sectional view showing an embodiment of the semiconductor device manufacturing method of the present invention, FIG. 2 is a detailed sectional view showing a partial process of the above-mentioned embodiment, and FIG. 3 is a conventional groove forming method. FIG. 4 is a process cross-sectional view showing the conventional improved groove forming technique. 21... Silicon substrate, 22... Silicon oxide film,
24... Opening, 25... Groove, 26... Deposited film,
27... Damage layer, 28... Taper (slope). Figure 2

Claims (1)

【特許請求の範囲】 (a)シリコン基板表面のエッチングマスク層をマスク
としてシリコン基板をエッチングすることにより、該基
板に溝を形成する工程と、 (b)その後、洗浄液、特にシリコン基板とエッチング
マスク層をエッチングし、しかもエッチングマスク層の
エッチング速度の方がシリコン基板のエッチング速度よ
り速い洗浄液を用いて前記溝内壁を洗浄することにより
、同時に溝の開口部に傾斜をつける工程とを具備してな
る半導体素子の製造方法。
[Claims] (a) A step of etching the silicon substrate using an etching mask layer on the surface of the silicon substrate as a mask to form a groove in the substrate; (b) After that, using a cleaning solution, particularly the silicon substrate and the etching mask; etching the layer, and cleaning the inner wall of the groove using a cleaning solution in which the etching rate of the etching mask layer is faster than the etching rate of the silicon substrate, and at the same time slopes the opening of the groove. A method for manufacturing a semiconductor device.
JP62012497A 1987-01-23 1987-01-23 Manufacture of semiconductor device Pending JPS63181330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62012497A JPS63181330A (en) 1987-01-23 1987-01-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62012497A JPS63181330A (en) 1987-01-23 1987-01-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63181330A true JPS63181330A (en) 1988-07-26

Family

ID=11807008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62012497A Pending JPS63181330A (en) 1987-01-23 1987-01-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63181330A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858859A (en) * 1990-05-28 1999-01-12 Kabushiki Kaisha Toshiba Semiconductor device having a trench for device isolation fabrication method
JP2007500454A (en) * 2003-05-20 2007-01-11 フェアチャイルド セミコンダクター コーポレーション Structure and method of forming trench MOSFET with self-alignment
JP2008098593A (en) * 2006-09-15 2008-04-24 Ricoh Co Ltd Semiconductor device and manufacturing method thereof
JP2009206502A (en) * 2008-01-29 2009-09-10 Sanyo Electric Co Ltd Mesa type semiconductor device, and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858859A (en) * 1990-05-28 1999-01-12 Kabushiki Kaisha Toshiba Semiconductor device having a trench for device isolation fabrication method
JP2007500454A (en) * 2003-05-20 2007-01-11 フェアチャイルド セミコンダクター コーポレーション Structure and method of forming trench MOSFET with self-alignment
JP2008098593A (en) * 2006-09-15 2008-04-24 Ricoh Co Ltd Semiconductor device and manufacturing method thereof
JP2009206502A (en) * 2008-01-29 2009-09-10 Sanyo Electric Co Ltd Mesa type semiconductor device, and manufacturing method thereof

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