JPS6267852A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To automatize the design of wiring pattern and to optimize it so as to make the best use of the advantages of I<2>L's, by connecting the I<2>L's with wires arranged at the same pitch as electrodes of the I<2>L. CONSTITUTION:A semiconductor integrated circuit device provided with I<2>L's has first-layer wires Ly juxtaposed in the direction Y, second-layer wires Lx juxtaposed in the direction X orthogonally to the first-layer wires Ly, and through holes TH for connecting the wires Ly in the first layer to the wires Lx in the second layer. Said first-layer wires Ly are located in the first layer in multiple wiring layers and the second-layer wires Lx are located in the second layer therein. By appropriately connecting the first-layer wires Ly and the second-layer wires Lx through the through holes TH, the I<2>L's can be connected with each other by wires arrange regularly.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to semiconductor integrated circuit device technology,
It relates to a technique that is particularly effective when applied to a semiconductor integrated circuit device in which IL (Integrated Injection Logic) is formed, for example, a technique that is effective when applied to a mixed analog/digital semiconductor integrated circuit device. .

[Background technology]

IIL is, for example, published by Sanens Forum Co., Ltd., "Very LSI Device Handbook J, November 2, 1982.
As described in the publication on the 8th, pages 172-178 (Section 2 IIL), advantages include high integration density, low power consumption, and good device compatibility with analog circuits. Because of this, it is widely used in consumer and industrial applications. In addition, its high-speed performance has also improved with recent VLSI (
Advances in process and device technology (ultra-large scale semiconductor integrated circuits) have led to significant improvements. For this reason, IIL is attracting attention as a basic circuit for future VLSI.

FIG. 6 1al Ibl lcl shows the general configuration of the IIL.

As shown in the figure, IIL is a semiconductor substrate 1 on which an n-type epitaxial layer is formed and a p-type injector diffusion layer 2.
1 and a p-type base diffusion layer 22, and one or more n-type collector diffusion layers 3 are formed in the p-type base diffusion layer 22, isometrically speaking, a pnp bipolar transistor Qp and an npn bipolar fist transistor Qn are integrally integrated so as to share a part of the electrode area. In the figure, INJ represents an injector formed by the p-type injector diffusion layer 21, B represents a pace B formed from the p-type base expansion layer 22, and C represents a collector formed from the n+ type collector diffusion layer 3, respectively.

Since the above-mentioned IIL can be arranged regularly and orderly around the injector INJ, it is fully suitable for miniaturization of elements and high integration density.

However, the wiring connecting between the above-mentioned IILs does not have any particular regularity (for example, aluminum
This was done randomly using appropriate layer wiring. For this reason, as the degree of integration of semiconductor integrated circuit devices increases, their wiring becomes more complex, making optimization difficult. The inventors of the present invention have clarified the problem that this becomes a major impeding factor that offsets the above-mentioned advantages of IIL.

[Purpose of the invention]

The purpose of this invention is to provide a technology that enables automation of wiring design and optimization that fully utilizes the advantages of IIL by providing regularity suitable for automation to the wiring that connects IIL. It's about doing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In other words, the pitch of the wiring connecting between IILs is
By specifying the electrode arrangement pitch to be the same as the electrode arrangement pitch of the IL, the wiring connecting between the IILs can have a regularity suitable for automation, thereby making it possible to automate the wiring design and fully utilize the advantages of the IIL. The objective is to enable such optimization.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device to which the present invention is applied.

The semiconductor integrated circuit device whose essential parts are shown in the same figure is a semiconductor integrated circuit device in which the above-mentioned IIL is formed [, the first layer wiring Ly arranged in the same direction, that is, the Y direction, The second layer wiring LX, which is aligned in the direction perpendicular to the first layer wiring Ly, that is, the X direction, connects the first layer wiring Ly and the second layer wiring lsLx. It has a through hole TH. Wiring between a large number of IILs is performed by the first layer wiring Ly, the second layer wiring LX, and the through holes TH.

Note that for other wiring, for example, power supply wiring such as the injector power supply Ij, the third layer wiring LZ is used. Furthermore, aluminum wiring formed in multiple layers is used for the wiring Ly, Lx, and Lz in each layer.

f! IJ2 FIG. 1al [bl shows partially extracted wiring Ly of the first layer and wiring Lx of the 20th layer.

As shown in the figure, in the embodiment, the first layer wiring Ly is formed in the first layer of the multilayer wiring, and the second layer wiring Lx is formed in the second layer. Then, the wiring Ly of the first layer and the wiring L x )- of the second layer are appropriately connected by the through holes TH, so that the wiring connecting between the IILs is regularly performed.

Further, the first layer wiring Ly is formed in the same direction as the running direction (Y) of the injector INJ of the above IIL, while the second layer wiring Lx is formed perpendicular to the running direction (Y) of the above injector INJ. It is formed in the direction (X) and is at ℃. This allows the electrode of the injector INJ to be connected to the first layer wiring Ly.
This allows the p-type injector to be taken out in full contact with the p-type injector diffusion layer 21, while the second-layer wiring Lx allows the IIL arranged on both sides of the injector INJ to be taken out across the injector INJ. so that they can be connected to each other.

FIG. 2 (al indicates the case where the gate arrangement pitch a of IIL is larger than the minimum arrangement pitch b of the arrangement aLx of the second layer,
Wirings Ly and Lx are electrically connected between the gates, and the area between the gates is effectively used to improve the wiring density.

Figure 2 [bl] shows that the gate arrangement pitch of IIL matches the arrangement pitch of the second layer, and that the arrangement of pitch B and collector C in the gate as gate electrodes is different from that in other gates. Furthermore, since the wiring Ly and Lx are connected on the gate electrode, the arrangement pitch d of the gate electrode is the same as the arrangement pitch of the wiring Ly, and furthermore, the gate arrangement pitch a is the same as the arrangement pitch of the wiring Lx. It has become. Since the configuration is as described above, automatic wiring by a machine is facilitated.

Figure 3 [aHbl is the above two types of wiring Ly, Lx and through hole x to create the wiring structure as shown in Figure 2 1bl.
An example of the formation of TH is shown in FIG.
It is shown by a cross-sectional view tal and a perspective plan view [bl].

In the same figure, the electrode extraction area of the first layer wiring Ly?
: W1, and the second layer wiring LX and the first layer wiring Ly
Area W2 of the connection part with through hole TH
Then, the relationship between Wl and W2 is Ly, L, where Wl is approximately the same as W2, or Wl is slightly smaller than W2.
It is set so that it does not exceed the XO width. In other words, at the electrode extraction portion and through hole TH, the wiring L
y.

The width of LX is specified to be a size that does not bulge.

In this case, the pace and emitter of IIL are
At the location connected to x, the through hole TH is formed directly above the base and emitter. Roughly speaking, along with this, the arrangement pitch d of the wiring Ly is
The pitch of the electrodes (B, C, C, C) of the IIL is defined to be the same, and the arrangement pitch a of the arrangement @Lx is defined to be the same as the arrangement pitch of the IIL gate. In this case, IIL
The arrangement pitch tdl of the electrodes is set to 5 so that the equivalent npn bivorous transistor Qn (FIG. 6 [cl)] can secure the minimum required reverse current amplification factor βi. This reverse current amplification factor βi is determined by the area SD of the pace diffusion layer of IIL.
The ratio of the surface gsc of the collector diffusion layer to K (SC/SB
). Therefore, the arrangement pitch d of the wirings Ly and Lx is set to such a size that the minimum reverse current amplification factor βi, ie, SC/SB, required by IIL can be obtained.

As a result of the above, each of the wirings Ly and Lx can be wired regularly and orderly according to the same dimensional rules as the electrode arrangement of IIL. By having such regularity, the wiring that connects the IILs becomes suitable for automation using, for example, CAD (computer-aided design system).
Optimization that fully utilizes the strengths of IL becomes possible.

In addition, in FIG. 3 fat, 4 is a surface insulating oxide film, 5 is
indicate interlayer insulating films, respectively.

FIG. 4 shows another embodiment of the invention.

In the semiconductor integrated circuit device shown in the figure, the electrodes of each IIL are arranged in parallel with the injector INJ. In a semiconductor integrated circuit device in which such an IIL is formed, the second layer wiring Lx is connected to the first layer wiring Lyftl)-th.
In addition to forming each layer, the wiring Ly of the first layer
is formed in the same direction as the electrode arrangement direction (Y) of the IIL, while the second layer wiring LX is formed in the direction (X) orthogonal to the electrode arrangement direction (Y).

Thereby, the same effect as in the case described above can be obtained.

FIG. 5 shows the overall configuration of the semiconductor integrated circuit device described above.

In the semiconductor integrated circuit device 100 shown in the figure, the first layer wiring Ly formed in the first layer and the second layer wiring Ly formed in the second layer
Each block 102, 103, 1
04.105, and wiring between blocks is performed by the third layer wiring LZ formed in the third layer.

As a result, it is possible to configure one circuit functional block from a plurality of IILs or linear elements, and to configure a semiconductor integrated circuit device 100 having an arbitrary function by connecting a plurality of circuit functional blocks. Furthermore, in this case, since the wiring within a block and the wiring between blocks are formed in different wiring layers, each wiring can be designed independently without interfering with each other. This makes it possible to freely configure highly functional and versatile semiconductor integrated circuit devices by, for example, leaving the functions within the blocks as they are and changing only the wiring between the blocks.

〔effect〕

The pitch of the wiring connecting between 1111IL is
By specifying the pitch to be the same as the electrode arrangement pitch of the IIL, the wiring connecting between the IILs can have regularity suitable for automation, thereby making it possible to automate wiring design and fully utilize the advantages of the IIL This has the effect of making it possible to optimize the system to the best of its ability.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the electrodes of the injector INJ may not be taken out entirely, but may be taken out partially at appropriate locations. Alternatively, a configuration may be adopted in which a plurality of rows of injectors having mutually different running directions are arranged in parallel.

[Application field]

The above description has been made of the case where the invention made by the present inventor is applied to analog/digital mixed semiconductor integrated circuit devices, which is the background field of application, but the invention is not limited to this (for example, digital-only It can also be applied to a semiconductor integrated circuit device or a bipolar 27MO8 mixed type semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an embodiment of a main part of a semiconductor integrated circuit device to which the present invention is applied, and FIG. 2 (aJJb
l is a perspective view showing the wiring section taken out, Fig. 3 tal,
lbl is a diagram showing the formation state of multilayer wiring and through holes in the semiconductor integrated circuit device shown in FIG. 1, FIG. 4 is a diagram showing another embodiment of the present invention, and FIG. 5 is a diagram to which the present invention is applied. A diagram showing the overall configuration of a semiconductor integrated circuit device.
FIG. IIL...Integrated injection
Logic, B, C... IIL [pole (Heath collector), INJ... Injector, Ly... 1st layer wiring, 2nd layer wiring, Lz... 3rd layer wiring, TH...through hole, d...wiring pitch. Agent Patent Attorney Katsuma Ogawa Otsu'-ゝ＼(, 1~D2 Figure 2 Figure C6,) Figure 5, -1111■

Claims (1)

[Claims] 1. IIL (Integrated Injection)
In a semiconductor integrated circuit device in which logic) is formed,
A semiconductor integrated circuit device characterized in that the arrangement pitch of wiring connecting between IILs is the same as the electrode arrangement pitch of the IILs. 2. The first layer has wiring lines aligned in the same direction and second layer lines aligned in a direction perpendicular to the first layer lines; Wiring between the above-mentioned IILs is performed by through holes connecting the wiring of the second layer, the wiring of the second layer, and the wiring of both the first and second layers. The semiconductor integrated circuit device according to item 1. 3. The first layer has wiring arranged in the same direction and a second layer arranged in a direction perpendicular to the first layer wiring, The wiring between the above IILs is performed by the wiring in the second layer, the wiring in the second layer, and the through hole connecting the wiring in both the first and second layers. In the layer, the wiring of the second layer is 2
The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is formed in each layer. 4. The first layer has wiring arranged in the same direction and a second layer arranged in a direction perpendicular to the first layer wiring, The wiring between the above IILs is performed by the wiring in the second layer, the wiring in the second layer, and the through hole connecting the wiring in both the first and second layers. In the layer, the wiring of the second layer is 2
The first layer wiring is formed in the same direction as the running direction of the injector of the IIL, while the second layer wiring is formed in a direction perpendicular to the running direction of the injector. A semiconductor integrated circuit device according to any one of claims 1 to 3, characterized in that: 5. The first layer has wiring arranged in the same direction and a second layer arranged in a direction perpendicular to the first layer wiring, The wiring between the above IILs is performed by the wiring in the second layer, the wiring in the second layer, and the through hole connecting the wiring in both the first and second layers. In the layer, the wiring of the second layer is 2
are formed in each layer, and the wiring of the second layer is formed in the same direction as the electrode arrangement direction of the IIL,
4. The semiconductor integrated circuit device according to claim 1, wherein the second layer wiring is formed in a direction perpendicular to the electrode arrangement direction. 6. The first layer has a first layer of wiring arranged in the same direction and a second layer of wiring arranged in a direction perpendicular to the first layer of wiring; The wiring between the above 11L is performed by the wiring in the layer, the wiring in the second layer, and the through hole connecting the wiring in both the first and second layers. A semiconductor integrated circuit device according to any one of claims 1 to 5, characterized in that a through hole is provided directly above the electrode at a location connected to the wiring. 7. The first layer has a first layer of wiring arranged in the same direction and a second layer of wiring arranged in a direction perpendicular to the first layer of wiring; Wiring between the IILs is performed by through holes that connect the wiring in the second layer, the wiring in the second layer, and the wiring in both the first and second layers, and the dimensions of the through holes match the wiring. The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein the width is defined within a width of .