JPS6236400B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a field effect transistor, and particularly to the structure of a source electrode.

(2) Prior Art and Problems In ultra-high frequency shot barrier type field effect transistors made of GaAs, a structure as shown in FIG. 1 has been proposed for the source electrode. That is, the active layer 2 is formed on the active layer 2 made of n-type GaAs formed on the surface of the semi-insulating substrate 1.
It has a gate electrode 3 that is in horizontal contact with the active layer 2, and a source electrode 4 and a drain electrode 5 that are in ohmic contact with the active layer 2. On the other hand, on the back side of the semi-insulating substrate 1, there is a semi-insulating substrate in the area where the source electrode 4 is formed. 1 and the active layer 2, a through hole 6 is formed on the back surface of the semi-insulating substrate 1 including the inner wall surface of the through hole 6.
Vapor deposited layer 7 in which an AuGe alloy layer and a gold (Au) layer are laminated
It is connected to the outside via a back electrode 9 consisting of a plating layer 8 of Au on top of the back electrode 9.

In the above conventional structure, the thick Au plating layer 8 (approximately
The thickness of 35 to 50 [μm] acts as a heat sink and provides good heat dissipation characteristics. On the other hand, when opening the through hole 6, etching must be performed until the back surface of the source electrode 4 is exposed; Since the source electrode 4 rapidly progresses along the line, peeling of the source electrode 4 is likely to occur. Therefore, the amount of etching must be strictly controlled, but this control is difficult in practice, and therefore there is always a risk that undesirable etching will proceed as described above.

(3) Object of the Invention An object of the present invention is to solve the above-mentioned problems and provide a field effect transistor which is free from the risk of causing the undesirable etching and has a structure that is easy to manufacture.

(4) Structure of the Invention According to the present invention, the above object is to provide a region with a high impurity concentration as a source region, and arrange it so that it reaches from the back side of the substrate to the bottom of the high impurity concentration region but does not reach the surface. This is achieved by using a structure in which the high impurity concentration region and the back electrode on the back side of the substrate are connected by a connecting conductor.

Hereinafter, as an embodiment of the present invention, ultra-high frequency field effect transistors made of GaAs manufactured according to the present invention will be connected according to the drawings.

FIG. 2 is a sectional view of a main part showing the above embodiment, and the same parts as in FIG. 1 are designated by the same reference numerals.

In the figure, 1 is a semi-insulating substrate made of GaAs doped with chromium (Cr), and 2 is an n-type substrate.
The active layer is made of GaAs, and the layer 11 directly below the gate electrode 3 is doped with n-type impurities such as silicon (Si) and sulfur (S) by ion implantation at a concentration of approximately 0.5 to 0.5.
An n-type region of 3×10 ¹⁷ [cm ^-3 ] and silicon (Si) of 2×10 ¹⁸ [cm ^-3 ] on both sides sandwiching the n-type region 11.
It consists of three regions, n ⁺ regions 12 and 13, implanted to the above concentration.

The n ⁺ region 13 is a drain region, and a drain electrode 5 made of metal is provided on its surface to form ohmic contact with n-type GaAs. This drain electrode 5 has a thickness of approximately 400 [Å], for example.
An AuGe alloy layer with a thickness of approximately 4000 [Å] on top of it
A stack of Au layers can be used.

Another n ⁺ region 12 is a source region,
In the present invention, the source electrode seen in the conventional example can be omitted on this n ⁺ region 12. That is, in this embodiment, the n ⁺ region 1 on the back surface of the semi-insulating substrate 1
2, a recess 14 reaching the n ⁺ region 12 is provided, and an AuGe alloy layer (thickness approximately 400 [Å] ) and Au layer (approximately 4000 mm thick)
[Å]) evaporated layer 7 and Au plating layer 8
(thickness approximately 35 to 50 [μm]).

With the above structure, this embodiment has a recess 1
Since n ⁺ type GaAs is exposed on the bottom surface 15 of 4, and the AuGe alloy is a material that forms ohmic contact with n ⁺ type GaAs, the n region 12, that is, the source region, is directly connected to the back electrode 9 at its bottom. Ru. In the device of this embodiment, during operation, the carrier is directly supplied to the n ⁺ region 12 from the back electrode 9, flows into the drain electrode 13 under the control of the potential of the gate electrode 3, and is sent out from the drain electrode 5. However, since the n ⁺ region 12 has a low electrical resistance, there is no need to provide an electrode on the surface as in the conventional example.

As described above, in this embodiment, by making the source region a high concentration region (n ⁺ region 12), this n ⁺
It is now possible to connect the region 12 directly to the back electrode 9, and etching from the back surface of the substrate to form this conductive path can be carried out until reaching the n ⁺ region 12, which eliminates the undesirable problems seen in conventional structures. No etching occurs. Therefore, the manufacturing schedule is stabilized, and the manufacturing yield and reliability of the device are improved.

Furthermore, this embodiment has the great advantage that, since it is not necessary to provide a source electrode on the surface of the active layer 2, the pattern of the gate electrode is not disturbed, and therefore the distance between the gate electrode and the source electrode can be arbitrarily selected.

In other words, it is desirable that the gate electrode be placed as close as possible to the source region, but if the source electrode is present, a step will occur near the gate electrode pattern of the photoresist film for patterning the gate electrode, and this step and the step of the source electrode will Diffuse reflection of light causes disturbances in the gate electrode pattern. Therefore, it was necessary to leave a gap of at least 1 to 2 [μm] between the gate electrode and the source electrode.

In this embodiment, this problem is also eliminated, the placement position of the gate electrode can be arbitrarily selected in the design, and the patterning accuracy of the gate electrode is improved in the manufacturing process, and the work is facilitated. Therefore, the electrical characteristics and manufacturing yield of the field effect transistor are improved.

Although the above embodiment has been explained using a planar structure, this invention applies even if the device to be manufactured has a structure in which the active layer has a mesa shape or a recessed structure in which the gate electrode forming part is a concave part. The invention can be carried out.

Furthermore, the present invention can also be implemented in field effect transistors made of semiconductors other than GaAs.

Furthermore, it goes without saying that there are no particular limitations on the manufacturing method and materials for each part for carrying out the present invention. For example, ohmic contact to the high concentration region 12 can also be obtained by forming, for example, a titanium-platinum-gold (Ti-Pt-Au) layer instead of the AuGe alloy layer. Furthermore, it is practical to form the connecting conductor that directly connects the high concentration region 12 and the back electrode 9 using the same material as the back electrode 9 in the same process as in the above-mentioned embodiment; may be separate items.

Further, although the above-mentioned embodiment shows an example in which the source electrode is removed, this does not prevent the source electrode from being provided on the source region for some reason. For example, in an integrated circuit device manufactured using the present invention, an electrode for connecting the source region and other regions may be provided on the surface.

As explained above, according to the present invention, it is easy to manufacture a field effect transistor, the manufacturing yield is improved, and the electrical characteristics and reliability are improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part for explaining a conventional field effect transistor, and FIG. 2 is a sectional view of a main part showing an embodiment of the present invention. In the figure, 1 is a semi-insulating or insulating substrate,
2 is an active layer, 3 is a gate electrode, 9 is a back electrode, 1
1 is directly below the gate of the active layer, 12 is a high concentration region,
Reference numeral 14 indicates a concave portion, and 15 indicates a bottom surface of the concave portion.

Claims (1)

[Claims] 1. An active layer formed on the surface of an insulating or semi-insulating substrate and made of a semiconductor having one conductivity type, and an active layer disposed on the active layer that causes a spot contact with the active layer. In a field effect transistor having a gate electrode and a high concentration region formed in an area of the active layer opposite to each other with a region immediately below the gate electrode in between and having a higher impurity concentration than directly below the gate electrode, One of the high concentration regions is connected to a back electrode disposed on the back surface of the substrate by a connecting conductor arranged so as to reach the bottom of one of the high concentration regions but not to reach the surface. Characteristics of field effect transistors.