JPS6230687B2 - - Google Patents
Info
- Publication number
- JPS6230687B2 JPS6230687B2 JP55143230A JP14323080A JPS6230687B2 JP S6230687 B2 JPS6230687 B2 JP S6230687B2 JP 55143230 A JP55143230 A JP 55143230A JP 14323080 A JP14323080 A JP 14323080A JP S6230687 B2 JPS6230687 B2 JP S6230687B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal wiring
- thin film
- tiw
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000010409 thin film Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 7
- 229910001120 nichrome Inorganic materials 0.000 claims description 7
- 239000010408 film Substances 0.000 description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の多層金属配線形成方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming multilayer metal wiring in a semiconductor device.
従来、半導体集積回路においては、シリコン基
板にトランジスタ、ダイオード、抵抗、容量等の
素子を形成し、これらの素子を例えばAlのよう
な金属膜で配線している。近年、集積度の増大が
ますます要求されてきて集積回路の素子数も増加
し、回路の複雑さに従つて配線の交叉が問題とな
つてきている。従来の配線方式であるとチツプサ
イズがますます大きなくり、歩留り、コストの面
で大きな障害となる。これをさけるために多層配
線方式が利用されている。 Conventionally, in semiconductor integrated circuits, elements such as transistors, diodes, resistors, capacitors, etc. are formed on a silicon substrate, and these elements are interconnected using a metal film such as Al. In recent years, there has been an increasing demand for increased integration, and the number of elements in integrated circuits has also increased, and as the circuits have become more complex, wiring crossovers have become a problem. Conventional wiring methods require increasingly large chip sizes, which poses a major hurdle in terms of yield and cost. To avoid this, a multilayer wiring system is used.
従来、この多属配線を行なう場合は、配線とし
て通常Al膜が用いられ、Al膜同士を直接に接触
させて電気的接続させていた。即ち、第１図に示
すように、シリコン基板１に保護被膜２を形成
し、これに既知の写真製版技術にて孔を形成す
る。そのあと電極および配線のため一層目のAl
膜３を形成する。次に一層目のAl膜３と二層目
のAl膜４がシヨートするのを防ぐための絶縁膜
５を形成し、所望の部分に孔を形成した後二層目
のAl膜４を形成する。 Conventionally, when performing this multi-metal wiring, an Al film was usually used as the wiring, and the Al films were brought into direct contact with each other for electrical connection. That is, as shown in FIG. 1, a protective coating 2 is formed on a silicon substrate 1, and holes are formed therein by a known photolithography technique. After that, the first layer of Al is used for electrodes and wiring.
A film 3 is formed. Next, an insulating film 5 is formed to prevent the first layer Al film 3 and the second layer Al film 4 from being shot, and after holes are formed in desired areas, the second layer Al film 4 is formed. .
従来はこのようにして多層配線を形成してお
り、一層目のAl膜３にシンター後ヒルロツク６
が生じ、このヒルロツク６から絶縁膜５にクラツ
クが生じたり、あるいはピンホールが出来たりし
て、一層目のAl膜３と二層目のAl膜４がシヨー
トするという問題点があつた。 Conventionally, multilayer wiring is formed in this way, and the first layer Al film 3 is coated with hillocks 6 after sintering.
This caused a problem in that the hillocks 6 caused cracks or pinholes in the insulating film 5, causing the first Al film 3 and the second Al film 4 to be shot.
本発明はかかる点に鑑みてなされたもので、基
板上に第１の金属配線として例えばAl膜を形成
した後、TiW又はNiCr薄膜を該Al膜を覆つて基
板上全面に形成し、しかる後これを熱処理し、そ
の後該TiW又はNiCr薄膜を除去して絶縁膜を介
して第２の金属配線を形成することにより、第１
の金属配線に生じるヒルロツクの発生を抑えて第
１、第２の金属配線がシヨートするのを防止で
き、かつ該第１、第２の金属配線が直接に接触し
て電気的接続した多層金属配線の形成方法を提供
するものである。 The present invention has been made in view of this point, and after forming, for example, an Al film as a first metal wiring on a substrate, a TiW or NiCr thin film is formed on the entire surface of the substrate to cover the Al film, and then This is heat-treated, and then the TiW or NiCr thin film is removed and a second metal wiring is formed through the insulating film.
A multilayer metal wiring that can suppress the occurrence of hillocks that occur in the metal wiring and prevent the first and second metal wiring from being shot, and in which the first and second metal wiring are in direct contact and electrically connected. The present invention provides a method for forming.
以下、本発明の一実施例を図に基づいて説明す
る。第２図ａ〜ｂは本発明の一実施例による多層
金属配線形成方法を工程順に示す。ここでは、第
１、第２の金属配線としてAl膜を用いている。 Hereinafter, one embodiment of the present invention will be described based on the drawings. FIGS. 2a to 2b show a method for forming a multilayer metal wiring according to an embodiment of the present invention in the order of steps. Here, an Al film is used as the first and second metal wirings.
まず、第２図ａに示すように、選択拡散領域を
有する半導体基板１表面に保護被膜２を形成し、
これに既知の写真製版技術にて孔を形成する。続
いて、Alを全面に蒸着し、既知の写真製版技術
にて一層目のAl膜３を形成する。次に、第２図
ｂに示すように、TiW薄膜７を全面に被着す
る。この膜厚は500〜1000Åに形成すれば十分で
ある。そして一層目のAl膜３とシリコン基板１
とのオーミツク接触をとるために400〜500℃、
N2中で熱処理を行なう。このとき、従来の方法
であると一層目のAl膜にヒルロツクが発生し、
これが一層目、二層目のAl膜をシヨートさせる
こととなるのであるが、本実施例のように一層目
のAl膜３の上にTiW薄膜を形成しておくと該Al
膜３でのヒルロツクの発生を抑えることができ
る。 First, as shown in FIG. 2a, a protective film 2 is formed on the surface of a semiconductor substrate 1 having a selective diffusion region,
Holes are formed in this by a known photolithography technique. Subsequently, Al is deposited on the entire surface, and a first layer of Al film 3 is formed using known photolithography techniques. Next, as shown in FIG. 2b, a TiW thin film 7 is deposited on the entire surface. It is sufficient to form this film with a thickness of 500 to 1000 Å. And the first layer Al film 3 and silicon substrate 1
400~500℃, to take ohmic contact with
Heat treatment is carried out in N2 . At this time, with the conventional method, hillocks occur in the first layer of Al film,
This will cause the first and second layers of Al film to be shot, but if a TiW thin film is formed on the first layer of Al film 3 as in this example, the Al film will be shot.
The occurrence of hillocks in the membrane 3 can be suppressed.
次に、熱処理後TiW薄膜７を除去する。これ
は例えばフレオン（CF4）ガスを用いたプラズマ
エツチにて行なうことができる。フレオンガスに
よるプラズマはAl膜３をエツチングすることは
ないので、TiW薄膜７を除去するために少しオ
ーバー気味にエツチングを行なつてもAl膜３が
エツチングさてれ変形するようなことはない。ま
たTiW薄膜７と保護被膜２、例えば酸化珪素膜
は反応し難いので、保護被膜２上に反応層が生じ
ることもなく、フレオンガスによるプラズマエツ
チでTiW薄膜７は完全に除去される。また仮に
少々反応層が出来たとしても、酸化珪素膜はフレ
オンガスによるプラズマでエツチングされるの
で、エツチング時間を長くすることによりTiW
薄膜７は完全に除去され得る。そして、このよう
にしてTiW薄膜７を除去した後、第２図ｃに示
すように、絶縁膜５を形成して所望の部分に孔を
形成した後二層目のAl膜４を形成すると、Al膜
３，４同士が直接に接触して電気的接続した多層
配線が得られる。 Next, after the heat treatment, the TiW thin film 7 is removed. This can be done, for example, by plasma etching using Freon (CF 4 ) gas. Since the plasma generated by Freon gas does not etch the Al film 3, even if the etching is slightly excessive in order to remove the TiW thin film 7, the Al film 3 will not be etched and deformed. Further, since the TiW thin film 7 and the protective film 2, for example, a silicon oxide film, hardly react with each other, no reaction layer is formed on the protective film 2, and the TiW thin film 7 is completely removed by plasma etching using Freon gas. Furthermore, even if a slight reaction layer is formed, the silicon oxide film will be etched by the plasma generated by Freon gas, so by increasing the etching time, the TiW
The thin film 7 can be completely removed. After removing the TiW thin film 7 in this way, as shown in FIG. 2c, an insulating film 5 is formed and holes are formed in desired areas, and then a second layer of Al film 4 is formed. A multilayer wiring in which the Al films 3 and 4 are in direct contact with each other and electrically connected is obtained.
このように本実施例では、エツチングの発生を
防止でき、しかもAl膜同士が直接に接触して電
気的接続した多層金属配線を得ることができる。 As described above, in this embodiment, it is possible to prevent the occurrence of etching, and moreover, it is possible to obtain a multilayer metal wiring in which the Al films are in direct contact with each other and are electrically connected.
なお、上記実施例では、Al膜上に形成する薄
膜をTiWからなるものとしているが、これは
NiCrからなるものであつてもよく、同様の効果
を奏する。 In the above example, the thin film formed on the Al film is made of TiW.
It may also be made of NiCr, and the same effect can be achieved.
また、上記実施例では、一層目の配線を形成す
る場合について述べているが、本発明は当然に、
三層や四層の多層配線構造における二層目、三層
目の配線を形成する場合にも適用でき、同様の効
果を奏する。 Furthermore, although the above embodiment describes the case where the first layer of wiring is formed, the present invention naturally
It can also be applied to forming second and third layer wiring in a three-layer or four-layer multilayer wiring structure, and similar effects can be achieved.
またさらに、上記実施例では一層目の金属とし
てAlを用いているが、Alと同様に熱処理後ヒル
ロツクが発生するものであれば他の金属に対して
も本発明の方法を有効に適用できるのは勿論であ
る。 Furthermore, although Al is used as the first layer metal in the above examples, the method of the present invention can be effectively applied to other metals as long as they cause hillocks after heat treatment like Al. Of course.
以上説明したように、この発明の多層金属配線
形成方法によれば、基板上に第１の金属配線を形
成後、該第１の金属配線を覆つて上記基板上全面
にTiW又はNiCr薄膜を形成して熱処理し、その
後該TiW又はNiCr薄膜を除去して絶縁膜を介し
て第２の金属配線を形成するようにしたので、ヒ
ルロツクの発生を防止して上記第１と第２の金属
配線がシヨートするのを防止でき、かつ上記第１
と第２の金属配線が直線に接触して電気的接続し
た多層金属配線を得ることができる効果がある。 As explained above, according to the multilayer metal wiring forming method of the present invention, after forming a first metal wiring on a substrate, a TiW or NiCr thin film is formed on the entire surface of the substrate, covering the first metal wiring. After that, the TiW or NiCr thin film is removed and the second metal wiring is formed through the insulating film, thereby preventing the occurrence of hillocks and allowing the first and second metal wiring to be connected. It is possible to prevent shooting, and the above-mentioned
There is an effect that it is possible to obtain a multilayer metal wiring in which the first metal wiring and the second metal wiring are in straight line contact and electrically connected.
第１図は従来の方法により形成された多層金属
配線を有する半導体素子を示す断面図、第２図は
本発明の一実施例による多層金属配線形成方法を
示す工程別断面図である。
図において、１はシリコン基板、２は保護被
膜、３，４はAl膜、５は絶縁膜、６はヒルロツ
ク、７はTiW薄膜である。なお図中同一符号は
同一又は相当部分を示す。
FIG. 1 is a cross-sectional view showing a semiconductor device having a multilayer metal wiring formed by a conventional method, and FIG. 2 is a cross-sectional view of each step showing a method for forming a multilayer metal wiring according to an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a protective film, 3 and 4 are Al films, 5 is an insulating film, 6 is a hillock, and 7 is a TiW thin film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
金属配線形成方法において、 基板上に第１の金属配線を形成する工程と、 上記第１の金属配線を覆つて上記基板上全面に
TiW薄膜又はNiCr薄膜を形成した後、熱処理す
る工程と、 上記TiW薄膜又はNiCr薄膜を除去する工程
と、 上記第１の金属配線上に絶縁膜を介し、かつ該
第１の金属配線と直接に接触して所望の電気的接
続を得るよう第２の金属配線を形成する工程とを
含むことを特徴とする多層金属配線形成方法。[Scope of Claims] 1. A multilayer metal wiring forming method for forming a multilayer metal wiring on a substrate, comprising: forming a first metal wiring on a substrate; all over the top
A step of heat-treating after forming the TiW thin film or NiCr thin film; A step of removing the TiW thin film or the NiCr thin film; forming a second metal interconnect so as to contact and obtain a desired electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14323080A JPS5766629A (en) | 1980-10-13 | 1980-10-13 | Formation of electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14323080A JPS5766629A (en) | 1980-10-13 | 1980-10-13 | Formation of electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5766629A JPS5766629A (en) | 1982-04-22 |
| JPS6230687B2 true JPS6230687B2 (en) | 1987-07-03 |
Family
ID=15333921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14323080A Granted JPS5766629A (en) | 1980-10-13 | 1980-10-13 | Formation of electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5766629A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232671A (en) * | 1975-09-08 | 1977-03-12 | Fujitsu Ltd | Manufacturing process of semiconductor device |
| JPS5467766A (en) * | 1977-11-10 | 1979-05-31 | Toshiba Corp | Semiconductor device |
-
1980
- 1980-10-13 JP JP14323080A patent/JPS5766629A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232671A (en) * | 1975-09-08 | 1977-03-12 | Fujitsu Ltd | Manufacturing process of semiconductor device |
| JPS5467766A (en) * | 1977-11-10 | 1979-05-31 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5766629A (en) | 1982-04-22 |
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