JPS6222490B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a switching signal generator for a stereo demodulator that reduces beat sound during stereo demodulation when receiving pilot tone FM stereo broadcasting. In FM stereo broadcasting, as shown in the spectrum diagram of the pilot tone stereo composite signal in Figure 1, the main signal is the sum signal (L+R) of the left channel and right channel (referred to as L and R, respectively), and the difference signal is It is well known that the main carrier is FM-modulated and transmitted using a composite signal in which (L-R) is carrier-suppressed AM modulated with a subcarrier of 38KHz, and a pilot signal of 19KHz, which is 1/2 of 38KHz, is added. It is as follows. Now, in recent years, in FM tuners, beat sounds during stereo playback due to adjacent station or intermodulation interference have been considered a problem, and a beat reduction stereo demodulator that electronically cancels this beat has been proposed. FIG. 2 is a block diagram of such a proposed beat-reducing stereo demodulator. Refer to the same figure. The received stereo composite signal is buffer-amplified by an amplifier 1 and input to switching circuits 2 and 12 which play the role of a decoder.
(sometimes abbreviated as VCO) 7. Frequency division block 1
8. A PLL circuit (PLL circuit) consisting of a 1/2 frequency divider 9 that divides the subcarrier frequency into 1/2, a phase comparator 4, a low-pass filter (hereinafter sometimes abbreviated as LPF) 5, and a DC amplifier 6. input to the aids control loop circuit). In this case, the DC amplifier 6 is not necessarily required. In this example, if the free run frequency of VCO7 is 228KHz, it becomes 76KHz with a 1/3 frequency divider of ₁₈₁ , and then becomes 76KHz with a 1/2 frequency divider of ₁₈₂ .
It becomes 38KHz, which is a subcarrier frequency. 1/2 frequency divider 18 The output of ₂ is further divided by a 1/2 frequency divider of 9 to 19KHz, which is input to the phase comparator 4 and synchronized with the pilot signal (19KHz) in the input composite signal. Then, the output of the ₁₈₂ frequency divider will reproduce the subcarrier synchronized with the input signal.
These subcarriers F ₁ (t) and F ₂ (t) become rectangular waves with a duty cycle of 50%, and when normalized and expressed as a Fourier series, they become as follows. F ₁ (t)=1/2+2/πcosω ₀ t −2/3πcos3ω ₀ t+2/5πcos5ω ₀ t−……
(1) F ₂ (t)=1/2-2/πcosω ₀ t +2/3πcos3ω ₀ t-2/5πcos5ω ₀ t+...
(2) However, ω ₀ is 2π×38KHz On the other hand, the outputs of the ₁₈₃ frequency divider that divides the output of VCO 7 by 1/2 are F ₃ (t) and F ₄ (t), F ₃ (t) = 1/2 + 2 /πcos3ω ₀ t −2/3πcos9ω ₀ t+ ...(3) F ₄ (t)=1/2−2/πcos3ω ₀ t +2/3πcos9ω ₀ t− ...(4). Assuming that the input composite signal includes an unnecessary spectrum with a frequency three times the subcarrier frequency, the composite signal is expressed by the following equation. (L+R)+(L-R) _cosω0t + _Pcosω0 /2t+xcos( _3ω0 ± _Δω1 )t (5) where P is the pilot signal level and x represents the amplitude of the frequency triple the subcarrier frequency. F ₁ (t) and F ₂ (t) are multiplied by a composite signal in the switching circuit 2. If we extract only the audio component of the output of switching circuit 2, we get (1)×(5)
From 1/2(L+R)+1/π(L-R)-x/3πcos
Δω ₁ t(6) (2)×(5) 1/2(L+R)−1/π(L−R)+x/3πcos
Δω ₁ t(7) In equations (6) and (7), the third term x/3π is output as an unnecessary beat sound. On the other hand, in the switching circuit 12, F ₃ (t), F ₄
(t) is multiplied by the composite signal, and the audio component of the output of the switching circuit 12 is obtained from (3)×(5): 1/2(L+R)+x/πcosΔω ₁ t (8) From (4)×(5): 1 /2(L+R)-x/πcosΔω ₁ t (9), and the second term includes a component of x/πcosΔω ₁ t (a signal three times as large as the unnecessary beat sound). Therefore, with 13 mixers, (6) + 1/3 x (8), (7) + 1/3
By mixing ×(9), (6)+1/3×(8), 1/2(L+R)+1/π(L-R)−x/3πcos
Δω ₁ t +1/3{1/2(L+R)+x/πcosΔω ₁
t} =2/3(L+R)+1/π(L-R) (10) From (7)+1/3×(9), 2/3(L+R)-1/π(L-R) (11) Become. Furthermore, (10)−2π−3/2π+3×(11),(11)−
If we do 2π-3/2π+3×(10), we get (10)-2π-3/2π+3×(11)=8/2π+3L(1
2) (11)−2π−3/2π+3×(10)=8/2π+3R(
13) The unnecessary beat sound is completely removed, and the L, R
signals are separated. The above is the operating principle of the beat reduction stereo demodulator shown in Fig. 2. In order to cancel the beat component caused by the third harmonic of the subcarrier and the frequency component around three times the subcarrier frequency included in the composite signal, , F ₃ (t) for F ₁ (t),
There needs to be a phase relationship of F ₄ (t) with respect to F ₂ (t). If this is reversed (F ₄ (t) for F ₁ (t), F ₃ (t) for F ₂ (t)), the beat component will not be canceled out but doubled. Also F ₁ (t), F ₂ (t) and F ₃ (t), F ₄ (t)
If there is a difference in transmission delay time (that is, a phase difference) between the switching waveforms, the amount of beat component cancellation, that is, the amount of beat cancellation, will be extremely degraded. Figure 3 is F ₁
The difference in delay time between (t) and F ₃ (t) and the deterioration in the amount of beat cancellation are calculated and illustrated. In this way, F ₁ (t), F ₂ (t) and F ₃ (t), F ₄ (t)
Always determine the phase relationship between F ₁
A frequency dividing circuit shown in FIG. 4 has been proposed in the past as a frequency divider circuit for reducing the delay time difference between (t), F ₂ (t) and F ₃ (t), F ₄ (t). In Fig. 4, the 1/3 frequency divider and 1/2 frequency divider are configured with master-slave JK flip-flops.
Table 1 shows the truth table of the master-slave JK flip-flop.

[Table] However, H indicates high, L indicates low, and × indicates that it does not depend on the input state. The signal waveforms of each part in FIG. 4 are shown in FIG. 4A.
Take the NAND (184) of the output of the JK flip-flop ₁₈₁₂ , which is one element constituting the 1/3 frequency divider, and the output of the 1/2 frequency divider ₁₈₂ , and calculate the output of _{183 .}
By inputting to the K terminal of the 1/2 frequency divider, 18
The phase of the output of the _3/2 frequency divider is determined. In addition, in order to match the delay time difference between the output of the 1/2 frequency divider ₁₈₂ and the output of the 1/2 frequency divider ₁₈₃ , the input of the CK terminal of the 1/2 frequency divider ₁₈₃ is delayed by the delay device ₁₈₅ . ing. The 1/3 frequency divider composed of JK flip-flops 18 ₁₁ and 18 ₁₂ is a synchronous type, so JK
The output of the flip-flop ₁₈₁₂ has a delay time of one flip-flop with respect to the output of the VCO. Since the output is input to the 1/2 frequency divider ₁₈₂ as a ripple type counter, the output of the 1/2 frequency divider ₁₈₂ has a delay time of two flip-flops with respect to the output of the VCO 7. On the other hand, 1/2 frequency divider 18
Since the output of ₁₈₃ has a delay time of one flip-flop with respect to the CK input of the frequency divider ₁₈₃ , the CK input of the 1/2 frequency divider ₁₈₃ is delayed by the delay time of one flip-flop. The output is delayed by a delay device of ₅ so that the output has a delay time of two flip-flops with respect to the output of the VCO 7. From the above, the output has a delay time variation of ±2 times, and has a delay time variation of up to 4 flip-flops. Furthermore, in the method of correcting the variation in the output with respect to the output using a delay device such as ₁₈₅ , it is difficult to establish a correlation between the variation in the delay time of the delay device and the variation in the delay time between the outputs, so it is preferable. do not have. If there is a variation corresponding to four flip-flops, the beat cancellation effect will be reduced as shown in FIG. 3, and the conventional circuit has the disadvantage that it is greatly affected by the variation in the delay time of the flip-flops. SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching signal generator for stereo demodulation, which eliminates the above-mentioned drawbacks of the prior art and is comprised of a frequency dividing logic circuit and has less variation in transmission delay time. The key point of this invention is to convert the frequency divider circuit to T-FF (T-FF).
It is basically configured with a flip-flop) and a D-FF, and a 1/6 frequency divider with a duty cycle of 50% and three 1/2 frequency dividers are synchronously divided by a clock based on the VCO oscillation frequency. R so that the phase relationship of each divided cycle output always maintains a predetermined relationship.
- By determining the phase relationship with a logic circuit such as an S latch, variations in transmission delay time can be suppressed. FIG. 5 is a circuit diagram showing an embodiment of the present invention. The flip-flop manufacturing process in the same figure can be TTL or C-MS, but here it can be constructed on the same chip as the bipolar IC.
The explanation will be based on the I ² L process. In Figure 5, 21, 22, and 23 are respectively
T-FF, 24, 26, 27 configured in I ² L format
are D-FF configured in I ² L format, and 25 is
This is an R-S latch constructed in the I ² L format, and the respective symbols are shown in FIG. 6, and the truth table is shown below. That is, in FIG. 6, a is the symbol of the R-S latch, b is the symbol of the T-FF, and c is the symbol of the D-FF. Table 2 is the symbol of the R-S latch, Table 3 is the symbol of the T-FF,
Table 4 shows the truth values of D-FF.

【table】

【table】

[Table] Regarding the inverter, which is the basic configuration of the I ² L circuit, its symbol is shown in FIG. 7a, and a specific example of the circuit configuration is shown in FIG. 7b. A feature of the I ² L circuit configuration is that connecting the outputs of two or more I ² L circuits creates a wired AND. Two circuits in which two inverters are connected in series are prepared, and the symbol of the circuit in which the output values are commonly connected is shown in FIG. 8a, and a specific example of the circuit configuration is shown in FIG. 8b. Even if two inverters are connected in series, it is logically equivalent to nothing. As shown in Figure 8b, the output side Z is constructed by commonly connecting the collectors of two transistors, and the output side Z terminal is only when the two output side transistors are off. It is at the logic "1" level. The truth table for inputs X, Y and output Z is shown in Table 5 below.

[Table] As shown in truth table 5 above, in the I ² L circuit,
It will be seen that simply connecting the output sides of these circuits in common results in a wire-and circuit. The circuit of FIG. 5 is written in this manner. Next, an explanation will be given using the RS latch as an example. R-
When the S latch is represented by an inverter, it becomes as shown in FIG. This can be easily expressed using a wired and notation as shown in Figure 9A.
In FIG. 9A, when S=1 and R=0, S=
= 1, the output of wired AND A ₁ becomes 1, the output of inverter I ₁ becomes 0, and Q is 0. At this time, since R = Q = 0, the output of wired AND A ₂ becomes 0. It can be seen that the output of the inverter _I2 becomes 1 and becomes as shown in the truth table of the RS latch shown in Table 2. Now, returning to Fig. 5, 28 is a buffer, and the output of VC (not shown) is added to this buffer.
228KHz signal is input. T-FF21,2
Duty cycle with 2, 23 and D-FF24
It constitutes a 1/6 frequency divider. A timing chart showing the operation of the circuit shown in FIG. 5 is shown in FIG. The output of the T-FF 23 becomes a pulse with a duty of 1/6, as shown in _Q3 in FIG. Also T
-FF21's ₁ , T-FF22's Q ₂ , T-FF2
The output obtained by taking the wired AND of 3 and ₃ becomes R ₅ in FIG. 10, which is a pulse with a duty of 1/6 and a phase different from Q ₃ by 180 degrees. By inputting these two pulses to the RS latch 25, a 1/6 frequency divided output _Q5 with a duty of 50% can be produced.
On the other hand, the output Q ₁ of T-FF21 and the output of D-FF24
By taking the wired and with ₄ , the first
0 figure D ₇ is obtained, and Q ₅ and D ₇ are 38K with fixed phase.
Hz and 114KHz signals. Next, Q ₅ and D ₇ are D-
If input is input to each D input terminal of FF 26, 27, and the output frequency of VCO is input to T terminal respectively, and the VCO frequency is used as a clock and delayed, each output Q ₆ , Q ₇ of D-FF 26, 27 will be as follows. Synchronous frequency division output with transmission delay time difference of 26 and 27
The switching signal has a delay time variation of D-FF±1. As explained above, according to the present invention, T-
By creating a synchronous frequency divider using FF, D-FF as the basic configuration, the switching signal of 38KHz
By always maintaining the desired phase relationship between D and 114KHz, the difference in transmission delay time of
- It was possible to have a variation in transmission delay time of FF±1. The transmission delay time of D-FF is about 1/2 of that of master-slave JK-FF, so the conventional variation, that is, master-slave
In this invention, the variation in delay time difference is reduced to 2 D-FF compared to 4 JK-FF, so the variation in delay time difference can be reduced to 1/4 of the conventional one. Furthermore, compared to the conventional example shown in FIG. 4, the number of required circuit elements can be reduced to about 70%. By making this circuit using the ^I2L process, it can easily coexist with other bipolar circuits on the same chip, making it possible to integrate a beat reduction stereo demodulator into an IC with a smaller chip area. Ta.

[Brief explanation of the drawing]

Figure 1 is a spectrum diagram of a pilot tone stereo composite signal, Figure 2 is a block diagram showing the configuration of a conventional beat reduction stereo demodulator that has been proposed, and Figure 3 is a diagram of 38KHz and 114K.
A graph showing the relationship between the delay time difference of the Hz switching signal and the amount of beat cancellation. Fig. 4 is a circuit diagram of a proposed conventional frequency division block for obtaining a switching signal. FIG. 5 is a circuit diagram showing one embodiment of the present invention. FIG. 6 is a block diagram showing symbols of various flip-flops used in the present invention. FIG. 7 is an I ² L circuit. 8 is a circuit diagram showing the inverter, which is the basic configuration of the inverter, FIG. Figure 10 is an equivalent circuit diagram that redraws Figure 9 to make it easier to understand.
This is a time chart of various signals in FIG. 5. Explanation of symbols, 1... Buffer amplifier, 2... Switching circuit, 3... Capacitor, 4... Phase comparator, 5
...LPF, 6...DC amplifier, 7...VCO, 9...1/2 frequency divider, 12...switching circuit, 13...mixer,
18... Frequency dividing circuit, 21, 22, 23... T-FF,
24...D-FF, 25...RS latch, 26, 27...
D-FF, 28...batshua.

Claims (1)

[Claims] 1 This is a signal generation device for switching the received stereo composite signal in the reception demodulator of FM stereo broadcasting using the pilot tone method, and the output frequency of the voltage controlled oscillator (hereinafter abbreviated as VCO) whose output frequency is a specific frequency. As a 1/6 frequency divider that divides the frequency by 1/6, the first, second and third
each T flip-flop (hereinafter abbreviated as T-FF) and the first D flip-flop (hereinafter referred to as D-FF).
A frequency divider is provided by interconnecting FF (abbreviated as FF),
The first output with a duty of 1/6 from the third T-FF output
By taking out the 1/6 frequency-divided output of the third T-FF, and taking the AND of the negative-phase output of the third T-FF, the negative-phase output of the first T-FF, and the output of the second T-FF. A second 1/6 frequency divided output with a duty of 1/6 which is 180° different in phase from the first 1/6 frequency divided output is obtained, and the two types of 1/6 frequency divided output are obtained.
The 6-divided output is input to the R-S latch to obtain a third 1/6-divided output with a duty of 50% from the latch, while the output of the first T-FF and the first D-FF are By taking the AND of the negative phase outputs, the third 1/
A 1/2 frequency division output with a fixed phase relationship with the 6 frequency division output waveform is obtained, and the third 1/6 frequency division output and the 1/2 frequency division output, which are R-S latch outputs, are respectively used as the second frequency division output. , 3rd
By inputting it to the D terminal of the D-FF and delaying the frequency of the VCO output as a clock, synchronized 1/6 frequency divided output and 1/2 frequency divided output are obtained as switching signals. A switching signal generator for stereo demodulation.