JPS62224042A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve space utilizing efficiency in a gate array IC while maintaining the order of wiring and adaptability for automatic design of wiring for the gate array IC, by separating circuit elements and wirings as an upper part and a lower part via a surface insulating film. CONSTITUTION:An internal circuit part 2 wherein arbitrary logic circuits are constituted, a peripheral circuit part 3 and a terminal pad part 4 are arranged in a gate array IC. The internal circuit part 2 is largly apportioned to the central part of a semiconductor substrate 1, which a large number of basic cell arrays 5 are arranged in the internal circuit part 2. Each basic cell array 5 is arranged in parallel with one another, and respective wiring regions 7 of specified width are arranged between the respective basic cell arrays 5. a wiring region 7 shown in a shadowed portion is separated to an upper part and a lower part via a surface insulating film of the semiconductor substrate 1. The wiring is formed on the surface insulating film, while the circuit elements, for example, a bypass condenser, are formed under the film.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to semiconductor integrated circuit technology, and furthermore, to technology that is effective when applied to gate array LSIs (large-scale integrated circuit devices), such as bipolar and B i -CMO8 type gate array I combined with C-MOS
This article relates to techniques that are effective for use in C.

[Conventional technology]

Gate array ICs (semiconductor integrated circuit devices) are, for example, published by Nikkei Electronics 19 published by Growhill Publishing Co., Ltd.
June 3, 1985 issue 1151-177 negative (commentary: 1000
Gate arrays, which are about to become a billion yen market, are devices that realize desired circuit functions by arbitrarily wiring a large number of circuit elements prepared in the form of bases on a semiconductor substrate. Therefore, it is also called a so-called semi-custom IC.

Here, the present inventor has proposed a layerer l! of the gate array IC described above. I considered aK. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

Figure 6 shows a gate array IC considered by the present inventor.
The layout configuration is shown below.

The gate array IC shown in the figure is provided with an internal circuit section 2, a peripheral circuit section 3, and a terminal pad section 4, which constitute an arbitrary logic circuit network.

The internal circuit section 2 is largely allocated to the center of the semiconductor substrate 1. A large number of basic cell arrays 5 are arranged in this internal circuit section 2 . Each basic cell array 5 is arranged parallel to each other. Along with this, each basic cell array 50 has a predetermined width. A viewing area 7 is provided.

The basic cell array 5 has a large number of basic cells 6 arranged in one direction (in the row direction in the figure). In each basic cell 6, circuit elements for forming a logic gate are formed in advance in the form of a semiconductor base. The type and number of circuit elements formed in each basic cell 6, their arrangement, etc. are standardized in advance.

On the other hand, an external gate array 8 is provided in the peripheral circuit section 3 . This external gate array 8 is an arrangement of a large number of input/output buffer sections 9. In each input/output section 9, circuit elements sufficient to arbitrarily configure any one of an input buffer circuit, an output buffer circuit, or an input/output buffer circuit are formed in advance in the form of a semiconductor base. A terminal pad section 4 for bonding is provided outside the input/output buffer section 9.

In the gate array IC described above, in particular, by providing wiring regions 7 between each basic cell array 7,
Wiring between the basic cells 6 can now be performed in an orderly manner, thereby making it easier to automate wiring design using, for example, CAD (computer-aided design system). This wiring design occupies a very large proportion of the initial cost of the gate array IC. Improving the suitability for automating the wiring design brings significant advantages in terms of reducing the design cost of gate array ICs.

[Problem that the invention seeks to solve]

However, the inventors have found that the above-mentioned technique has the following problems.

That is, the wiring area 7 described above is essential for improving the orderliness of the wiring in the gate array and the suitability for automation of its design, but on the other hand, the wiring area 7
The inventors have found that the problem is that the space occupies a large proportion of the overall layout space, reducing the effective layout space that can actually be used to form circuit elements. It was done.

An object of the present invention is to improve the efficiency of space utilization in a gate array IC while maintaining the orderliness of wiring in the gate array IC and the suitability for automation of wiring design, thereby substantially reducing the layout space available for forming circuit elements. This technology provides a technology that allows users to increase their productivity.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, wiring between basic cells is formed on the surface insulating film of the portion forming the wiring region of the gate array, while circuit elements such as bypass capacitors are formed under the surface insulation.

[Effect]

According to the above-described means, the circuit elements and the wiring are distributed vertically by the optical surface insulating film, so that they can be formed independently without interfering with each other. As a result, while maintaining the orderliness of the wiring in the gate array IC and the suitability for automation of self-destructive design, the efficiency of space utilization in the gate array IC is increased, and the layout space that can be used for forming circuit elements is substantially reduced. The purpose of this is achieved: to increase the number of employees.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows the layout configuration of a gate array IC to which the technology according to the present invention is applied.

The gate array IC shown in the figure first includes an internal circuit section 2, a peripheral circuit section 3, and a terminal pad section 4, each of which constitutes an arbitrary logic circuit network.

The internal circuit section 2 is largely allocated to the center of the semiconductor substrate 1. In this internal circuit section 2, a large number of basic cell arrays 5 are arranged. Each basic cell array 5 is arranged parallel to each other. Along with this, a forest area 7 having a predetermined width is provided between each basic cell array 5. This wiring area 7 ensures the orderliness of wiring and suitability for automation of wiring design.

The basic cell array 5 has a large number of basic cells 6 arranged in one direction (in the row direction in the figure). In each basic cell 6, circuit elements for forming a logic gate are formed in advance in the form of a semiconductor base. The type and number of circuit elements formed in each basic cell 6, their arrangement, etc. are standardized in advance. In this case, in the gate array IC of the embodiment, although not shown in the drawings, a bipolar element for forming the output stage of the logic gate and a C-MO8 element for forming the logic circuit section are combined in each basic cell 6. It is formed in the form of a semiconductor base.

On the other hand, an external gate array 8 is provided in the peripheral circuit section 3 . This external gate array 8 has a large number of input/output sections 9 arranged therein. Each Ota Kabak 7A Division 9 includes:
Circuit elements that can arbitrarily configure any one of an input buffer circuit, an output buffer circuit, or an input/output buffer circuit are formed in advance in the form of a semiconductor base.

A terminal pad section 4 for bonding ink is provided on the outside of the input/output pad 77 section 9.

Here, in the gate array IC of the embodiment, although the details will be described later, the wiring region 7 indicated by diagonal lines in FIG. 1 is divided into upper and lower portions by the surface insulating film of the semiconductor substrate l. Then, wiring is formed on the surface insulating film, and circuit elements such as bypass capacitors are formed under the surface insulating film.

FIG. 2 shows a part of the basic cell array 5 shown in FIG. 1.

In the figure, wiring between basic cells 6 is performed by multilayer wiring. In this case, the column direction is made by the first-layer aluminum wiring A12, the row direction is made by the second-layer aluminum wiring A12, and the connection between both wirings Al1 and A12 is made by the through-hole arrangement tjlTH.

Above the basic cell array 5, there is 1! Source VCC and ground potential G
The wiring connected to each ND is connected to the right side by the second layer aluminum wiring Al. In addition, wiring area 7
Above, the first and second layer aluminum wiring #A71 and #A12 are wired in the row and column directions.

FIG. 3 shows a cross-sectional state of a part of the basic cell 6, and corresponds to the section AA in FIGS. 1 and 2.

In the figure, the semiconductor substrate 1 of the gate array IC of the embodiment is a p-type silicon semiconductor substrate IO on which an epitaxial layer is formed. This semiconductor substrate IK has an element formation region formed by an n-type buried layer 11 and an n-type well diffusion layer 12, and an isolation region formed by a p-type isolation diffusion layer 13 and a p-type well diffusion layer 14.

In the element formation area in the basic cell 6, there are two bipolar
A transistor Qlj Q2 is formed. Each bipolar transistor Ql, Q2 has a p-type base diffusion layer 15, an n+ type emitter diffusion layer 16, and an n+ collector connection diffusion layer 17, respectively.

Furthermore, a surface insulation M18 made of an oxide film is formed immediately above the semiconductor substrate 1. On this surface insulating film 18, a first layer of aluminum wiring 100°100'ρ is formed. Furthermore, on the surface insulating film 18 and the first layer of aluminum arrangement 100°100', there is glabellar insulation g! 19 is formed.

Then, on this interlayer insulating film 19, a second layer of aluminum arrangement 101, 101' is formed.

On the other hand, in the wiring region 7, the surface insulating film 18 of the semiconductor substrate 1
Wiring Al l, A for connecting between the basic cells 6 on the top
12 is formed, and at the same time, circuit elements are formed under the surface insulating film 18. As the circuit elements, in the embodiment, an n+ type buried layer 11 and an n type well diffusion layer 12 are formed under the surface insulating film 18. The n-type buried layer 11 and the n-type well diffusion layer 12 in this wiring region 7
is the n+ type buried layer 11 forming the collector region of one bipolar transistor Q1 in the basic cell 61111.
and n-well diffusion layers 12, respectively.

Here, as shown in FIG. 4, two bipolar transistors Ql are formed between the basic cells 6.

When the output stage of the logic gate is constructed by connecting Q2 in series in a totem pole type between the power supply Vcc and the ground potential GND, as shown in FIG. The n-type diffusion 1-12 has a junction capacitance f (Cp) with respect to the p-type silicon semiconductor substrate 1,
This junction capacitance (Cp) comes to act as a bypass capacitor Cp that is equivalently connected in parallel between the power supply VCC of the output stage and the ground potential GND. That is, in the arrangement region 7, the wirings All and A12 for connecting the basic cells 6 are formed on the surface insulating film 18.
Its surface insulation g! Bypass capacitors Cp as circuit elements are formed below 18 without interfering with each other. Moreover, since the bypass capacitor Cp can be formed in a large area over almost the entire layout space of the wiring region 7, it can stabilize the operation of a logic gate (macrocell) arbitrarily configured using the basic cell 6. It can have a sufficiently large capacity.

As described above, by distributing the large capacitance bypass capacitor Cp, which is a circuit element, and the wiring AJI, 12 vertically by the surface insulating film 18, they can be formed independently without interfering with each other. Be able to do things. As a result, while maintaining the orderliness of wiring in the gate array IC and suitability for automation of wiring design,
The objective is to increase the efficiency of space utilization in the gate array IC so that the layout space available for forming circuit elements can be substantially increased.

FIG. 5 shows another embodiment of the invention.

In the embodiment described above, the bypass capacitor Cp, which is a passive element, is formed in the wiring region 7, but as shown in FIG. can also be formed. In this case, the active element region 20A of the wiring region 7.

20B and 20C are formed under the surface insulating film, and are connected to wiring on the surface insulating film via through-hole wiring as necessary.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, a resistance element may be formed by a diffusion layer formed under the surface insulating film 18 of the wiring region 70.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the Bi-0MO8 type gate array IC, which is the field of application that formed the background of the invention.
For example, it is not limited to micro-
It can also be applied to random logic ICs such as processors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, while maintaining the orderliness of the wiring in the gate array IC and the suitability for automation of the wiring design, the efficiency of space utilization in the gate array IC is improved, and the layout space available for forming circuit elements is substantially increased. The effect is that

[Brief explanation of drawings]

FIG. 1 is a plan view showing the layout configuration of a gate array IC to which the technology according to the present invention is applied, FIG. 2 is a plan view showing an enlarged part of FIG. 1, and FIG. 2
FIG. 4 is a diagram showing an equivalent circuit of the portion shown in FIG. 3, FIG. 5 is a diagram showing another embodiment of the present invention, and FIG. FIG. 2 is a plan view showing a layout configuration of a gate array IC that was studied prior to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Internal circuit section, 3... Peripheral circuit section, 4... Terminal pad section, 5... Basic cell array, 6... Basic cell, 7... Wiring Area, 8...
External gate array, 9...Person output 3777 parts, 10...
... p-fJi silicon semiconductor substrate, 11... n-type buried island, 12... n-type well diffusion layer, 13... p-type isolation diffusion layer, 14... p-type well diffusion layer , 1B...
Surface insulating film (surface oxide film), 19... interlayer insulating film, A
ll...1st layer aluminum wiring, A12...2
Layer aluminum wiring, Vc c ... ML m,
GND-...Ground potential, Ql, Q2...Bipolar transistor for configuring the output stage, Cp...
- A bypass capacitor as a circuit element formed in the wiring area 7. Agent: Patent Attorney Katsuo Ogawa 1st
Figure P Figure 5

Claims (1)

[Claims] 1. A basic cell array formed by arranging basic cells in one direction on which circuit elements for configuring logic gates are formed on a semiconductor substrate, and a plurality of basic cell arrays are arranged in parallel to each other. A semiconductor integrated circuit device in which a wiring area of a predetermined width is provided between each basic cell array, and the wiring area is for connecting basic cells on a surface insulating film of a semiconductor substrate. 1. A semiconductor integrated circuit device characterized in that wiring is formed thereon, and circuit elements are formed under a surface insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein a diffusion layer forming a bypass capacitor is formed as a circuit element under the surface insulating film in the wiring region.