JPS62183222A - Parallel type analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain the result of conversion with high accuracy even if the specific accuracy of a voltage dividing resistor is not excellent and an offset voltage is in variance by providing a means selecting a voltage in response to each comparator among plural voltages and inputting the voltage to respective comparators. CONSTITUTION:Voltages Vn1, Vn2,..., Vnm are voltage division voltages divided minutely, they are inputted to a demultiplexer DEMn, one of them is selected as an output 3 of the demultiplexer. The output 3 is given to an inverting input of a comparator Cn. On the other hand, a median voltage-division voltage Vnc of the voltage-division voltage or an input voltage Vin is connected selectively through a switch Sn1 or a switch Sn2 to a noninverting input of the comparator Cn. The output of the comparator Cn is given to a logical gate Gn and the signal from the gate and a clock signal CK are ORed and an OR signal between the clock signal CK and the comparator output signal is inputted to a counter COUNTn. An output 4 the counter COUNTn becomes a logical input to the demultiplexer DEMn.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an analog-to-digital converter that converts an analog signal into a digital signal, and particularly relates to a parallel type or series-parallel type converter that enables highly accurate encoding. It relates to an analog-to-digital converter (hereinafter referred to as an A/D converter).

[Background of the invention]

Parallel A/D converters have been known as ultra-high-speed A/D converters. For example, there is a "blinking type analog-to-digital converter" disclosed in Japanese Patent Application Laid-Open No. 58-104527.

To explain a parallel type A/D converter using an 8-bit case as an example, as shown in FIG.
56 comparators (Cz=Czsa) are used to divide the two reference voltages V rexH and V rotl using 255 voltage dividing resistors (R4-Rx5a) to generate 256 divided voltages. The 256 comparison results are encoded into an 8-bit signal by an encoder circuit 1 and outputted by an output circuit 2. This A/
In order for the D converter to have good accuracy, it is necessary that (1) the voltage dividing resistor has good specific accuracy, and (2) the offset voltage of the comparator does not vary. However, these methods have a problem in that their accuracy is limited because they vary due to variations in transistor processing and process variations.

[Purpose of the invention]

An object of the present invention is to provide a parallel A/D converter that can obtain accurate conversion results even when the offset voltage of the comparator varies and the ratio accuracy of the voltage dividing resistor is poor.

[Summary of the invention]

In order to achieve the above object, the present invention increases the number of voltage dividing resistors several times compared to the number of comparators.

Means for correcting the offset variation of each comparator and the error in the voltage division ratio of the voltage dividing resistor by selecting an appropriate divided voltage from among these many divided voltages and using it as the divided voltage for each comparator. has been established. It has become clear that this makes it possible to realize a highly accurate parallel A/D converter.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

In this embodiment, a circuit is configured to correct the variation particularly when the offset voltage of the comparator has a large variation. FIG. 2 shows a circuit that selects one divided voltage from among a large number of divided voltages and applies it to a comparator. In Fig. 2, V n1 @ Vnzt..., ■0
．． are detailed divided voltages, these divided voltages are input to the demultiplexer OEM, and one of them is selected as the output 3 of the demultiplexer.

This output 3 is connected to the inverting input terminal of the comparator Cn. On the other hand, the non-inverting input terminal of the comparator C1 receives the center divided voltage V n c or the input voltage V t through the switch Sni or the switch Sn2.
n are selectively connected. The output of the comparator Cn is connected to a logic gate Gn, and this signal is logically summed with the clock signal GK, and the logical sum signal of the clock signal CK and the comparator output signal is input to the counter C0UNT. The output 4 of the counter C0UNT becomes the logic input of the demultiplexer DEMn.

FIG. 3 shows an example in which a parallel A/D converter is constructed using the comparator with the demultiplexer described above. In the case of an 8-bit parallel A/D converter, 256 comparators are used, and each of these comparators is provided with a demultiplexer.

The divided voltage that becomes the input of the demultiplexer may or may not be shared with the demultiplexer inputs of several adjacent comparators. In Fig. 3, the divided voltage V++s+ Vl[l, Vl? , Vta is shared by demultiplexers of adjacent comparators.

Next, a method in which the offset voltage Vos of the comparator C11 is canceled out by a comparator with a demultiplexer will be explained using FIG. This comparator has two operating modes. In other words, the 6 calibration mode, which is the calibration mode and the comparison mode, is an operation mode that finds a divided voltage that cancels the offset voltage of the comparator, and the comparison mode uses the divided voltage found in the calibration mode to calculate the input voltage and the divided voltage. The 0 calibration mode, which is an operation mode in which piezovoltages are compared and normal A/D conversion is performed, can be performed when the power is turned on, prior to the comparison mode, or periodically while the A/D converter is operating. It's okay. In the latter case, drifts in offset voltage due to temperature fluctuations can also be absorbed.

The calibration mode will be explained using FIG. In the calibration mode, the non-inverting input terminal of the comparator is connected to the central divided voltage V n c of the divided voltages by the switch Snl. Also, at the beginning of the calibration mode, the counter is reset, so the demultiplexer divides the voltage V n 1 g V
Outputs the lowest voltage among n Z t...vn. That is, the center divided voltage V u C is applied to the non-inverting input terminal of the comparator, and the lowest divided voltage is applied to the inverting input terminal. If the offset voltage of the comparator is zero, the output of the comparator will be at a high level. Next, when a clock signal is applied to the GK terminal, since the comparator output is at a high level, the gate Gn
is open and the clock is input to the counter. The value of the counter increases every clock, so the output voltage of the demultiplexer, that is, the voltage at the inverting input terminal of the comparator increases every clock.If the offset voltage of the comparator is zero, then the inverting input terminal When the voltage exceeds the central divided voltage, the output of the comparator changes to a low level, the gate On closes, and the value of the counter does not change any more. Comparator offset voltage Vos
If is not zero, the voltage at the 1 inverting input terminal is equal to the center divided voltage and the offset voltage V. When the voltage exceeds the sum of S,
The output of the comparator changes to low level and the gate G.

is closed and the counter value does not change any further. The digital value left in the counter by the above operation becomes a value that applies the sum of the center divided voltage and the offset voltage of the comparator to the inverting input terminal of the comparator. (Of course, since it is a digital value, it includes an error for the minimum unit of the divided voltage.) Therefore, from the perspective of the non-inverting input terminal, this comparator means that the input voltage of the non-inverting input terminal is greater than the center divided voltage. It looks like a comparator that inverts depending on whether it is small or small. In other words, it becomes an ideal comparator with no variation in offset voltage of the comparator.

(To be precise, this means that the offset voltage variation of the comparator has been reduced to the minimum unit of the divided voltage. However, this holds true because the input voltage of the demultiplexer is smaller than the maximum value of the offset voltage variation. (This is the case when the divided voltage is wide.) In Figure 3, in the calibration mode, switch 5nr (n = 1 to 2
56) and turn on the switch Sn! (n=1°~256)
It is possible to find a divided voltage that cancels out the variations in the offset voltage of each comparator by turning off each comparator at the same time. The state of applying this divided voltage is stored as a digital value in each counter.

After that, in the comparison mode, the switch Snl is turned off and the switch Sn2 is turned on (n=1. to 256), and the input voltage vtn is applied to the non-inverting input terminal of each comparator. Since a divided voltage that cancels out the offset voltage of each comparator using the digital value stored in the counter is applied to the inverting input terminal of each comparator, the overall A/D conversion result is free from errors due to offset voltage variations. t: Being ignored.

2) The circuit configuration for correcting the variation in offset voltage of the comparator when the variation is large has been described with reference to FIG. 2 and FIG. 73.

The method of canceling out errors using a comparator with a demultiplexer as described above can be further extended to a circuit configuration that corrects for poor ratio accuracy of the voltage dividing resistor to obtain a highly accurate conversion result.

FIG. 4 is a drawing showing this embodiment. The configuration of FIG. 4 differs from that of FIG. 3 in the following two points. (1) Enable terminal for each comparator (CE+, Ct: 2.
..., Cl': zsa) is provided, and when in the calibration mode, external data input (Dl, Dz,...) is provided.

[] 6) allows only one comparator designated through the decoder DEC to operate. (2)
A switch Snl,
5n2L was not provided, and it was connected directly to the input terminal vIn. Other configurations are shown in Figures 2 and 3.
Same as the figure.

Next, the operation of the embodiment shown in FIG. 4 will be explained.

This A/I converter also has a calibration mode and a comparison mode, as in the previous embodiment. Similarly, in the comparison mode, the divided voltage found in the calibration mode using the digital value stored in the counter is applied to the inverting input terminal of each comparator. The difference in operation lies in how the divided voltages are found in calibration mode. In the previous embodiment, in the calibration mode, the corrected partial voltage was found using the voltage generated by the A/D converter itself.

In this embodiment, in order to find the corrected divided voltage, an analog voltage serving as a reference and a digital code corresponding thereto are applied from the outside.

The calibration mode will be explained in detail as follows.

For calibration, a highly accurate D/A converter as a reference is required outside this A/D converter. First, digital codes such as '00...00' are converted into data manually (DI).

.

Inside the A/D converter, the digital code is 100...O
O', only one comparator designated by the decoder DEC, in this case Cx21g, operates. In this state, the corrected divided voltage corresponding to the comparator CxIIs is found in the same manner as in the previous embodiment. That is, the counter is reset and the lowest divided voltage is applied to the inverting input terminal of the comparator. Next, when a clock is applied, the voltage at the inverting input terminal increases every clock. Since the reference analog voltage is applied to the non-inverting input terminal of the comparator through the input terminal Vln, the counter stops rising when the voltage at the inverting input terminal exceeds the sum of the reference analog voltage and the offset voltage. At this time, when viewed from the non-inverting input terminal, this comparator appears to be a comparator that inverts depending on whether the voltage at the non-inverting input terminal is larger or smaller than the reference analog voltage. In other words, it becomes an ideal comparator without variations in the offset voltage of the comparator and variations in the ratio accuracy of the 1-voltage resistor.

Next, the digital code is increased by one, the corresponding analog reference voltage is applied from the input terminal V, and the corrected divided voltage of the comparator corresponding to this digital code is found. In this way, the corrected divided voltage of each comparator can be found in turn. The accuracy of this A/D converter is the accuracy of the external reference D/A converter plus an error equal to or less than the minimum unit of the divided voltage due to the voltage dividing resistor. Accuracy is good if it is made small enough.

In addition, in Fig. 4, each comparator is provided with an enable terminal so that only one comparator is selected by inputting data from the outside, but it is also possible to provide an enable terminal on the counter so that only one counter operates. Alternatively, it is also possible to connect the output of the decoder DEC to the gate Gr so that only one counter operates.

Further, a new data input terminal may be provided for inputting digital data from the outside, but there is a problem that the number of input/output pins becomes too large. Therefore, the increase in the number of input/output bins can be prevented by switching the data output terminal of the A/D converter to be used as a digital data input terminal during the calibration mode.

The circuit configuration for correcting a case where the voltage dividing resistor has poor relative accuracy and the comparator has a large offset voltage variation has been described above.

Note that in the two embodiments described above, the voltage at the inverting input terminal is gradually increased in the calibration mode, but the circuit may be configured so that the voltage is gradually decreased. In this case, it is necessary to reverse the polarity of the comparator or insert an inverter before the gate.

In the above, it has been explained that a comparator with a demultiplexer is used in a parallel type A/D converter, but can the comparator with a demultiplexer described in the first embodiment be used directly in a separate type A/D converter? A high-precision A/D converter can be realized.

Furthermore, even if the comparator with a demultiplexer of the present invention is used as the comparator of a successive approximation type A/D converter using voltage dividing resistors, a high-precision A/I converter that cancels out the offset voltage of the comparator can be realized. Further, the present invention provides analog/digital (hereinafter referred to as A/
In particular, it is possible to provide a parallel type high-speed A/1) converter with 11 speeds and suitable for integrated 48 circuits.

Conventionally, high-speed parallel A/D converters have
I11'158-1045274) D description, Jl:
UNI, base fQ4'RFF, wo The voltage output by the reference voltage voltage divider that divides the voltage into 2N minimum conversion units (LSB) and the human analog voltage are compared in magnitude at the same time using the 2N voltage ratio 91H. , the comparison results were encoded to obtain digital output. Figure 5 shows; bit (N=
This figure shows one of the known examples of the aη array type AID converter in case 3). This 3-bit parallel A/D converter has a reference voltage divider 10. Voltage comparators 31-38. Latch circuit 41-482 position detection theory J! 1 circuit 51-57,
The 6 reference voltage dividing book 1o, which is composed of an encoding circuit 60 and an output circuit 7o, divides the reference voltage section ■1 to G into eight ■SB by 2a=8 voltage dividing resistors 11 to 18. do. The operation of this 3-bit A/D converter is as follows. The voltage comparators 31 to 38 simultaneously compare the input voltage vtn with respect to the different divided voltage outputs 21 to 28 of the reference voltage voltage divider 10. The comparison outputs of the voltage comparisons 31 to 38 are #Q II when the input terminal V + n is larger than a certain point of the divided voltage outputs 11 to 18 of the reference voltage voltage divider 10;
Conversely, when it is small, it L II is output and taken into the latch circuits 41 to 48. The comparison result taken into the latch circuits 41-48 is used to detect the boundary between 5'1'' and o'' by the position detection logic circuits 51-57. The encoding circuit 6o encodes the detected result into a 3-bit Gray code or binary code, and outputs it to the outside via an output circuit.

As a result, a 3-bit digital output including an overflow code 84 is obtained. By the way, the 3-bit A/D converter shown in FIG. S operates with a clock φ.

FIG. 6 is a transfer chart of clock φ and comparison data. The voltage comparator outputs comparison data; Dk when the clock φ is at a high ()Ihigh) level. The latch circuit takes in comparison data; Dk when the clock is at a high level.

In this way, the final stage digital output is obtained when the operation lock φ of the output circuit 70 is at the old gh level.

As described above, the conversion speed of the parallel A/D converter is determined by the operating speed of logic circuits such as voltage ratio comparators and latch circuits. Therefore, the conversion speed of the conventional parallel A/D converter has been limited to the operating frequency of the clock φ, which is determined by the operating speed of the voltage comparator and the like.

The present invention provides a high-speed parallel A/D converter that has double the conversion rate without changing the clock frequency of the A/D converter.
A conversion device can be provided.

That is, in the present invention, a new reference voltage terminal is drawn out between each voltage dividing resistor of the reference voltage voltage divider in the opposite direction to the lead line of the existing reference voltage terminal, and the comparison with the input voltage is performed.

It has now become clear that it is possible to realize a high-speed A/D converter that operates at double the conversion rate without changing the clock frequency of the A/D converter.

An embodiment of the present invention will be described below with reference to FIG.

Similarly to FIG. 5, FIG. 7 also shows an example of 3 bits. FIG. 7 shows a reference voltage divider 10, voltage comparators 331 to 38. Latch circuits 41-482 position detection logic circuits 51-57. The parallel A/D converter of the encoding circuit 60 includes voltage dividing resistors 11 to 18 of the reference voltage voltage divider 1o.
Another divided voltage output is taken out in the opposite direction from intermediate points 21' to 28', and new voltage comparators 31' to 38', latch circuits 41' to 48', position detection logic circuits 51' to 57'
.

An encoding circuit 60' is added and the output of the encoding circuit 60.60' is input to an output logic circuit 70'. The voltage comparators 31 to 38 receive the input voltage ■ when the clock φl is at the 11iHh level. The voltage comparators 31' to 31'
38' is designed to compare with the input voltage ■In when the clock φ2 is at the old gh level. FIG. 8 shows a transfer chart of clock waveforms and comparison data. φl is Hi
The comparison data Dk obtained by the voltage comparators 31 to 38 when the clock waveform is at the 1IiHh level is taken into the latch circuits 41 to 48 and encoded to obtain the digital value shown in (a). On the other hand, the comparison data D obtained by the voltage comparators 31' to 38' when φ2 is at the old [h level]
Is k+t a clock? When z is at a high level, it is taken into the latch circuits 41' to 48' and encoded to obtain the digital value shown in (b). Here, k in the figure is a natural number, (Q) is ±2j (i; natural number), and (b) is ±(2
i −1,). By the way, (a).

The digital value in (b) has the analog/digital conversion characteristics shown in FIG. Now the output logic circuit 70 in FIG.
By providing a selection circuit for digital values (a) and (b) at ', different conversion characteristics can be selected at will.

Also, φ1. With φ2 as a reverse phase clock, the output logic circuit 7
0' output rate is φ1. If it is twice φ2, the 8th
The digital output is shown in the figure (c), and the conversion rate is φ!
, φ2 can be obtained. The digital output obtained here has different conversion characteristics (a) and (b)
are output alternately. By the way, voltage comparator 3 in FIG.
If the comparators shown in FIG. 10 are used for 1' to 38', the conversion characteristic will be only (a), and the conversion rate φ1. φ2
You can get an A/D converter that is twice as large as the one above. The comparator of FIG.
2 instead of VL and ■δ to the input capacitor C, effectively v2. This is a comparator that determines which comparison to perform. Thereby, the human voltage VTLL can be compared simultaneously by the two voltage comparator groups 31 to 38 and 31' to 38'. Conversely, if the same comparators as shown in FIG. 11 are used as the voltage comparators 31 to 38, the conversion characteristic becomes (b
) only.

On the other hand, when φl and φ2 are in-phase clocks, (a),
The digital values of (b) are simultaneously input to the output logic circuit 70'. Figure 11 shows φ1. A transfer chart of clock types and comparison data when φ2 is in phase is shown. At this time (a),
The minimum unit in (b) is shifted by -LSB as shown in FIG. The output logic circuit 70' can expand the number of conversion bits from 3 bits to 4 bits based on the digital values of (a) and (b). Therefore, the digital output (c) in FIG. 11 is a 4-bit output Dk.

As described above, according to the present invention, A/D conversion data with different conversion characteristics can be selectively obtained, and a function is added to the output logic circuit to further separate the least significant bit from two data with different conversion characteristics. By doing this, A/D converted data extended by 1 bit can be obtained. Furthermore, by providing the voltage comparator with an offset voltage of 1/2 LSB, it is possible to operate at twice the conversion rate compared to conventional conversion.

FIG. 12 shows another embodiment of the parallel A/D converter according to the present invention. Both ends 101 of the reference voltage circuit 10. .

Operational amplifiers 61 and 62 were added to 102. The operational amplifier 61 is grounded by the clock φ3, and the bias voltage V is connected to the T crystal.
It is connected to B and applied to the 101 end. The operational amplifier 62 is connected to the reference voltage VR at clock φ3, V2 at $3, and applied to the 102 terminal. The input voltage is also connected to the voltage comparators 31-38 and 31'-38' via the switch 73. The voltage comparators 31 to 38 and 31' to 38' are the same comparator.

A FOR circuit was used for the position detection circuit shown in FIG.

The operation of this 3-bit parallel A/D converter is as follows: switches 71.62 of operational amplifiers 61.62. ．． 72 and the input voltage connection switch 73 can be turned on and off in the same manner as in FIG. First, switch 71A.

72A is always fixed in the on state, and 71B and 72B are fixed in the off state. At this time, the clock φ and φ4 are in phase,
The output digital value with φ2 having the opposite phase is obtained as shown in FIG. 8. Next, clock φ1. φ2. φδ is in the same phase, the input voltage connection switches 73A and 73B are always on, and the voltage on one input side of the operational amplifier 61 is V.
If the voltage on one input side of B=-LSB (V)-62 is VR' = VR+LSB (V),
The obtained digital value has the A/D conversion characteristic shown in FIG. 9(a). Further, the output rate of the digital value is twice the rate of the clock φ1. At this time, the output logic circuit 70' is capable of outputting at rays 1 to 2 times the clock φ1. Also, switches 7+A and 72A are always on, 7113.72
1 (is always fixed in the off state, switches 74A and B are always fixed in the on state, and when the clocks φ1 and φ2 are in phase, the digital output shown in FIG. 11(c) is obtained.
At this time, the output logic circuit 70' outputs 3 pins 1 to (a),
It has a function that can be expanded from (b) to 4 bits.

In FIG. 13, a switch 71' and a resistor 90 are connected to both ends of the reference voltage divider circuit 10 instead of an operational amplifier. 1, which is an example of an embodiment in which a switch 72' is added, one end 101 of the reference voltage voltage dividing circuit 10 is connected to ground via a switch 71', and the intermediate point 21' of the voltage dividing resistor 11 is also connected to 71' via a resistor 90. 9 connected to ground, while 102 is a switch 72'
J reference voltage V R via the midpoint 28 of the voltage dividing resistor 18
' is also connected to the group 'Q pressure Vr+ via 72'. Both the switches 71' and 72' have a clock φ3. It is turned on and off at 〒8. This base is 1! The A/D conversion operation and function in the case of using the voltage divider circuit are the same as those in the embodiment shown in FIG.

〔Effect of the invention〕

As explained in detail above, according to the first embodiment, a highly accurate A/D converter can be realized even by using a comparator with a large offset variation, and according to the second embodiment, the offset variation can be reduced. Even if a large comparator is used and the specific accuracy of the voltage dividing resistor is poor, it is possible to obtain a highly accurate A.
The parallel type A/D converter of the present invention is particularly effective in terms of high precision, such as realizing a /D converter.

Further, according to the present invention, a new reference voltage point is drawn in the opposite direction from the conventional example from the intermediate point of each voltage dividing resistor that constitutes the reference voltage voltage dividing circuit of the parallel type A/D converter, and a new A/D converter is D
Configure the conversion device. This makes it possible to selectively obtain digital data with different conversion characteristics by using control signals and output logic circuits. Furthermore, high-speed conversion is now possible at a conversion rate twice the control signal frequency. Furthermore, the present invention has great effects, such as being able to increase the conventional resolution by 1 bit, and providing a multi-functional, high-speed parallel A/D converter by using only one device. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram explaining a conventional parallel A/D converter,
Fig. 2 is a circuit diagram showing a comparator with a demultiplexer of the present invention, Fig. 3 is a circuit diagram showing a parallel A/D converter using a comparator with a demultiplexer, and Fig. 4 is a circuit diagram showing a comparator with a demultiplexer. A circuit diagram showing another embodiment of a parallel type A/D converter, FIG. 5 is a conventional parallel type A/D converter.
6 is a diagram showing a time chart of the parallel type A/D converter of FIG. 5, and FIG. 7 is a diagram showing the configuration of the parallel type A/D converter of the present invention. Figure 8 is a diagram showing a time chart when different conversion characteristics are output alternately according to the present invention, Figure 9 is a diagram showing different conversion characteristics, and Figure 10 is a diagram showing two reference voltages manually. By doing this, we can effectively convert the comparative soft criterion into two inputs based on 1! FIG. 11 is a diagram showing a comparator that can be used as the midpoint of the tonnage pressure. FIG. 11 is a diagram showing a time chart when the conversion rate is twice the control signal in the present invention. FIG. 12 is a diagram showing one implementation of the present invention. FIG. 1:3 is a diagram showing an example in which both ends of the voltage divider circuit of FIG. 12 are constructed with a switch and a resistor. 1... Encoder circuit, 2... Output circuit, 3...
Demultiplexer output, 4...Counter output, Cn
...Comparator, G II...Logic gate, C0U
NT, . . . counter, DEM, . . . demultiplexer, 10 . . . groups 11 Rtl! Voltage dividing circuit, 11-1
8.11' to 18'...divider resistance. 21 to 28, 2], ' to 28'...each reference voltage point, 7
31~38.31'~38'...voltage comparator, 41~
4.8.41'-48'...Latch circuit, 51-57
．． 51' to 57'...Position detection circuit, 60°60'
... Encoding circuit, 61.62 ... Operational amplifier 70.7
0'...Output logic circuit, 71 to 73.71'. 72'...Switch, 75.76...Switch, 8
1~84.81'~84'...Digital output terminal, 9
0...Resistance, 91-97.91'-97'...1-OR circuit, Lot, 102...Reference voltage divider circuit terminal.

Claims (1)

[Claims] 1. In a parallel type or series-parallel type A/D converter consisting of a voltage dividing resistor that generates a plurality of divided voltages, a plurality of comparators, and an encoder circuit, the plurality of divided voltages are A parallel A/D converter comprising means for selecting one voltage from among the divided voltages according to each of the comparators and inputting the selected voltage to each of the comparators. 2. In the parallel type A/D converter of item 1 above, a selection circuit consisting of a demultiplexer and a counter is provided as means for selecting one voltage from the divided voltages. D converter. 3. In the parallel type A/D converter of item 1 above, means for selectively inputting one value of the input voltage of the A/D converter or the divided voltage to the other input terminal of the comparator. A parallel A/D converter characterized by being provided with. 4. In the parallel A/D converter described in item 2 above, one of the comparators (or counters or demultiplexers) is specified from the outside, only the specified comparator and demultiplexer are operated, and the portion corresponding to the comparator is A parallel A/D converter characterized in that it is provided with means for selecting a piezoelectric voltage. 5. Voltage dividing means for generating a plurality of first reference signals, a plurality of first interval comparators for determining the magnitude relationship between the plurality of reference signals and the analog input signal, and a plurality of the interval comparators. a plurality of first section detection circuits receiving the outputs of the section detection circuits; a first encoding circuit receiving the plurality of outputs of the section detection circuits;
a plurality of second interval comparators that generate a plurality of second reference signals from respective intermediate points of the voltage dividing means and determine a magnitude relationship between the plurality of second reference signals and the analog input signal; , a plurality of second interval detection circuits receiving the plurality of outputs of the second interval comparators; a second encoding circuit receiving the plurality of outputs of the plurality of second interval detection circuits; an output logic circuit receiving the outputs of the plurality of encoding circuits and the outputs of the second plurality of encoding circuits, the first plurality of interval comparators and the second plurality of interval comparators A parallel A/D converter, characterized in that the comparison results are outputted alternately or simultaneously, and the comparison results or logic results of the first and second interval comparators are outputted alternately or simultaneously in the output logic circuit. 6. A parallel A/D converter according to claim 5, characterized in that means for applying different voltages to both ends of the voltage means is provided.