JPS6190396A - Dynamic mos memory circuit - Google Patents

Abstract

PURPOSE:To transfer data between a memory array and buffer without a drop of memory cell potential by driving a switching part for connecting the memory cell array and buffer with the aid of a control signal having the potential lower than that of a power supply. CONSTITUTION:Transistors Q1 and Q2 of the switching part 21, which connects memory cells and the buffer part 31 for storing temporarily the data of bit lines 51 and 61 of said cells, are driven by a control signal which is lower than the power supply potential VCC, for instance the control signal S1 which rises only to a potential of a threshold voltage Vr obtained by subtracting Q1 from the power supply voltage VCC. Accordingly, the discharge of electric charge due to the parasitic capacity existing in a MOS transistor circuit of the buffer part 31 will not occur at the bit lines 51 and 61 until the potential of a nodal point 7 comes to the value obtained by subtracting the voltage Vr from the voltage of the signal S1. Thus, the data can be transferred between the memory cell array and buffer without the drop of the memory cell potential due to the discharge.

Description

[Detailed description of the invention] [Field of use in sedentary work] The present invention relates to a dynamic MOS memory circuit (2).

[Conventional technology]

FIG. 1 is a block diagram of a serial access type dynamic MOS memory circuit. Data for one word line of a memory group (hereinafter referred to as a memory cell array) 1 (including n sense amplifiers) is temporarily stored in a buffer section 6 via a switching section 2 . The buffer section 6 is
n buffers 31 t 3 equal to the number of sense amplifiers in memory group 1! r...

64, each bit line (5
s, 6s), (5ko, 6go),...e(5n+
6n) data in each buffer 5t l 6M +...
, island (2).Furthermore, from the decoder section 4:2, the buffer 6s + 3*r...+
6m sequentially and connect them to the pass lines I10 and I
connecting to lo (from 2, each buffer?n +
6z +...l The data stored in 3tl can be output to the outside at high speed.

FIG. 2 shows a set of switching circuits 21° buffer 61 . 4 is a diagram showing a decoder circuit 41. FIG.

The switching circuit 21 consists of switching transistors Ql, (h) controlled by a control signal St,
Controls the transfer of data on bit line 51.6t to buffer 61. The buffer 61 includes a buffer charging transistor Qs, which is controlled by a control signal Stl2.
Q4 and a transistor Q that forms a flip-flop and uses a data latch controlled by the data latch signal S3.
i and Qa, and temporarily stores data from bit line 51.6+.

The decoder circuit 45 is controlled by the decode signal S4 and transfers the data stored in the buffer 61 to the path line I10.
, Ilo, and Qs.

Next, the operation of the circuit shown in FIG. 2 will be explained in detail with reference to the drawings.

Since the sensing operation of dynamic RAM is well known, a detailed explanation thereof will be omitted.

Therefore, after the sensing operation is completed, that is, the bit line 51.
The operation after the left title position of 61 has been sufficiently determined will be explained. , FIG. 6 is a timing chart for explaining data transfer from the pits R51, 61 to the buffer capital 61. After the sensing operation, the potential of the bit line 51 becomes the power supply potential Vcc,
Assume that the magnetic potential of the bit line 61 has become the ground potential Ov. At this time, the control signal S2 is already set to a potential higher than the power supply potential Vcc plus the threshold voltage of the switching transistor Q3 or Q4, and therefore the nodes 7 and 8 are both at the power supply potential VCC. is being charged. When charging is completed, the control signal S2 is dropped to the ground potential Ov. After this, the control signal S1 rises from the ground potential Ov to the power supply potential VCC.

This (2) Therefore, the switching transistor (h-Q2
turns on. Node 7 is charged to power supply potential VCC, and bit line 5 is also at the same potential, so there is no charge movement. Node 8 is also charged to power supply potential VCC, but since bit line 61 is at ground potential Ov, switching transistor Q! turns on, and the charge at node 8 moves toward bit line 6i. The shifted weight flows out to the ground point of the sense amplifier of the memory cell array 1. Therefore, the first position of the marked point 8 eventually becomes the ground potential Ov. When the potential difference between nodes 7 and 8 is sufficient, the control signal Sl is dropped from the power supply potential VCC to the ground potential Ov.

Switching transistors Ql and Qz are turned off, and memory cell array 1 and buffer 61 are separated.

Thereafter, when the data latch signal S1 is fixed to the ground potential Ov, the bit line 5! .

The data from 61 will be radiated.

Here, the operation of the flip-flop constituted by the transistors Qs #Qs i will be described in detail.

As mentioned above, the control signal S: is (power supply potential VCC)+
When the node 7°8 is at a potential higher than the threshold voltage V of the switching transistor Qa (or Q4), the node 7°8 is at the power supply potential Veet. Therefore, the transistor Qs = the gate ()X position of Qs is the power supply potential vcc. At this time, since the data latch signal Ss is in a floating state, the first position of the data latch signal S3 is connected to the power supply potential VCC through the transistors Qs and Qg.
It is charged to a magnetic potential that is equal to or less than the threshold voltage Vτ of the transistor Qs or Q6.

The control signal S2 is dropped to the ground potential 0Vt, and the switching transistor Q! due to the rise of the control signal S1! ,Q
* is in the on state (when it becomes 2, the node 7 is the power supply potential Vcc, and the '1st level of the node 8 is falling, so the transistor Q6 is always in the on state, and the floating potential of the data latch signal SS also becomes the node 8 through the transistor Q6. Therefore, the gate potential and source potential of the transistor Qa fall almost simultaneously, so the transistor Qs is always in an off state.Therefore, the movement of charge from the node 7 is as follows. Therefore, the abdication of node 7 is ideal (maintaining the power supply potential VCC').

However, in a transistor with an MO8 structure, there is a parasitic capacitance due to the overlap between the gate electrode, source, and drain diffusion layers, which cannot be ignored. This parasitic capacitance exists between nodes 7 and 8 as a capacitance C1 For example, the parasitic capacitance CI due to this overlap and the capacitance of node 7 (mainly transistors Q+, Qs, Qs,
If the capacity ratio with Qy (diffusion capacity) is 1=5, mark point 8
When oscillates from the power supply potential 5V to the earth potential Ov,
In response to this amplitude, the potential at the riij point 7 drops by 1v from the low source potential of 5v to 4v. At this time, since the control signal S1 has risen to the 4-source potential vcc, the potential of the node 7 (switching transistor Q1, Qx case)
4th place - level of threshold voltage Vt);
discharges the electric charge. As a result, the low level of the bit line 51 is lowered, which ultimately lowers the potential of the memory cell array 1.
There is a drawback that the potential of the memory cell array 1 is lowered by transferring the data of 1.61 to the buffer 61.

Up until now, we have explained data transfer from the bit line side to the hardware side, but we will briefly explain the case of data transfer from the buffer side to the bit line side.In this case,
First, the flip-flop (=data) is transferred from the pass line I10 via the transistor Qγ+Qa.Here, if high level data is written to node 7 and low level data is written to node 8 (explained using two bit lines) 5
s and 6+ are charged in advance to the voltage source potential VCC. When the control signal S1 rises from the ground low level Ov to the power supply level Vcc, the transistor Q6 turns on because the node 7 is at a high level (2), and the charge on the bit line 61 is transferred to the control signal S3 via the transistors Q* and Qs. flows into the ground point of the generation circuit, and eventually the potential of the bit line 61 becomes the ground potential Ov.The electric charge of the bit line 51 is ideal (= maintains the vertical potential VCO.

However, in this case as well, due to the influence of the parasitic capacitance at existing between the nodes 7 and 8, when the potential of the control signal S1 is raised to the power supply potential VCC, the potential of the bit line 51 is lowered and the memory cell array 1 is The disadvantage is that the potential decreases. Also, when the high level originally input to node 7:2 is lower than (power supply potential VCC - voltage Vt to the threshold voltage of switching transistor Q1) (= means that the charge is discharged from the bit line 5). This has the disadvantage that the high level ultimately written into the memory cell is reduced.

[Problem that the invention seeks to solve]

In conventional dynamic MOS memory circuits, when data is transferred from the memory cell array to the buffer or from the buffer to the memory cell array (2. The effect of parasitic capacitance existing in the MO8 structure transistor circuit of the buffer (2), the potential of the memory cell is There was a drawback that it decreased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic MOS memory circuit that can transfer data from a memory cell array to a buffer or from a buffer to a memory cell array without lowering the memory cell's potential.

[Means for solving problems]

The present invention provides a dynamic MOS memory circuit consisting of a memory cell array, a buffer section, and a switching section, in which a control signal of a potential lower than the power supply potential is applied to the gate of a transistor in the switching section, and the switching section is activated. drive

〔Example〕

8 Examples of the present invention will be described with reference to the drawings.

In this embodiment, in the dynamic MOS memory circuits shown in FIGS. 1 and 2, the control signal 81 is
The switching transistors Qs and Qz are driven by raising the potential only to a potential lower than the power supply magnetic potential VCC. For example, if the control signal 81 is raised only to the potential of (power supply potential vcc - threshold voltage of the output transistor of the control signal Sl), the potential of the node 7 is (potential of the control signal 81 - transistor Bit f= until the threshold voltage of Q!
%I5+.

No discharge of charge from 61 occurs. Therefore, there is no drop in the potential of the memory cell, which occurs when the control signal S+ is raised to the power supply potential vcc.

Transfer of data from memory cells to buffer 61 and (
For any of the data transfers from the two buffers 61 to the memory cells, there is no lowering of the memory cells.

〔Effect of the invention〕

In the dynamic MOS memory circuit according to the invention, a control signal of the second order, which is lower than the second order, is applied to the gate of the transistor in the switching section, and the switching section is actuated, thereby controlling the 'magnetic field' in the memory cell. Data can be transferred between the memory cell array and the buffer section without deterioration in performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a serial access type dynamic MOS memory circuit, and FIG. 2 shows a set of switching circuits 21. FIG. 3, which shows the buffer 6+ and the decoder circuit 41, is a timing chart for explaining data transfer from the pit line to the buffer section. DESCRIPTION OF SYMBOLS 1... Memory cell array, 2... Switching part, 6... Buffer part, 5, 6... Pit line, Qt, Qx... Switching transistor, Ss... Control signal.

Claims (1)

[Scope of Claim] A memory cell array having a plurality of bit lines, a buffer section for temporarily storing data on each bit line of the memory cell array, and a method for transferring data from the memory cell array to the buffer section; In a dynamic MOS memory circuit including a switching section for connecting the memory cell array and the buffer section when transferring data from the buffer section to the memory cell array, a control signal having a potential lower than a power supply potential is provided. A dynamic MO, characterized in that the switching section is driven by applying the voltage to the gate of the transistor of the switching section.
S memory circuit.