JPS6166292A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain a high-speed operation of a bipolar RAM by giving the prescribed control to the base of a current changeover switch transistor of a memory cell and writing the information to the memory cell while only a word line is selected. CONSTITUTION:When a word line W and a pair of data lines D and D' are selected, a selected memory cell MC is read out to supply the read information Di and Di' to a writing circuit WA. Then a write enable signal WE is supplied to the circuit WA, and the circuit WA supplies the reference voltage and the control voltage lower than the reference voltage to the bases of memory cell current changeover switch transistors Q5 and Q6 respectively. Thus the cut-off and cut-on states are reversed between the TRQ1 and Q2 forming an FF of the cell MC. Then the information is written to the cell MC in a selection mode of a word line only. The amplitude of the word line is reduced to shorten the rise time. This ensures a high-speed operation of a bipolar RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor integrated circuit technology and also to semiconductor storage devices. Regarding.

[Background Art] For example, the applicant previously proposed a circuit as shown in FIG. 1 as a data write circuit in a static RAM (random access memory) whose memory cells are flip-flop circuits made of bipolar transistors. (Patent Application No. 58-151551).

In the figure, an example of a read circuit SA and a memory cell MC is shown along with a write circuit WA. That is,
In this circuit, word line W, data line, D
In the non-selected state, the memory cell M is
Data is held by pulling C and causing standby current Ist to flow. At this time, memory cell MC
One of the internal nodes n1 or n2 has a high level V
c, and the other is set to a low level Vcm.

At the time of reading, the write enable signal W1 externally input to the write circuit WA is set to a high level, so that the transistor Q w 1 forming the current switch circuit of the write circuit WR is turned on, and the emitter follower transistor Q The base potential of W 41 Q w B is brought to a level determined by the voltage drop across resistor R3.

As a result, the voltage from the emitters of the transistors Q W 4 and Q W s to the node nl+n2 in the memory cell MC at an intermediate potential between the levels VC u and V c □ is used as the reference voltage V r e f to It is supplied to the bases of transistors Q3 and Q4, which are connected to Ql and Q2 to form an ECL circuit.

Therefore, by the word line drive transistor Qx,
The word line W is raised to a potential higher than V c 1, and the Y switch YS is activated by the output signal Y of the Y decoder.
When turned on, the constant current source I2 is connected to the data line by the circuit 3, D is drawn, and the base sg voltage V is output from inside the memory cell MC.
A current flows from the node n, which has a higher potential than r e f, to the data line iD, and a current flows to the other data line 100 from within the readout circuit SA through the transistor Q3.

At this time, since the transistor Q4 is cut off, the readout circuit SA
The readout circuit SA detects whether current flows from inside the
Transistor Qs1. Complementary read data D O * D O is outputted from the emitter of Qs2 and supplied to an output buffer circuit (not shown) 6 On the other hand, in data writing, the word line driving transistor Qx first changes the potential VX of the word line W to the second level. As shown in the figure, the voltage is increased from VXL to vXR. Then, the standby current Ist is increased accordingly,
Potential Vc1 of node n1yn2 in memory cell MC,
Vcm is also increased, and Vcl is the read reference voltage V r e
higher than f.

Vc(, is raised to a lower level than this.

Subsequently, when the complementary data line D is selected by the Y decoder, the potential of the data line D falls from high level to low level, and accordingly, the potential of node n1tn2 in memory cell MC also decreases to some extent. Although it decreases, the reference voltage V
A read state is set in which r e f is intermediate between the two potentials.

Furthermore, during writing, the transistor Q W 1 is cut off by setting the write enable signal WE externally supplied to the writing circuit WA to a low level. Therefore, when the word line W is set to the selection level VXR and the potential of the node n1wn2 is raised as described above, the complementary input data Di and Di° formed based on the data input from the outside are , is supplied to the base of the transistor QW2 + 0w3 which is connected in an emitter couple with the transistor Qw1 in the write circuit WA. Then, current flows only through the transistor with the higher base potential and not through the other transistor, causing the emitter follower transistor Qw4 y Qw
Only one base potential of 6 is made lower than that at the time of reading. As a result of this, the emitter voltages of transistors Qw4 and Qw6 are the same voltage (VW
R), and the other voltage becomes a voltage WL lower than the lower potential Vcm in the memory cell.

Therefore, for example, assuming that input data Di and Di are supplied such that the base potential of the transistor Q w 6 becomes low while the potential of the node n1 is higher than the potential of the node n2, the transistor connected to the data line Q4
A voltage VWL lower than the potential Vcm of the node n2, which provides the base potential of the transistor Q1 in the memory cell connected to the data line, is applied to the base of the transistor Q1. Therefore, a collector current begins to flow through transistor Q, and the potential at node n decreases, so that the base potential of transistor Q2 decreases and shifts toward cutoff.

Then, the collector current of transistor Q2 decreases and the potential of node n2 increases. When the potential of node n2 increases, the collector current of transistor Q2 further increases, causing inversion of the flip-flop circuit.

As described above, in the bipolar static RAM of FIG. Q2 and ECL
Transistor Q3 constituting the circuit. By supplying one base of Q4, the flip-flop was inverted and data was written into the memory cell. Therefore, in the dedicated system as described above, transistor Q3.
The low write voltage vwL applied to the base of Q4 is made lower than the potential vco of the lower node in the memory cell. In other words, the word line selection level (high level)
Let VXR be VxR-VWL>ΔV c □
It is necessary to satisfy the following condition: (= V x RV c □).

In addition, in the case of the above write operation, transistors Q3 and Q4
The write voltage VvL applied to one base of the memory cell MC is connected to the same data line D as the memory cell MC, and the word line is set to a non-selection level (low level) VXL, so that the memory cell MC is brought into a non-selected state. If the potential becomes lower than the potential of a node in a memory cell that is selected, there is a risk that unselected memory cells will also be inverted and erroneously written. To prevent this, transistor Q3. The voltage VWL applied to the base of Q4 must satisfy the condition that it is higher than the non-selection level VXL of the word line, that is, VWL - VxL, )0.

The above two conditional expressions, V x H-V W L, >ΔVc
.

By adding V w L −V X L, > O, the conditional expression regarding the word line amplitude ΔV
==VxR-VXL>ΔVc□ is obtained.

As can be seen from this conditional expression, the bipolar static RAM to which the conventional writing method is applied requires a very large word line amplitude.

Furthermore, if the amplitude of the word line is large, the amplitude of the data line must also be large. As a result, the inventors have found that there are problems in that the rise time of the word line becomes longer, which impedes the speeding up of the memory, and the noise margin of the cell decreases because the drive amplitude of the memory cell is large. revealed.

[Object of the Invention] An object of the present invention is to provide a bipolar static RAM that can be increased in speed.

Another object of the present invention is to provide a bipolar static RAM with good memory cell noise margin.

The above-mentioned and other objects and novel features of the present invention will become clear from the description of Book 1 of the present invention and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in bipolar static RAM,
For example, a flip-flop circuit having a Schottky barrier diode and a resistor connected in series with the Schottky barrier diode is used as a memory cell.

By applying a voltage higher than the read reference voltage to the base of a similar transistor connected to the complementary data line and provided separately from the transistor to which the read reference voltage is applied during reading, the selected data line is selected. By inverting the stored memory cells to allow data to be written to them.

This achieves the above object of improving access time and memory cell noise margin by making it possible to reduce the amplitude of the word line.

The present invention will be described in detail below along with examples.

[Example] Figure 3 shows an example of the circuit configuration of the main part when the present invention is applied to a bipolar static RAM. It is formed on a single semiconductor substrate such as.

As one of the memory cells MC is shown as a specific circuit, the collector is connected to the word line W through load resistors R4 and R5, and the base and collector are connected to each other in a crosswise manner. Wired drive transistor Q
1. Schottky barrier diodes 5BD1, 5BD2 connected in parallel with Q2 and E load resistors R4, R5.
This and resistors R6 and R7 connected in series constitute a flip-flop circuit.

The drive transistors Ql and Q2 have a multi-emitter structure, although not particularly limited, and one emitter is shared and connected to a constant current source 1 through which a standby current 1st flows. The other emitters of the transistors Ql and Q2 are connected to a pair of data lines (or digit lines) D, respectively.

Connected to D.

The transistor Q1. A load resistance R is placed on the collector of Q2.
4. Schottky barrier diode 5B in parallel with R5
A memory cell structure in which D1-3BD2 and resistors R6 and R7 are connected has already been proposed by the applicant. By adopting such a memory cell structure, the holding current 1st during standby (holding state)
miniaturization and faster readout are possible.

That is, in the memory cell having the structure shown in FIG. 1, when the read current Ir is increased in order to increase the read speed, the base current of the transistor Q2 (Ql) increases and the higher side node nz The potential of (R2) decreases, and when it decreases to a certain level, the potential is clamped by the Schottky barrier diode SBD 1 (S BD 2 ), making it impossible to obtain a sufficient read level difference. On the other hand, in the memo cell (FIG. 3) having the structure as in the above embodiment, the resistor R6 (R) is connected in series with the Schottky barrier diode S B D 1 (S B D 2 ). , a sufficient readout level difference can be obtained even when a large readout current Is is applied.
In addition to reducing power consumption by reducing t, the ratio between read current Ir and standby current Ist is increased to enable faster readout.

A plurality of similar memory cells are arranged in the horizontal direction around the memory cell MC shown as a representative, with the word line W in common.

Multiple similar memory cells are also arranged vertically along the data line.
They are arranged with D in common. m in two columns and rows like this
A memory array M-ARY is configured by arranging Xn memory cells in a matrix.

The word line W shown as a representative is selected/unselected by a word line drive transistor Qx operated in response to an X address decode signal X. This X
Address decode signal X is formed by an X decoder X-DEC which decodes address signal Ax supplied from a suitable circuit device not shown.

A pair of data @D, D is connected to a constant current source I2+13 provided in common to other data lines via a transistor Q y e Q y as a column switch. The constant current source I2*I3 has a constant voltage V B 2 applied to its base, and an emitter resistor Re2. Re3
The transistor QiztQi3 is provided with a transistor QiztQi3.

A decode signal Y formed by a Y decoder Y-DEC that decodes an address signal Ay supplied from the appropriate circuit device (not shown) is applied to the base of the transistor Q y r Q y.

In this embodiment, although not particularly limited, a fifth-order circuit is provided to apply a predetermined bias voltage to the data line when not selected.

That is, a diode [)to and a resistor R1° connected in series are provided between the base and collector of the transistor QIO whose collector is grounded.

The series diode D1o and the resistor R1° are connected to a constant current source 4 via a transistor Q20 similar to the column switch transistor Qy + Qy. The emitters of the transistors Q10 are connected to the complementary data lines D, respectively.

Therefore, the transistor Qzo has a multi-emitter structure or is composed of two transistors each having a common base and collector.

On the other hand, a minute constant current source l6yI6 is provided at one end of the pair of data lines (the upper end in the drawing). That is, a transistor Q3oyI6 receiving a constant voltage V a 4 is provided.
Q31 and its emitter resistor Re4°Re5 constantly sink a minute constant current. This results in
The data line potential when not selected is biased by approximately the sum of the forward voltage Vf of the diode DIO and the base-emitter voltage vE of the transistor QIO.

Further, the constant current source (4) includes transistors Q22 to Q2 to which a predetermined bias voltage vB5 is applied to the base.
4 are provided respectively. This bias voltage Vo
5 is set slightly lower than the selection level of the Y address decode signal Y.

Therefore, when switching the column switch, complementary data I! When D and D are switched to other data lines (not shown) and the decode signal Y becomes lower than the voltage V e 5, the transistors Q y + Q7 and QI
O is turned off and transistors Q2□ to Q24 are turned on, so that the previously selected data line, D
The current 1r is cut off. Next, decoding (when the i-signal Y becomes higher than the voltage Vs5, transistors Q2□ to Q24 are turned off, and the column switch Q V t Q )' of the next selected data line is turned on.

This prevents the constant current ■r from flowing between the two data lines under the current distribution ratio according to the address decode signal level. Therefore, in this example:
A half-selected state of data lines does not occur.

In order to read data held in the memory cells, the pair of data lines D is provided with current changeover switch transistors Q3 and Q4 whose emitters are coupled. These transistors Q3. The collector output signal of Q4 is transmitted to the input of sense amplifier SA.

Although not particularly limited, the sense amplifier SA is composed of the following circuit elements.

A transistor QS11Q receives a constant voltage -1s1 ・Rs 3 formed by a resistor Rs 3 through which a constant current 1s1 flows.
A constant current source Is2 is provided at each emitter of S2. And each two ructor has a resistor Rs1
．． Rs2 is provided.

The above transistor Q3. The collectors of Q4 are respectively connected to the emitters of the transistors QSIIQSZ. The collector output of the transistor QSzrQS2 is transmitted to the base of the transistor Qss +Qs4, and the emitter of these transistors QS3t Qs4 is connected to a level shift diode DS1eD.
s2 and constant current source Is3 are provided in series.

The diode Ds1. The output level through Ds2 is
The constant current Isl,
Is2 and resistances Rs□ to Re3 are set.

Note that the above 1 to transistor Q3. The base of Q4 is connected to the levels Vcm and Vcm of nodes n1 and n2 in the memory cell at the time of reading, which are formed in the reference voltage generation circuit VRG.
An intermediate voltage V r e f is applied.

In this embodiment, the transistors Q3 and Q4 are
Similarly, a current switching transistor Q5 whose emitter is connected to the complementary data line D and constitutes an ECL circuit with transistors Ql and Q2 in the memory cell.
and Q6 are provided. The bases of the transistors Q5 and Q6 are connected to a write base P! supplied from the write circuit WA.
A constant voltage w is applied. In addition, this write circuit WA forms a write voltage V W L at a level lower than the read base ((1! voltage V r e f ) and a write voltage v wH higher than this in response to the external input data Di, Di. Thus, it can be supplied to the bases of the transistors Qs and Qe.

The write circuit WA is, for example, as shown in FIG.

It is configured.

That is, this write circuit is provided with a shrink circuit 4 that cuts noise in the write enable signal WE supplied from the outside and generates a stable signal, and generates a signal that is in phase with the write enable signal output from the shrink circuit 4. WEI is multi-emitter transistor Q30
is supplied to. The pair of emitters of this transistor Q3゜ includes a differential amplifier stage DA0 and an emitter follower EF.
The output nodes of the emitter followers EF1*EF2 on the OR side and the NOR side of the data input buffer circuit DIB consisting of 11EF2 and 1EF2 are connected, and a wired OR of the respective outputs of the shrink circuit 4 and the data input buffer circuit DIR is taken. . In this case, the output signal of the emitter follower EF1 becomes a signal in phase with the input data Di, and the output signal of the emitter follower EF2 becomes an inverted signal of the input data D+.

Therefore, when reading data when the write enable signal WE is set to a high level, the emitter voltages of the multi-emitter transistor Q30 are both set to a high level, so the input signals of the next stage amplifier API and Ar1 are fixed at a high level. . Each of the amplifiers AP, AP2 consists of a differential amplification stage and an emitter follower.
Since the emitter follower is connected to the node on the OR side, the amplifier AP'1. The output signals of AP2 are forcibly fixed to a low level during reading. Since this low level signal is supplied to the bases of the transistors Q5 and Qe, both transistors Q5 and Qe are cut off, and no current flows toward the data line D.

On the other hand, during writing when the write enable signal WE is set to low level, the output signal WEI of the shrink circuit 4 becomes low level, and the multi-emitter transistor Qso
is cut off.

Therefore, the output signals of the emitter followers EF1e and EF2 of the data manual buffer DIH are supplied as they are to the next stage amplifier AP1sAP2. As a result, the output signal of one of the amplifiers AP1 and Ar1 is set to a higher level than at the time of reading, depending on the input data Di. The other output signal is at the same level as when reading.

These two signals serve as the write voltages VWH and VWL, and the transistors Qs and Qe connected to the data fiD,
, respectively, so that the memory cell selected at that time is inverted.

The shrink circuit 4 includes a pair of transistors Q41t Q4□ whose emitters are commonly connected, and a constant current [4a and The collector of the transistor Q41 t Q42 and the power supply voltage V
It has a current switch circuit C5O made up of resistors R41, R42, and R44, which are respectively connected to cc (ground level). Then, a connection node n1 between the collector of the transistor Q41 and the resistor R41
A resistor R43 and a diode D are connected between
41 #D42 is connected, and a voltage that is obtained by dividing the potential difference between the power supply voltage Vcc and a potential two steps higher than v2E by the threshold voltage of diodes D41 nD42 by the resistance ratio of resistors R41 and R43 is applied to the node. n. The potential of this node n1 is applied to the base of a transistor Q43 whose collector is grounded, and the emitter voltage of this transistor Q43 is the reference voltage V e
A is applied to the base of one transistor Q4□ of the current switch circuit C8o. The emitter of the transistor Q43 is connected to V by the constant current source 4b.
I'm drawn to engineering. And the above-mentioned resistor R4.

A reference voltage generation circuit is configured by R43 and R44, diode D4□+D42, transistor Q43, and constant current source 4b. on the other hand.

A write enable signal WE supplied from outside the IC is applied to the base of the other transistor Q41 of the current switch circuit C80.

Therefore, the current path of the current switch circuit CSO is switched using the reference voltage VBB applied to the base of the transistor Q4□ as a threshold value. That is, when the write enable signal WE is higher than the reference voltage VIIB, a current flows through the transistor Q41, and when the lower write enable signal W becomes lower than the reference voltage Vaa, the current of the transistor Q41 is cut off, and the current flows through the transistor Q42. will be washed away.

Moreover, in the above shrink circuit, the current flowing through the resistor R41 is divided between the transistor Q41 and the reference voltage generation circuit, so that the transistor Q41
The generated reference voltage VaB is changed depending on whether VaB is turned on or cut off.

Furthermore, in this embodiment, a delay capacitor C1 is provided between the node n1 in the reference voltage generating circuit and the power supply voltage Vcc (ground level). As a result, the emitter follower consisting of the transistor Q42 driven by the collector voltage of the transistor Q42 and the constant current source 4C outputs the signal WE1 which is in phase with the write enable signal WE and has noise components cut. It has become.

The write circuit shown in FIG. 5 is an example in which the read reference voltage V r is set based on the write enable signal W1 and external input data Di, Dx during writing.
Various other types of circuits can easily be considered for the circuit that generates the write voltage VWH higher than e f.

Therefore, in the above embodiment, as shown in FIG.
When the word line W is raised from the unselected level VXL to the selected level VXH by the word line driving transistor Qx from the data holding state, the potentials of nodes n1 and n2 in the memory cell rise as in the case of FIG. When the Y switch transistor Q V +0 is turned on by the decode signal Y from the Y decoder, the 1 selected data line is turned on.

The potential of Vc1. Vcm also decreases a little and the reference voltage V r e
f is made to be at a level approximately midway between vCl and VcO. At this time, if the read reference voltage V r e f is applied to the bases of transistors Q3 and Q4, either transistor Q3 or Q4 is turned on and a current flows out from within the read circuit SA, so this is amplified. By the way.

Complementary data outputs Do, Do are obtained.

Therefore, during writing, one word line and a pair of data lines are selected and once set to the readable state as described above, and then, for example, the base voltage of the transistor Q6 is changed according to the input data Di, D. , read reference voltage V r
While the potential VWL is lower than e f, the voltage at the base of the other transistor Q5 in the pair is set to a potential V w higher than the word line selection level V X H.
Lifted by H. Then, the transistor Q2, whose base had been applied with the potential V c 1 of the node n at a high level in the memory cell, is cut off, and current no longer flows from the memory cell MC toward the data line. . As a result, nodes n1 and n2 in the memory cell
, the potential jlt rises, and the state jlt, which is the same as the state T in which only the word line W is selected, is temporarily reproduced.

However, in this state, the potential Vcm of the lower node n2 in the memory cell is increased to a level close to the reference voltage Vraf applied to the base of the transistor Q6, so that the data line is disconnected from the transistor Q1 in the memory cell. A current begins to flow a little toward the opposite side, so that the potential of the node n1 decreases, the base potential of the transistor Q2 decreases, and the potential of the node n2 increases. This automatically inverts the flip-flop and writes different data than before.

As described above, in the writing method circuit of the above embodiment.

Data is written in a word line selected state (data line not selected). On the other hand, in the circuit of the conventional write method shown in the first part, α writing is performed in the read state fi (state in which both the word line and the data line are selected). Therefore, as is clear from FIG. 4, the potential of the node n1+n2 in the memory cell is higher in the word line selection state than in the read state. Therefore, the above equation, which indicates the condition for the amplitude of the word line, V
The potential difference ΔVcm at VxL)ΔVcm (=Vxo−Vcm) is smaller in this embodiment than in the one shown in FIG.

As a result, according to this embodiment, the amplitude of the word line can be made small, so the rise time of the word line is shortened, and the read speed is improved. Further, if the amplitude of the word line is reduced, the amplitude of the data line can also be reduced, so that the read speed is further improved. Furthermore, when the driving amplitude of the memory cell is reduced in this manner, the noise margin of the cell is improved.

Moreover, in the above embodiment, the transistor Q3 to which the read reference voltage Vrof is applied and is connected to the read circuit SA
．． Separately from Q4, write voltage VW L t V W
Since a current changeover switch Qs+Q6 to which H is applied is provided, the write voltage V W H is read out and the reference voltage V
There is no problem in making it higher than r e f. In other words, in a device equipped with a readout circuit with a circuit groove structure as shown in FIG. 3, the voltage VW from the write circuit WA during writing is
L, VWH is connected to transistor Q3. If the write voltage VWH is supplied to the base of Q4 to perform writing and the write voltage VWH is made higher than the read reference voltage Vref, there is a risk that the transistors Q3 and Q4 will be saturated. Since the transistors to which VWL and VWH are applied are separated from the transistors to which write voltages VWL and VWH are applied, there is no risk that transistors Q3 and Q4 in the read circuit SA will be saturated.

In the above embodiment, the base potential of the transistor Q1°, which applies the bias voltage to the data line when not selected, is as follows:
Since it only needs to be lower than the non-selection level VXL of the word line during writing, it can be higher than the potential V c □ of the lower node in the memory cell, as shown in FIG.

In the above embodiment, the transistor Q3. to which the read reference voltage V.sub.ref is applied. Write voltages VWH, VWL newly supplied from the write circuit WA separately from Q4.
, are provided, but the present invention is not limited to this. For example, a multi-emitter transistor Q1o controlled by a decode signal Y from a Y decoder may be configured separately, and this transistor Writing may be performed by respectively applying write voltages VWH and VWL output from the write circuit WA to the bases of the write circuit WA.

[Effects] (1) A flip-flop type memory cell and a pair of current changeover switch transistors connected to a pair of selection lines to which this memory cell is connected, and whose transistor and emitter in the memory cell are commonly connected. In a semiconductor memory device in which data held in a memory cell is read or written by controlling a voltage applied to the base of the current switching transistor, one of the current switching transistors has a By making the base voltage of the memory cell higher than the reference voltage at the time of reading, data is written into the memory cell with only the word line selected. Therefore, data is written with only the word line selected. As a result, the amplitude of the word line can be reduced, which has the effect of shortening the rise time when selecting the word line and improving the access time.

(2) Connected to a flip-flop type memory cell and a pair of selection lines to which this memory cell is connected.

The memory cell has a pair of current changeover switch transistors connected in common to the transistor and the emitter, and by controlling the voltage applied to the base of this current changeover switch transistor, the voltage held in the memory cell is In a semiconductor memory device designed to read or write data, by setting the base voltage of one of the current switching transistors higher than the reference voltage during reading, data can be transferred to the memory cell with only the word line selected. Since it is configured to perform writing, writing is performed in the word line selected state, so the amplitude of the word line can be reduced, and the memory heat amplitude (
This has the effect of reducing the decrease in Vcl-Vo) and improving the noise margin of the memory cell.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the structure of the memory cell and the structure of the read circuit and the write circuit are not limited to those of the embodiment described above, and various modifications can be considered.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the main part configuration of a bipolar static RAM proposed prior to the present invention. FIG. 2 is a timing chart showing an example of the potential relationship between each signal and node to explain the operation of the circuit, and FIG. 3 is an implementation of the main part when the present invention is applied to a bipolar static RAM. Circuit diagram showing an example. FIG. 4 is a timing chart for explaining the operation. FIG. 5 is a circuit diagram showing an example of a write circuit. X-DEC...X decoder, Y-DEC...Y
Decoder, M-ARY...Memory array, MC...
...Memory cell, W...Word line, D, D...
Selection line (data line), SA...readout circuit, WA...
...Writing circuit. Figure 1: CAVE and V2: 2nd
Diagram No. 4 In drawing question-4, I have ¥1,000,000,000,000,000,000,000,000,000,000,000.
Sogome 2su 1zugote

Claims (1)

[Claims] 1. A flip-flop type memory cell, and a pair of current switches connected to a pair of selection lines to which this memory cell is connected, and in which a transistor and an emitter in the memory cell are commonly connected. A semiconductor memory device comprising a switch transistor and configured to read or write data held in a memory cell by controlling a voltage applied to the base of the current changeover switch transistor, the current changeover switch being configured to read or write data held in a memory cell. 1. A semiconductor memory device characterized in that the base voltage of one of the transistors is made higher than a reference voltage during reading, thereby writing data into a memory cell with only a word line selected. 2. The memory cell is composed of a pair of drive transistors, a load resistor connected to the collector side of the drive transistor, and a Schottky barrier diode and a resistor provided in parallel with the load resistor and connected in series with each other. A semiconductor memory device according to claim 1, characterized in that the semiconductor memory device is made of: 3. The current changeover switch transistor is provided separately from a readout current changeover switch transistor whose emitter is commonly connected to the drive transistor in the memory cell and whose base receives a readout reference voltage, similar to this transistor. A semiconductor memory device according to claim 1 or 2, characterized in that the semiconductor memory device is made of a semiconductor memory device.