JPS6141172B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a television receiver, and is particularly suitable for use as a channel selection system.

A frequency synthesizer system using PLL has been developed as a channel selection system for color television receivers. This frequency synthesizer system typically has a loop consisting of a voltage controlled oscillator, a prescaler, a programmable frequency divider, a phase comparator, and a low pass filter. The output of the reference oscillator divided by the fixed frequency divider is applied to one input terminal of the phase comparator, and the output of the voltage controlled oscillator is applied to the other input terminal by the prescaler and the programmable frequency divider. The frequency is divided and added.

The frequency division ratio of the programmable frequency divider is determined by the output code of the code converter controlled by the channel selector. The division ratio of the programmable frequency divider determines the desired channel. The channel selector has a memory circuit for storing data corresponding to a plurality of channels. When a channel selection operation is performed, data corresponding to the desired channel among the plurality of data is read out from the memory circuit.

The frequency division ratio of the programmable frequency divider is set according to the read data, and a desired channel is thereby selected.

Now, let the desired channel be the first channel, the frequency division ratio of the programmable frequency divider at this time be the first frequency division ratio, and the setting data at this time be the first data. In a normal channel selection system, when the first channel is being received, the first frequency division ratio and the first data are held constant and the oscillation frequency of the voltage controlled oscillator of the PLL is locked to a predetermined value. Ru.

On the other hand, in color television receivers,
An AFT (Automatic Fine Tuning) circuit is provided. This AFT circuit controls the oscillation frequency of the local oscillator so that the intermediate frequency of the intermediate frequency amplification stage is always maintained at a constant frequency. This AFT circuit has a discriminator for detecting a shift in the intermediate frequency of the intermediate frequency amplification stage.
The output DC voltage of this discriminator is normally applied to the tuner's voltage controlled oscillator to control the oscillation frequency of the local oscillator.

Some frequency synthesizer systems incorporate an automatic frequency tuning (AFT) function. In this method, fine adjustment data corresponding to the deviation of the antenna input frequency is stored in advance in a memory circuit. When a channel in which the antenna input frequency deviates significantly is selected by the frequency synthesizer system, fine tuning data corresponding to that channel is read out from the memory circuit. The read fine adjustment data corrects the frequency division ratio of the variable frequency divider that divides the output of the reference oscillator, and in this way the oscillation frequency number of the voltage controlled oscillator is adjusted. In this frequency synthesizer system, the output of the reference oscillator is frequency-divided via a variable frequency divider and then input to a phase comparator.

As mentioned above, in a frequency synthesizer system that uses a variable frequency divider between the reference oscillator and the phase comparator, the division ratio N of the programmable frequency divider is
and the frequency division ratio R of the variable frequency divider described above are set at the time of channel selection. The prescaler divides the oscillation frequency of the voltage controlled oscillator into the operating range of the programmable frequency divider, and its frequency division ratio is a unique value.

In a frequency synthesizer system using this PLL, ₀ : Oscillation frequency of the voltage controlled oscillator M: Frequency division ratio of the prescaler R: Frequency division ratio of the variable frequency divider (which divides the output of the reference oscillator) γ: Frequency division ratio of the reference oscillator Assuming that the oscillation frequency is the oscillation frequency, the following relationship holds true.

₀ = M・N・γ/R=M・γ・N/R N= ₀・R/M・γ As can be seen from this formula, the variable element that sets the oscillation frequency of the voltage controlled oscillator when selecting a channel is N and R. Generally, in a frequency synthesizer system, when R is a variable element for fine adjustment, the frequency resolution during fine adjustment differs between channels.

The difference in frequency resolution during fine adjustment between channels will be explained below using a specific example.

Now, in the frequency synthesizer system, M = 64 (prescaler frequency division ratio) γ = 4MHz (reference oscillator oscillation frequency) R = 1024 ± Δγ (R is the frequency division ratio of the variable frequency divider, and for fine adjustment, Δγ is added or subtracted.)

When receiving the first channel with this frequency synthesizer system, the oscillation frequency of the voltage controlled oscillator must be ₀ = 150 MHz, so the division ratio N ₁ of the programmable frequency divider is N ₁ = ₀ . R/M・γ=150×1024/64×
4=600.

Therefore, when receiving the first channel, ( ₀ = 150) = (M = 64) x (N ₁ = 600) x (
The following relationship holds: γ=4)/(R=1024).

Here, if the frequency division ratio R of the variable frequency divider is changed by +1 for fine adjustment and becomes R = 1024 + 1, then ₀ = 64 × 600 × 4 / 1024 + 1 = 149.85365M
The oscillation frequency is Hz.

Before and after R is changed by +1, 150MHz - 149.85365MHz = 146.35kHz, so the oscillation frequency has decreased by 146.35kHz.

Next, the frequency resolution when receiving the 62nd channel will be explained.

When receiving the 62nd channel, the oscillation frequency must be ₀ = 824MHz, so the division ratio N ₂ of the programmable frequency divider is N ₂ = ₀・R/M・γ=824×1024/64×
4=3296.

Therefore, when receiving the 62nd channel, ( ₀ = 824) = (M = 64) x (N ₂ = 3296) x
The following relationship holds true: (γ=4)/(R=1024).

Here, for fine adjustment, the division ratio R of the variable frequency divider is
If it is changed by +1 and becomes R=1024+1, then ₀ = 64×3296×4/1024+1=823.1960
The oscillation frequency is 9MHz.

Before and after R is changed by +1, 824MHz - 823.19609MHz = 803.9kHz, so the oscillation frequency has decreased by 803.9kHz.

As mentioned above, when R is varied to "1" while receiving the 1st channel, the oscillation frequency is varied to 146.35kHz, and when receiving the 62nd channel, R is varied to "1". Then, the oscillation frequency is varied to 803.9kHz. In other words, the frequency resolution during fine adjustment differs between channels. Comparing the frequency resolutions of the first channel and the 62nd channel, there is a large difference.

The above is due to the fact that R is a variable element.
This means that when receiving a channel, it is possible to compensate for deviations in the antenna input frequency in fine steps, but when receiving the 62nd channel, it is impossible to compensate in fine steps.

An object of the present invention is to configure frequency division ratio setting data N that determines the frequency division ratio of a programmable frequency divider of a frequency synthesizer system to be finely adjusted by fine adjustment data, and to reduce the frequency at the time of fine adjustment. The purpose of resolution is to provide a television receiver controller configured to have the same resolution on all channels.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a receiving system for a television receiver. Reference numeral 11 denotes a tuner, and when a tuning voltage is applied to its terminal as a terminal voltage of a variable capacitance diode, a desired channel corresponding to the tuning voltage value can be received. This tuner 11 obtains the local oscillation frequency setting and tuning frequency setting by applying a tuning voltage to a voltage controlled oscillator (including a variable capacitance diode) provided inside the tuner 11, and obtains tuning. . The television signal of the channel selected by this tuner 11 is applied to a television signal processing circuit 12 and an audio intermediate frequency amplification circuit 13.

The oscillation output of the voltage controlled oscillator inside the tuner 11 is input to the programmable frequency divider 15 via the prescaler 14. The frequency-divided output of the programmable frequency divider 15 is input to one input terminal of the phase comparator 16. The output of the reference oscillator 17 is input to the other input terminal of the phase comparator 16. The output pulse voltage of the phase comparator 16 is applied to the oscillation frequency control terminal of the voltage controlled oscillator of the tuner 11 via the low-pass filter 18.

In the frequency synthesizer using this PLL method, the frequency division ratio of various values is set at the frequency division ratio designation input terminal for setting the frequency division ratio of the programmable frequency divider 15, so that the low frequency Filter 18
The output DC voltage of can be varied. The local oscillation frequency of the tuner 11 is varied by this output DC voltage, so that a desired channel is selected. If there is a frequency fluctuation in the local oscillation frequency, the output DC voltage of the low-pass filter 18 will also change accordingly, providing a function of suppressing the frequency fluctuation. In this way, a stable receiving condition of the tuner can be obtained.

The frequency division ratio of the programmable frequency divider 15 is set by the output data from the frequency division ratio storage circuit 19 when there is no control information for frequency fine adjustment.
The frequency division comparison storage circuit 19 uses a ROM (read only memory). The output data is then applied to the division ratio designation input terminal ₁₅₁ of the programmable frequency divider 15.

During frequency fine adjustment operation, the output data of the fine adjustment signal generation circuit 20 is sent to the frequency division ratio specifying input terminal 1 in order to finely adjust the oscillation frequency of the voltage controlled oscillator.
5 Added to ₁ .

The frequency division ratio storage circuit 19 includes an input/output circuit (I/O
The output of port 21 is added. The operation output of the keyboard unit 22 is sent to the decoder 23, I/O
The read address of the frequency division ratio storage circuit 19 can be designated via the port 21 .

The output of the decoder 23 is also applied to the address designation input terminal of the random access memory circuit 24RAM. When the RAM 24 is in the read mode, its output is input to the fine adjustment signal generation circuit 20 via the I/O port 21. Also, this
When the RAM 24 is in write mode, the output of the fine adjustment signal generation circuit 20 can be written to the RAM 24 via the I/O port 21.

keyboard unit 22, decoder 23,
The input/output timing and switching of the RAM 24, I/O port 21, fine adjustment signal generation circuit 20, etc. are performed by control command signals from the control device 25. As the control device 25, a microcomputer is used.

FIG. 2 shows the key arrangement of the keyboard unit 22. This keyboard unit 22 has channel designation key switches CH.0 to CH.9 and function switches FU.1 to FU.4.

FIG. 3 shows the data storage format of the RAM 24. In FIG. 3, the vertical direction is the divisions (24 ₁ , 24 ₂ . . . 24 _o ) corresponding to the channels.
In the horizontal direction, there is a fine adjustment data area 24A (5 bits) and a direction designation data area 24B (1 bit).

The relationship between the keyboard unit 22 and the RAM 24 is as follows. When selecting a channel, two of the channel designation key switches CH.0 to CH.9 of the keyboard unit 22 are optionally operated, so that the outputs of the two key switches are applied to the decoder 23 in the order of operation. As a result, the decoder 23 generates a responsive digital signal, which passes through the I/O port 21 and specifies an address in the frequency division ratio storage circuit 19 constituted by a ROM. Data for setting the frequency division ratio is read from the frequency division ratio storage circuit 19 designated by the address. By reading out the data in the frequency division ratio storage circuit 19 in this manner, the television receiver enters the tuning state.

At this time, data related to the frequency fine adjustment operation of the section corresponding to the selected channel is read out from the RAM 24.

The output data of the RAM 24 includes fine adjustment data and direction designation data, and is input to the fine adjustment signal generation circuit 20.

For example, CH.0 of the channel specified key switch.
~ When CH.1 is operated sequentially, a digital signal corresponding to the first channel is output from the decoder 23. The digital signal from the decoder 23 is as follows.
As the address signal of the frequency division ratio storage circuit 19, I/
Pass through the O port 21 and divide the division ratio read input terminal 19
from this frequency division ratio storage circuit 19.
Frequency division ratio setting data for channel selection is read. Further, the digital signal from the decoder 23 in response to the channel designation key switch is input to the RAM 24 to designate the address corresponding to the first channel, and the fine adjustment data and direction designation data of the designated address are read out. The read fine adjustment data and direction designation data are input to the fine adjustment signal generation circuit 20 via the I/O port 21.

In the fine adjustment signal generation circuit 20, processing for correcting the dividing ratio setting data is performed based on the fine adjustment data and the direction specifying data. (Specific processing operations will be explained in FIGS. 4 and 5.) Among the data generated by the fine adjustment signal generation circuit 20, the fine adjustment data is based on the frequency division ratio if the direction designation data is "0". It is added to the frequency division ratio setting data read from the storage circuit 19, and if the direction designation data is "1", it is subtracted from the frequency division ratio setting data read from the frequency division ratio storage circuit 19.

The new frequency division ratio setting data obtained by the above processing operation is applied to the frequency division ratio designation input terminal 151 of the programmable frequency divider ₁₅ in order to appropriately control the oscillation frequency of the voltage controlled oscillator.

The direction designation data indicates whether the antenna input frequency is shifted in the positive direction or the negative direction using "0" or "1", and is combined with the division ratio setting data from the division ratio storage circuit 19. The fine adjustment signal generation circuit 20 is commanded to perform addition or subtraction processing with the fine adjustment data. Depending on the contents of the direction specifying data, the output of the voltage controlled oscillator, that is, the local oscillation frequency, is controlled to increase or decrease, or is maintained at the same frequency.

Next, when receiving the first channel,
Since correct tuning cannot be obtained with the fine tuning data read from the RAM 24, if it is necessary to rewrite the division ratio setting data due to the fine tuning operation, the following operation is performed. Function switch FU2 for shifting the oscillation frequency of the voltage controlled oscillator of the keyboard unit 22 to a higher side
Or, either function switch FU3 for shifting the oscillation frequency to a lower side is called,
The oscillation frequency is finely adjusted.

When either the function switch FU3 or FU2 is operated, the absolute amount of fine adjustment data is varied within the fine adjustment signal generating circuit 20. By varying the absolute amount of the fine adjustment data, the frequency division ratio of the programmable frequency divider 15 is also varied. During this fine adjustment operation, when fine adjustment data and direction designation data for making the image optimal are obtained, a function switch FU1 having a function of writing the fine adjustment data and direction designation data into the RAM 24 is operated. In this way, new fine adjustment data and direction specifying data are written to the RAM 24 via the I/O port 21. In this way, new data will be transferred to RAM2
4, if the channel designation key switches CH.0 and CH.1 of the keyboard unit 22 are operated in order to receive the first channel,
The new fine adjustment data and direction designation data previously stored in the RAM 24 for the first channel are
RAM 24 is read. The best possible image is therefore obtained.

Next, the frequency resolution of the frequency synthesizer system using the above-mentioned PLL will be explained.

₀ : Local oscillation frequency of the tuner M: Frequency division ratio of the prescaler N: Frequency division ratio of the programmable frequency divider γ: Assuming the reference frequency, ₀ =M×N×γ N= ₀ /M××γ.

Now, in this frequency synthesizer system, M=64 and γ=1.25kHz.

When receiving the first channel, the oscillation frequency of the voltage controlled oscillator is required to be ₀ = 150MHz, so the division ratio of the programmable frequency divider is N ₁
is, N ₁ = ₀ /M×γ=150×10 ³ /64×1.2
5=1875.

Therefore, when the first channel is received, data corresponding to N=1875 is read from the frequency division ratio storage circuit 19. This read operation is
This is possible by operating the channel designation key switches CH.0 and CH.1 of the keyboard unit 24.

If N is varied by "1" for fine adjustment while the first channel is being received, N = 1875 + 1 = 1876, and the local oscillation frequency is ₀ = M x N x γ = 64 x 1846 x Variable to 1.25=150080kHz.

The frequency division ratio N ₂ of the programmable frequency divider is N ₂ = ₀ /M×γ=824×10 ³ /64×1.2
5=10300.

Therefore, when the 62nd channel is received, data corresponding to N=10300 is read from the frequency division ratio storage circuit 19. When receiving the 62nd channel, if N is changed by 1 for fine adjustment, N = 10300 + 1 = 10301, and the local oscillation frequency is ₀ = M x N x γ = 64 x 103001 x 1.25 = Variable to 824080kHz.

Before and after N is varied by +1, 150MHz-150.080MHz=-80kHz, so the oscillation frequency is reduced by 80kHz. Similarly, when N is varied by 2, ₀ =
It becomes 150160kHz, and the frequency change of the local oscillator of 160kHz is uneven. In other words, every time N is changed by 1,
A frequency change of 80kHz is obtained.

Next, the frequency resolution when receiving the 62nd channel will be explained. When receiving the 62nd channel, the oscillation frequency must be ₀ = 824MHz, so before and after changing N +1, it is 824MHz - 824.080MHz = -80kHz, so the oscillation frequency has been reduced by 80kHz. become. Similarly, when N is varied by 2, ₀
= 82416kHz, resulting in a local oscillator frequency change of 160kHz. This means that even when receiving the 62nd channel, a frequency change of 80 kHz is obtained every time N is changed by "1".

As described above, if the local oscillation frequency is to be shifted by 80 kHz, fine adjustment data of "+1" or "-1" should be added to N. Also, if you want to shift the local oscillation frequency by 160 kHz, you only need to add "+2" or "2" fine adjustment data to N, and if you want to shift it by 360 kHz, you can add "+3" or "-" to N. 3" fine adjustment data may be added. The rate of frequency change obtained by finely adjusting N (80kHz
unit) is the same for all channels. This means that the frequency resolution when making fine adjustments is the same for each channel. This also means that fine adjustment of the reception frequency is possible in a wide reception band area (VHF, UHF).

FIG. 4 shows a fine adjustment signal generation circuit.

The output of the frequency division ratio storage circuit 19 is output from the gate circuit 30.
is input to one input terminal ₃₀₁ of the . The output of this gate circuit 30 is input to the division ratio designation input terminal ₁₅₁ of the programmable frequency divider 15. The output of the addition/subtraction circuit 33 is applied to the other input terminal ₃₀₂ of this gate circuit 30. This gate circuit 30
is either one of the input terminals 30 ₁ or 30 ₂
The switching control signal is obtained from the data presence/absence detection circuit 34.

The output of the fine adjustment data processing circuit 31 is input to one input terminal of the addition/subtraction circuit 31, and the output of the frequency division ratio storage circuit 19 is input to the other input terminal. This addition/subtraction circuit 31 can add or subtract fine adjustment data to or from the frequency division ratio setting data, and the result of the calculation is input to the input terminal ₃₀₂ of the gate circuit 30. The addition or subtraction operation of the addition/subtraction circuit 31 is determined by the output signal of the direction specifying data processing circuit 32. The output of the fine adjustment data processing circuit 31 is also applied to the data presence/absence detection circuit 34. This data presence detection circuit 34 determines the presence or absence of fine adjustment data, and if fine adjustment data exists, controls the gate circuit 30 to select the input terminal ₃₀₂ , and if there is no fine adjustment data, controls the input terminal 302. Control is performed to select the end ₃₀₁ .

Output data from the RAM 24 is input to the fine adjustment data processing circuit 31 and the direction specifying data processing circuit 32 via the I/O port 21. The fine adjustment data is stored in the fine adjustment data area 24A of the RAM 24.
The direction specifying data is read from the direction specifying data area 24B.

5 and 6 show the circuit of FIG. 4 in more detail. When a certain channel is selected by the keyboard unit 22, the division ratio setting data is stored in the division ratio storage circuit 1 constituted by a ROM.
It is read from 9. The read frequency division ratio setting data is sent to 11-1 through line group 51.
Bit input to one input end of the full adder. On the other hand, the fine adjustment data read from the RAM 24 is input to the input terminal group of the presettable up-down counter 60 via the I/O port 21 line group 53. The direction designation data is also input to the direction designation data processing circuit 32 via line 54.

In the presettable up-down counter 60, fine adjustment data is read under the control of a data read timing pulse _φ2 input to the load terminal. The direction designation data is latched into the direction designation data processing circuit 32 at a timing determined by clock pulse _φ2 .

At this time, if the fine adjustment data from the RAM 24 is all "0", this is the data presence/absence detection circuit 3.
4 is detected by the NOR circuit 56 that constitutes 4.
The output control signal of this NOR circuit 56 is input to the gate circuit 30 via an inverter 57. (Shown in FIG. 6) The gate circuit 30 receives data input through a line group 51 connected to the frequency division ratio storage circuit 19 or a full adder according to a control signal from the data presence/absence detection circuit 34. Either one of the data input through the line group 52 connected to the output side of the programmable frequency divider 15
selectively input to the division ratio designation input terminal of . Therefore, if all the fine adjustment data are "0",
The data of line group 51 is selected and input to the frequency division ratio designation input terminal of programmable frequency divider 15 .

Next, if fine adjustment data exists, the direction designation data from the direction designation data processing circuit 32 determines either the addition operation or the subtraction operation of the full adder 55. The full adder 55 performs an addition operation when the carry input from the direction specifying data processing circuit 32 is "0", and performs a subtraction operation when the carry input is "1".

The frequency division ratio setting data from the frequency division ratio storage circuit 19 is input to one input terminal of the full adder 55.
Fine adjustment data from the presettable up-down counter 60 is input to the other terminal. The full adder 55 performs addition or subtraction processing between the frequency division ratio setting data and the fine adjustment data, and the result is sent to the frequency division ratio designation input terminal of the programmable frequency divider 15 via the line group 52 and the gate circuit 30. is input. At this time, the gate circuit 30 is switched so that the data of the line group 52 can be selected by the output from the NOR circuit 56 constituting the all-zero detection circuit.

Next, if the correct oscillation frequency of the voltage controlled oscillator cannot be obtained depending on the fine adjustment data read from the RAM 24, the function switch
FU2 or FU3 is operated. The operator determines whether fine adjustment is necessary by looking at the image state.

The outputs of function switches FU2 and FU3 are sent to the corresponding D flip-flop 8.
2,83 can be controlled. These constitute an operating circuit.

For example, when the function switch FU2 is turned on, the output of the D-type flip-flop circuit 82 becomes "1". This output "1" is applied to one input terminal of the exclusive OR circuit 61 and also to one input terminal of the OR circuit 81. Furthermore, the D-type flip-flop circuit 8
2 output “1” is NAND circuit 72, NAND circuit 7
6 each applied to one input end.

The output of the OR circuit 84 is applied to one input terminal of a NAND circuit 86, a reset terminal of a frequency divider 87, and a first input terminal of a NAND circuit 88. Therefore,
The output of the oscillator 85 is applied to the output terminal of a NAND circuit 86 and frequency-divided by a frequency divider 87 , and the frequency-divided output is inputted to a second input terminal of a NAND circuit 88 . These constitute a clock pulse introduction circuit.

The output of the inverter 75 is input to the third input terminal of the NAND circuit 88 . 1st of NAND circuit 88
When the input terminal and the third input terminal are held at "1", the output of the frequency divider 87 is output from the NAND circuit 88.
appears at the output of , and is introduced into the clock input terminal Ck of the presettable up-down counter 60.

The presettable up-down counter 60 is
When the output of the exclusive OR circuit 61 is "0", it performs a down-count operation, and when it is "1", it performs an up-count operation.

() Now assume that the direction designation data latched in the direction designation data processing circuit 32 is "0" and the function switch FU2 is operated. Since the input terminals of the exclusive OR circuit 61 are "0" and "1", this output is 1,
The presettable up-down counter 60 starts up-counting operation.

Further, since the direction designation data is "0", the full adder 55 performs an addition operation. The fine adjustment data is varied by the up-count operation of the presettable up-down counter 60.

Therefore, the full adder 55 performs fine adjustment of the division ratio setting data, and the adjusted division ratio setting data is input to the division ratio designation input terminal of the programmable frequency divider 15. will be done. While continuing to press the function switch FU2, when the image condition becomes optimal, the function switch FU2 is released. The fine adjustment data at this time is held in the output terminal group of the presettable up-down counter 60. Here, if you want to store the fine adjustment data in the RAM 24, press the function switch FU.
1 is operated. Function switch FU
When the 1 operation is performed, a clock pulse φ ₁ is generated for the fine adjustment data, which passes through the I/O port 21 via the transmission gate group 62 and is stored in the RAM 24.

If the best image cannot be obtained even if the function switch FU2 is kept pressed, the up-counting operation of the presettable up-down counter 60 continues and the fine adjustment data becomes all "1". The fact that the fine adjustment data has become all "1" is detected by the NAND circuit 58 that constitutes the all-1 detection circuit.
The output of 9 becomes "1". When the output of the inverter 59 becomes "1", the inputs of the NAND circuit 72 are "1", "1", the inputs of the NAND circuit 73 are "1",
"0", the inputs of the NAND circuit 74 become "0" and "1", and the output of the inverter 75 becomes "0".
Therefore, the output of the NAND circuit 88 is always "1"
Therefore, no pulse is applied to the presettable up-down counter 60.

"0" is latched as the direction designation data, and when the function switch FU2 is operated, the presettable up/down counter 60
When the output (fine adjustment data) becomes all "1", the fine adjustment operation is automatically stopped.

() Assume that the direction designation data latched in the direction designation data processing circuit 32 is "1" and the function switch FU2 is operated. Since the input terminals of the exclusive OR circuit 61 are "1" and "1", its output is "0".
The presettable up-down counter 60 performs a down-counting operation. Further, since the direction designation data is "1", the full adder 55 performs a subtraction operation. When this operation progresses and the output (fine adjustment data) of the presettable up-down counter 60 becomes all "0", this is detected by the NOR circuit 56. In other words, the presettable up-down counter 60
When the outputs of the NOR circuit 56 become all "0", the output of the NOR circuit 56 becomes "1". This Noah circuit 5
The output of 6 is one input terminal of the NAND circuit 76,
It is applied to one input terminal of the AND circuit 77.
With this, the input of the NAND circuit 76 is
The outputs of "1" and "1" are "0", and the input of the AND circuit 77 is "1" and the output of "0" is "0".

As a result, the inputs of the AND circuit 66 are "0",
It becomes "1" and the output becomes "0". and,
Since the output of the NOR circuit 67 becomes "1", the contents of the direction designation data processing circuit 32 are rewritten from "1" to "0". Therefore, the presettable up-down counter 60
Since the input of the exclusive OR circuit 61 becomes "0" and "1" and the output becomes "1", the operation is switched to an up-count operation, and the full adder 55 starts to perform an addition operation. As explained above, this state is the same as when the direction designation data is "0" and the function switch FU2 is operated.

() It is now assumed that the direction designation data latched in the direction designation data processing circuit 32 is "0" and the function switch (FU3) is operated. At this time, the input terminals of the exclusive OR circuit 61 are "0", "0", and its output is "0", so the presettable up-down counter 60 starts a down counter operation. Further, since the direction designation data is "0", the full adder 55 performs an addition operation. When function switch FU3 is operated,
D-type flip-flop circuit 83 is driven.
Since the output of this D-type flip-flop circuit 83 becomes "1", the output "1" of the OR circuit 84 is output from one input terminal of the NAND circuit 86,
It is applied to the reset terminal of frequency divider 87 and the first input terminal of NAND circuit 88. Therefore, the output of the oscillator 85 appears at the output terminal of the NAND circuit 86 and is frequency-divided by the frequency divider 87, and the frequency-divided output is inputted to the second input terminal of the NAND circuit 88. The inverter 7 is connected to the third input terminal of the NAND circuit 88.
The output of 5 is input. 1st of NAND circuit 88
When the input terminal and the third input terminal are held at "1", the output of the frequency divider 87 appears at the output of the NAND circuit 88 and is introduced into the floating input terminal Ck of the presettable up-down counter 60. .

Since the direction designation data is "0" and the inputs of the exclusive OR circuit 61 are "0" and "0", its output is "0". The presettable up-down counter 60 is in a down-counting state, and the full adder 55 is in an adding state.

Press and hold function switch FU3 until the presettable up/down counter 60
When the outputs of are all “0”, the NOR circuit 56
The output of is "1". As a result, the input of the NAND circuit 76 is "1", "0", the output is "1",
The input of the AND circuit 77 is "1", and the output is "1".

As a result, the contents of the direction designation data processing circuit 32 are rewritten from "0" to "1". Therefore, the inputs of the exclusive OR circuit 61 are "1" and "0", and the output is "1", and the presettable up-down counter 6
0 switches to up count operation. The full adder 55 also performs a subtraction operation.

When the function switch FU3 is pressed while "0" is latched as the direction designation data, and the presettable up-down counter 60 continues to count down and the full adder 55 to continue to add, the presettable When the output of the up-down counter 60 becomes all "0", the direction designation data is rewritten to "1". Then, the presettable up-down counter 60 automatically switches to an up-counting operation, and the full adder 55 automatically switches to a subtracting operation.

If this state continues further and the output of the presettable up-down counter 60 becomes all "1", this is detected by the NAND circuit 58. When the output of the presettable up counter 60 becomes all "1", the output of the NAND circuit 55 becomes "0" and the output of the inverter 59 becomes "1". As a result, the input of the NAND circuit 72 is "1", the output is "1", and the input of the NAND circuit 73 is "1", "1", and the output is "0".
becomes. Therefore, the input of the NAND circuit 74 is "1", "0", the output is "1", and the inverter 75
Since the output of Ck becomes "0", the NAND circuit 88 is controlled and the clock pulse input terminal Ck
The pulse will no longer be applied to . By this,
The fine adjustment operation will stop automatically.

() Now assume that the direction designation data latched in the direction designation data processing circuit 32 is "1" and the function switch FU3 is operated. In this case, the operation is the same as the case where the presettable up-down counter 60 automatically switches to the up-counting operation and the full adder 55 automatically switches to the subtracting operation, as described above. Therefore, if the function switch FU3 is kept pressed, the output of the presettable up-down counter 60 will eventually become all "1", and the fine adjustment operation will be automatically stopped.

As described above, in the present invention, when finely adjusting the frequency division ratio of the programmable frequency divider 15,
A configuration based on a presettable up-down counter 60 and an exclusive OR circuit 61 works effectively for the full adder 55. That is, by adding or subtracting the data of the presettable up-down counter 60 to the data of the full adder 55, the range of fine adjustment can be widened. Furthermore, in this case, the addition or subtraction mode in the full adder 55 and the up-count mode and down-count mode in the presettable up-down counter 60 are automatically combined and controlled using a simple configuration.

As described above, the present invention is configured such that the frequency division ratio setting data N that determines the programmable frequency division ratio of the frequency synthesizer system is finely adjusted by the fine adjustment data, and the frequency resolution at the time of fine adjustment is In particular, it is possible to provide a control device for a television receiver configured to have the same resolution in each channel, in particular, by configuring the fine adjustment data variable means by a simple control circuit and widening the variable range.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is a key layout diagram of the keyboard unit in FIG. 1, FIG. 3 is a diagram showing a memory map of the RAM in FIG. 1, and FIG. FIG. 1 is a diagram specifically showing the fine adjustment generation circuit, and FIGS. 5 and 6 are diagrams showing the circuit of FIG. 4 in more detail. 15...Programmable frequency divider, 20...Fine adjustment signal generation circuit, 55...Full adder, 56...NOR circuit, 60...Presettable up-down counter, 61...Exclusive OR circuit.

Claims (1)

[Claims] 1. A voltage controlled oscillator that obtains the local oscillation output of the receiver, a prescaler that divides the output of the voltage controlled oscillator, a programmable frequency divider to which the output of the prescaler is supplied, and a programmable frequency divider that divides the output of the voltage controlled oscillator. Comparing means for comparing the output of the frequency generator and the output of the reference oscillator and controlling the oscillation frequency of the voltage controlled oscillator according to the frequency and phase difference thereof; and means for setting the division ratio of the programmable frequency divider. In the television receiver control device, the means for setting the frequency division ratio is capable of selectively inputting different data to one input terminal, and certain selected first data is input to the one input terminal. A full adder that adds or subtracts the data input to the other input terminal while the data is being input to one input terminal, and uses the result as the frequency division ratio, and an up count for the clock pulse from the clock pulse introduction circuit section. ,
a presettable up-down counter capable of down-counting and applying output data to the other input terminal of the full adder; and a latch circuit that latches a 0 or 1 signal that determines addition or subtraction operation of the full adder. a 0 or 1 signal latched in the latch circuit means is applied to one input terminal and an output is applied to a control terminal for determining up-counting or down-counting operation of the presettable up-down counter. an exclusive OR circuit, at least a first operation circuit which can set a signal of 0 or 1 to the other input terminal of the exclusive OR circuit and sets the first signal by operation; and the presettable circuit. A control device for a television receiver, comprising an all-zero detection means for detecting all zeros in output data of an up-down counter and applying a control output to the set and reset ends of the latch circuit means. 2. The presettable up-down counter is provided with all-1 detection means for detecting all-1s in its output, and controls the clock pulse introduction circuit by the output of the all-1 detection means,
2. The control device for a television receiver according to claim 1, wherein the control device is configured to stop clock pulse introduction in the state of . 3. The latch circuit means capable of controlling the counting operation of the presettable up-down counter is capable of storing the latch signal by circulating it by clock pulses, and is capable of storing a 0 or 1 signal read from the storage circuit. an input section for storing the
A set that can rewrite its memory contents,
It is equipped with a reset input section and first and second gate circuits that apply outputs to the set and reset input terminals, respectively, and the all-zero detection means is connected to one input terminal of each of the first and second gate circuits. A control circuit is added thereto, and the outputs of the first operation circuit and the second operation circuit are applied to the other input terminals of each of the first and second gate circuits, respectively. A control device for a television receiver according to claim 1. 4. The output during operation of the first and second operating circuits is configured to control a clock pulse introduction circuit so that the output of an oscillator is introduced into the clock input terminal of the presettable up-down counter. A control device for a television receiver according to claim 2, characterized in that: