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JPS61263124A - Mask plate for manufacturing semiconductor device - Google Patents

Mask plate for manufacturing semiconductor device

Info

Publication number
JPS61263124A
JPS61263124A JP60105310A JP10531085A JPS61263124A JP S61263124 A JPS61263124 A JP S61263124A JP 60105310 A JP60105310 A JP 60105310A JP 10531085 A JP10531085 A JP 10531085A JP S61263124 A JPS61263124 A JP S61263124A
Authority
JP
Japan
Prior art keywords
wafer
mask
pattern
mask plate
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60105310A
Other languages
Japanese (ja)
Other versions
JPH0466094B2 (en
Inventor
Yutaka Kadonishi
門西　裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP60105310A priority Critical patent/JPS61263124A/en
Publication of JPS61263124A publication Critical patent/JPS61263124A/en
Publication of JPH0466094B2 publication Critical patent/JPH0466094B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a mask plate for manufacturing a semiconductor device which can define the width of a facet cut portion of a wafer, by constructing the plate of a belt-shaped transparent element provided adjacently to a pattern element and a mask element provided adjacently on the opposite side to the pattern element. CONSTITUTION:A mask plate 10 is formed, on a glass plate 11, of a pattern element 12 with a pattern drawn for forming ordinary layers on a wafer, a belt-shaped transparent element 13 provided adjacently to said pattern element 12 and further a belt-shaped mask element 14 provided adjacently to the outside f said transparent element 13. The wafer 1 being moved under the mask plate 10, an orientation flat 2 of the wafer 1 is matched with the edge 14a of the mask element 14 by visual observation from above the transparent plate 13. Then, a light is projected from above the mask plate 10. Thereby the wafer 1 is cut by the width (t) of the transparent element 13 from the orientation flat 2, and thus a facet cut portion having a definite width is formed constantly.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 この発明は、半導体装置製造用のマスク板、特にファセ
ットカット部形成に有効なマスク板に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a mask plate for manufacturing semiconductor devices, and particularly to a mask plate effective for forming facet cut portions.

（ロ）従来の技術 一般に、半導体ウェハにおいて、各層や電極を形成する
工程、あるいは搬送過程で、取扱い上、ビンセットでつ
まむ場合がある。この場合、箇所をかまわずつまむと、
ウェハ表面を傷つけるおそれがある。そこで、第３図に
示すように、ウェハ１のオリエンテーションフラット２
から内側に予めファセットカット部（カントゾーン）３
を形成し、テストではアウトとなるようにする。ウェハ
１を取扱う時は、ファセットカット部３をピンセットで
つまむことになる。このファセットカット部３を形成す
るのに、従来は第２図に示すように、正常なパターン形
成用のパターン部４を有するガラス板５の下方にパター
ン形成すべきウェハ１を配設し、オリエンテーションフ
ラット２を含むウェハ１の端部にプラスチック板６を被
せ、露光時にこの部分に光が当たらないようにしていた
。(b) Prior Art Generally, semiconductor wafers are sometimes pinched with a bin set for handling during the process of forming layers and electrodes, or during the transport process. In this case, if you pinch the area,
There is a risk of damaging the wafer surface. Therefore, as shown in FIG. 3, the orientation flat 2 of the wafer 1 is
Facet cut part (cant zone) 3 on the inside from
, so that it will be out in the test. When handling the wafer 1, the facet cut portion 3 is pinched with tweezers. To form this facet cut portion 3, conventionally, as shown in FIG. 2, the wafer 1 to be patterned is placed below the glass plate 5 having the pattern portion 4 for normal pattern formation, and the orientation The end of the wafer 1 including the flat 2 was covered with a plastic plate 6 to prevent light from hitting this part during exposure.

（ハ）発明が解決しようとする問題点 上記した従来技術によるファセットカット部の形成では
、オリエンテーションフラット近傍にプラスチック板を
被せるのみであるから、非露光幅、つまりカット幅が一
定せず、必要以上にファセットカット部の幅を大きくし
たり、逆にその幅が狭く、時にはチップの一部をカット
することになり、本来不合格であるべきものが、テスト
しても合格となるものがあった。(c) Problems to be Solved by the Invention In the formation of facet cut portions according to the above-mentioned prior art, since the plastic plate is only placed in the vicinity of the orientation flat, the non-exposed width, that is, the cut width is not constant and is larger than necessary. In some cases, the width of the facet cut part was made larger, or conversely, the width was narrower, and sometimes a part of the chip was cut off, which resulted in some products passing the test even though they should have failed. .

この発明は、上記に鑑み、ウェハのファセットカット部
の幅を一定となし得る半導体装置製造用のマスク板を提
供することを目的としている。In view of the above, it is an object of the present invention to provide a mask plate for manufacturing semiconductor devices that allows the width of the facet cut portion of a wafer to be constant.

（ニ）問題点を解決するための手段及び作用この発明の
マスク板は、半導体ウェハに所要のパターンを形成する
ためのパターン部と、このパターン部に隣接して設けら
れる帯状の透明部と、この透明部の前記パターン部とは
反対側に隣接して設けられるマスク部とから構成されて
いる。(d) Means and operation for solving the problems The mask plate of the present invention includes a pattern section for forming a desired pattern on a semiconductor wafer, a band-shaped transparent section provided adjacent to the pattern section, The mask part is provided adjacently on the opposite side of the transparent part to the pattern part.

このマスク板を用いて半導体ウェハにパターンを形成す
る場合に、透明部よりウェハ表面が目視でき、マスク部
にウェハのオリエンテーションフラットを合わせると、
常に一定幅のファセットカット部を持つウェハが得られ
る。When forming a pattern on a semiconductor wafer using this mask plate, the wafer surface can be seen from the transparent part, and if the orientation flat of the wafer is aligned with the mask part,
Wafers with facet cuts of constant width are always obtained.

（ホ）実施例 以下、実施例により、この発明をさらに詳細に説明する
。(E) Examples The present invention will be explained in more detail with reference to Examples below.

第１図は、この発明の一実施例を示すマスク板の平面図
である。同図において、マスク板１０は、ガラス板１１
上に、ウェハに通常の層を形成するためのパターンが描
かれたパターン部１２と、このパターン部１２に隣接し
て設けられる帯状の透明（白抜き）部１３、さらにこの
透明部１３の外側（パターン部１２とは反対側）に隣接
して、帯状のマスク（黒ベタ）部１４が形成されて構成
されている。FIG. 1 is a plan view of a mask plate showing an embodiment of the present invention. In the figure, the mask plate 10 is a glass plate 11.
On the top, there is a pattern section 12 on which a pattern for forming a normal layer on a wafer is drawn, a band-shaped transparent (white) section 13 provided adjacent to this pattern section 12, and an outer side of this transparent section 13. A band-shaped mask (solid black) portion 14 is formed adjacent to the pattern portion 12 (on the side opposite to the pattern portion 12).

次に、このマスク板１０を用いてウェハ製造のファース
ト工程処理をなす場合を説明する。Next, a case will be described in which this mask plate 10 is used to perform the first step of wafer manufacturing.

ウェハ１をマスク板１０の下方で移動させ、透明部１３
の上方から目視により、ウェハ１のオリエンテーション
フラット２をマスク部１４の端縁１４ａに合わせる。そ
して、マスク板１ｏの上方より光を投射する。これによ
り、ウェハ１はオリエンテーションフラット２より透明
部１３の幅ｔだけカットされ、常に一定幅のファセット
カット部（アウトゾーン）３が形成される。The wafer 1 is moved below the mask plate 10 and the transparent part 13
The orientation flat 2 of the wafer 1 is aligned with the edge 14a of the mask portion 14 by visual observation from above. Then, light is projected from above the mask plate 1o. As a result, the wafer 1 is cut by the width t of the transparent portion 13 from the orientation flat 2, and a facet cut portion (out zone) 3 having a constant width is always formed.

ファースト工程以後のウェハ１の位置決めは、ファスー
ト工程でパターン部１２によってウェハ１中に形成され
る位置決めチップを用いることにより、精度良くなすこ
とができ、従って以後の工程では、ファセットカット部
３の幅が変化することはない。The positioning of the wafer 1 after the first process can be performed with high precision by using a positioning chip formed in the wafer 1 by the pattern part 12 in the fast process. never changes.

（へ）発明の効果 この発明によれば、マスク板のパターン部とマスク部の
間に帯状の透明部を設けているので、この透明部よりウ
ェハを目視しながら、ウェハの位置決めが出来るので、
ウニへのファセットカット部を常に一定幅とすることが
でき、得られるチップに不良を出したり、不必要にアウ
トとするのを防止できる。特に、マスクで力・７トする
ので、チップを分断する態様でカットされることはなく
、多情りが向上する。(F) Effects of the Invention According to the present invention, since a band-shaped transparent part is provided between the pattern part of the mask plate and the mask part, the wafer can be positioned while visually observing the wafer from this transparent part.
The facet cut portion of the sea urchin can always be made to have a constant width, and it is possible to prevent the resulting chips from being defective or being cut out unnecessarily. In particular, since the mask applies force, the chip will not be cut in a manner that would separate it, and the flexibility will be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この発明の一実施例を示すマスク板の平面図
、第２図は、従来のウェハのファセットカット部の形成
を説明するための平面図、第３図は、ウェハの平面図で
ある。 １：ウェハ翫 ２：オリエンテーションフラット、 ３：ファセットカット部、１０：マスク板、１１ニガラ
ス板、　　１２：パターン部、１３：透明部、　　１４
：マスク部。 特許出願人　　　　　　ローム株式会社代理人　　　　
弁理士　中　村　茂　信第１図 第２図 第３図FIG. 1 is a plan view of a mask plate showing an embodiment of the present invention, FIG. 2 is a plan view illustrating the formation of a conventional facet cut portion of a wafer, and FIG. 3 is a plan view of a wafer. It is. 1: Wafer rod 2: Orientation flat, 3: Facet cut section, 10: Mask plate, 11 Glass plate, 12: Pattern section, 13: Transparent section, 14
:Mask part. Patent applicant ROHM Co., Ltd. agent
Patent Attorney Shigeru Nakamura Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] （１）半導体ウェハに所要のパターンを形成させるため
のパターン部と、このパターン部に隣接して設けられる
帯状の透明部と、この透明部の前記パターン部とは反対
側に隣接して設けられるマスク部とからなる半導体装置
製造用のマスク板。(1) A pattern section for forming a desired pattern on a semiconductor wafer, a band-shaped transparent section provided adjacent to this pattern section, and a band-shaped transparent section provided adjacent to the opposite side of the transparent section from the pattern section. A mask plate for manufacturing semiconductor devices consisting of a mask part.
JP60105310A 1985-05-16 1985-05-16 Mask plate for manufacturing semiconductor device Granted JPS61263124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60105310A JPS61263124A (en) 1985-05-16 1985-05-16 Mask plate for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60105310A JPS61263124A (en) 1985-05-16 1985-05-16 Mask plate for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS61263124A true JPS61263124A (en) 1986-11-21
JPH0466094B2 JPH0466094B2 (en) 1992-10-22

Family

ID=14404129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60105310A Granted JPS61263124A (en) 1985-05-16 1985-05-16 Mask plate for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS61263124A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1278236A1 (en) * 2001-07-09 2003-01-22 Sanyo Electric Co., Ltd. Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1278236A1 (en) * 2001-07-09 2003-01-22 Sanyo Electric Co., Ltd. Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed
US6897126B2 (en) 2001-07-09 2005-05-24 Sanyo Electric, Co., Ltd. Semiconductor device manufacturing method using mask slanting from orientation flat
CN100466170C (en) * 2001-07-09 2009-03-04 三洋电机株式会社 Method for making compound semiconductor device

Also Published As

Publication number Publication date
JPH0466094B2 (en) 1992-10-22

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