JPS6121524A - High speed data collecting system - Google Patents

Abstract

PURPOSE:To obtain a simple and inexpensive high-speed data collection system with excellent versatility by selecting a gain required for each channel signal by a variable gain amplifier circuit after each channel is selected by a multiplexer circuit. CONSTITUTION:A detection signal from detectors 111-11n is selected by a multiplexer MPX circuit 13 and fed to a variable gain amplifier 171 of an amplifier circuit 17. The variable gain amplifier 171 amplifies an input signal with a gain set by a gain setting circuit 172 comprising plural stages of resistors R1- Rm and switches S1-Sm. An output of the amplifier 171 is converted into a digital signal by a sample-and-hold circuit 14 and an A/D converter circuit 15 and collected by a data acquisition computer 16. The computer 16 uses software to generate a channel switching signal (a) and generate a gain switching signal (b) by means of a switching signal generating means 161. The gain switching signal (b) changes over the switches S1-Sm to control switchingly the amplifier 171 to the gain in response to a channel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed data acquisition system for low-level analog signals, and particularly to an improved system having a simple and inexpensive configuration and excellent versatility.

[Prior Art] A conventional high-speed data acquisition system for low-level analog signals is generally configured as shown in FIG. That is, each low-level analog signal from the various detectors 111 to lln (each system is indicated by a channel Chi to Chn)
is the amplifier 1 corresponding to each channel on a one-to-one basis.
21 to 12n are amplified into signals of the same level, and then supplied to a multiplexer circuit (hereinafter abbreviated as MPX circuit) 13. This MPX circuit 13 switches channels (this is called scanning) in response to a channel switching signal a'' from the data acquisition computer device 16.
Each signal from l to Chn is sequentially output.

The signal output from this MPX circuit 13 is quantized by a sample hold circuit 14, encoded by an analog-to-digital (hereinafter abbreviated as A/D) conversion circuit 15, and converted into a digital signal. input to device 16; When scanning of all channels from Chl to Chn is completed, the above operation is repeated from the beginning to acquire data at the next time, and this is then repeated to acquire all data at the necessary time.

[Problems to be solved by the invention] However, in the conventional high-speed data acquisition system as described above, it is necessary to provide an amplifier for each channel in a one-to-one ratio, and the cost ratio of these amplifiers to the entire system is high. There are problems in that it is large and has a complicated configuration, and requires a lot of time for adjustment and calibration work.

Incidentally, as a means to improve the problems of the above system, a system as shown in FIG. 5 has been considered.

That is, in this system, the detection signals from each of the detectors 111 to Un are input directly to the MPX circuit 13, and one amplifier 12 is provided at the subsequent stage, and its function is as shown in FIG. are equivalent. However, in the system shown in FIG. 5, since there is only one amplifier 12, the signals of each channel can only handle the same level, that is, the same type of signals, which limits its range of application. , the problem arises that it is extremely lacking in versatility.

The present invention was made in order to improve the above-mentioned problems, and aims to provide a high-speed data acquisition system for low-level analog signals that has a simple and inexpensive configuration and is highly versatile.

[Means for solving the problem] That is, the high-speed data collection system according to the present invention has the following features:
Supplying multiple channels of low-level analog signals to a multiplexer circuit and outputting them in response to a channel switching signal, and amplifying the output signal of the multiplexer circuit by switching the gain in accordance with the gain switching signal using a variable gain amplifier circuit, The output of this variable gain amplifier circuit is sampled and held in synchronization with the switching cycle of the channel switching signal, and then converted into a digital signal. In addition to performing data acquisition, the data acquisition computer device generates the channel switching signal and gain switching signal. In particular, the channel selection and gain selection using the channel switching signal and gain switching signal may be set in the order of channel arrangement, but may also be set so that the gains required for each channel are performed in the same order.

[Effect]

In other words, this high-speed data acquisition system uses a multiplexer circuit to select each channel and then a variable gain amplifier circuit to select the gain required for each channel signal, thereby reducing the need for an amplifier for each channel. Since only one variable gain amplifier circuit is required, the configuration is simple and inexpensive with excellent versatility.Also, by selecting channels in order of the same gain, the number of times the variable gain amplifier circuit is switched can be reduced. This can speed up collection.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. However, in FIG. 1, the same parts as in FIG. Only the different parts will be described here.

FIG. 1 shows its configuration, in which the detectors 111 to 1
The detection signal from 1n is supplied to the variable gain amplifier 171 of the amplifier circuit 1γ via the MPX circuit 13. This variable gain amplifier 171 has a gain *rk e rFRI made up of multiple stages of resistors R1 to R1 and switches 81 to 5I11.
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The output of this amplifier 171 is converted into a digital signal by the sample hold circuit 14 and the A/D conversion circuit 15, and then sent to the data acquisition computer device 1.
Collected at q. This computer device 16 has a switching signal generating means 161 that generates the channel switching signal a and a gain switching signal S using software, and the gain switching signal S is supplied to the gain setting circuit 172. , for controlling the variable gain amplifier 171 to a predetermined gain by switching the switches 81 to 5Ill.

The operation of the above configuration will be described below with reference to FIGS. 2 and 3. Incidentally, in order to simplify the explanation, FIG. 2 shows the case of a channel order scanning method, which will be described later.

First, each channel Chl to C of the detectors 111 to 11n
The output of hn, the force 3N ~ Sin is shown in Figure 2 (al) ~ (an
) is supplied to the MPX circuit 13 as shown in FIG. These channel outputs 3i1 to Sin are:
As shown in FIG. 2(b), all channels are switched by the MPX circuit 13 at each time TR (the time required to acquire one data of one channel, called sampling time). (J1 to Chn signals are 1
It is converted into a signal SMPX in a connected state. The output signal SMPX of this MPX circuit 13 is a low-level signal, and its level also varies greatly (for example, several μv to several mV) depending on the type of signal (for example, detection by a thermal lightning pair, strain gauge, thermistor, etc.). Figure 2 (C)
As shown in FIG. 2, the signal is amplified by a variable gain amplifier 171 with a gain corresponding to each channel Ch1 to Chn, and at the same time is converted into a signal 5PGA with the same level. The output signal 5POA of the variable gain amplifier 171 is held by the sample and hold circuit 14 so that its value remains constant during the TR time, and becomes a signal 88H as shown in FIG. 2(d). The output signal 5sii of this sample hold circuit 14 is converted into a digital signal SA by an A/D converter 15.
D and collected in a data acquisition computer device.

Here, the switching signal generating means of the data acquisition computer II will be explained with reference to Tables 1 and 2.

Table 1 Table 2 Mlol
r1= l't'iT Now, the signals to be collected are Chr, Ch2, -, C; h as shown in Table 1.
It is assumed that there are n channels, and each channel has a corresponding amplification gain required for data acquisition.

The gain is Gl, G2,..., depending on the type of signal.
It is assumed that there are m ways of Qm (normally, even if the number n of signal channels is large, there are at most several types of signal channels, so the number m of signal types is also about several). In this case, the gain of the variable gain amplifier 111 is set by the gain setting circuit 112.
, G2,..., GO+. The switching signal generating means generates a channel switching signal a and a gain switching signal S so as to switch the gain of the variable gain amplifier 171 to a gain corresponding to the channel being scanned at a certain point in time.

Further, the switching signal generating means changes the scanning (switching) order of the MPX circuit 13 to Chl, Ch2, . . . in order to further speed up data collection.

Instead of sorting channels up to Ch'n in order of channel number (array), as shown in Table 2, the channels are sorted by the same gain (this is called gain sorting), and each channel is sorted so that scanning is performed according to this order. The switching signals a and b may also be generated.

In other words, in the channel order scanning method shown in Table 1, it is necessary to switch channels at the times indicated by ← in the table, and this number of times M is extremely small compared to the number of signal types (i.e., the number of gain types) m. There is also a possibility that the maximum number of channels is equal to n. That is, if the sampling time of one channel is Tc, the time required to switch the gain of the R% variable amplifier circuit 171 (i.e., the operating time of the switches 81 to SL of the gain setting circuit 172) corresponds to Table 1. The timing chart is shown in Figure 3 (a
), all channels Ch1~Qh at one time
The time TEA required to acquire n data is Ts A = n TR + MTO = (1). The above gain setting port T! Reed switches can be used as the switches 81 to S11 of the 1172, but since these are mechanical contacts, the operating time Tc is longer than TH, that is, TR<TC! Equation (1) means that the time T8A required for data acquisition becomes long, and is not suitable for high-speed data collection.

Therefore, when the gain sorting order scanning method is adopted as shown in Table 2, the timing chart corresponding to Table 2 becomes as shown in FIG. 3(b), and the data acquisition time TBB is Since the number of times is the same as the number of signal types m, T's e-nTt< +mTc
'=・I'ZI. Here, since m is sufficiently smaller than M, Tse is a sufficiently shorter time than TBA. That is, in the gain sorting scanning method, the time TUB required for data acquisition can be significantly shortened, so data collection can be speeded up. Incidentally, the gain sorting for scanning and the switching signal generating means for controlling the scanning can be easily realized because they can all be performed by software of the data acquisition computer device 16.
This makes it possible to easily perform post-processing such as data checking and reverse sorting.

Therefore, in the high-speed data acquisition system configured as described above, a large number of amplifiers can be integrated into one amplifier circuit, thereby making it possible to significantly reduce costs and shorten adjustment and calibration work. Furthermore, the variable gain amplifier allows the gain to be freely set for each signal even when different types of signals coexist, resulting in high versatility. Furthermore, if a gain sorting order scanning method is used, data collection can be speeded up.

[Effects of the Invention] As detailed above, according to the present invention, there is provided a multiplexer circuit that switches and outputs low-level analog signals of a plurality of channels according to a channel switching signal, and a gain switching signal that inputs the output signal of this multiplexer circuit. a variable gain amplifier circuit that switches and amplifies the gain according to the channel switching signal; an analog-to-digital converter that samples and holds the output of the variable gain amplifier circuit in synchronization with the switching cycle of the channel switching signal and converts it into a digital signal; a data acquisition computer device having switching signal generation means for inputting the output of the analog-to-digital conversion means to collect data and generating the channel switching signal and the gain switching signal; in particular, the switching signal generation means; The means generates the channel switching signal and the gain switching signal so that the channel selection and gain selection are performed in the order of channel arrangement, or the means generates the channel switching signal and the gain switching signal so that the channel selection and gain selection are performed in the same order of the required gain of each channel. By generating the switching signal and the gain switching signal, it is possible to provide a high-speed data acquisition system for low-level analog signals that has a simple and inexpensive configuration and is highly versatile.

[Brief explanation of the drawing]

FIG. 1 is a block circuit configuration diagram showing an embodiment of a high-speed data acquisition system according to the present invention, FIGS. 2 and 3 are diagrams for explaining the operation and switching control means of the embodiment, respectively, and FIG. 5 and 5 are block circuit configuration diagrams showing the configuration of a conventional high-speed data acquisition system, respectively. 111-11n...detector, 121-12n...amplifier, 1.3...MPX circuit, 14...sample hold circuit, 15...A/D conversion circuit, 16...data acquisition 161... Switching signal generation means, 17... Amplifying circuit, 171... Variable gain amplifier, 172... Gain setting circuit,... Channel switching signal, b... Gain switching signal .

Claims (3)

[Claims] (1) A multiplexer circuit that switches and outputs low-level analog signals of multiple channels according to a channel switching signal, and a variable gain amplifier circuit that inputs the output signal of this multiplexer circuit and amplifies it by switching the gain according to the gain switching signal. , analog-to-digital conversion means for sampling and holding the output of the variable gain amplifier circuit in synchronization with the switching cycle of the channel switching signal and converting it into a digital signal; and data collection by inputting the output of the analog-to-digital conversion means. 1. A high-speed data acquisition system, comprising: a data acquisition computer device having switching signal generation means for performing the channel switching signal and the gain switching signal. (2) The high-speed data according to claim 1, wherein the switching signal generating means generates the channel switching signal and the gain switching signal so that channel selection and gain selection are performed in the order of channel arrangement. Collection system. (3) The switching signal generating means generates the channel switching signal and the gain switching signal, respectively, so that channel selection and gain selection are performed in the same order of gains required by each channel. The high-speed data collection system according to paragraph 1.