JPS609661B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS609661B2 JPS609661B2 JP54085686A JP8568679A JPS609661B2 JP S609661 B2 JPS609661 B2 JP S609661B2 JP 54085686 A JP54085686 A JP 54085686A JP 8568679 A JP8568679 A JP 8568679A JP S609661 B2 JPS609661 B2 JP S609661B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor wafer
- manufacturing
- view
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】
この発明は、PN接合を有する半導体ウェハから複数の
半導体べレットを打ち抜き、抜き取る半導体装置の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor pellets are punched out from a semiconductor wafer having a PN junction.
従来、1枚の半導体ウェハから複数個の半導体装置を製
造する場合、半導体ゥェハを打ち抜き、抜き取って複数
個の半導体べレットを得た後、この各半導体べレットに
それぞれ電極金属をろう付けして製造していた。Conventionally, when manufacturing multiple semiconductor devices from a single semiconductor wafer, the semiconductor wafer is punched and extracted to obtain multiple semiconductor pellets, and then electrode metal is brazed to each semiconductor pellet. was manufacturing.
第1図〜第5図によって、従来の半導体装置の製造方法
について説明する。A conventional method of manufacturing a semiconductor device will be explained with reference to FIGS. 1 to 5.
第1図は半導体ウェハ1の平面図であり、この半導体ゥ
ェハ1は半導体基板にフオト・エッチング法などにより
選択拡散を行なって作られ、1個以上のPN接合を有し
ている。第2図は同じく半導体ゥェハ1の平面図である
が、半導体ウェハ1表面上の抜き取ろうとするべレット
部分2aを示すものである。第3図は半導体べレット2
の平面図、第4図はその側面図である。この半導体べレ
ット2は半導体ゥェハ1のべレット部分2aを超音波、
スクラィブ、し−ザなどによって打ち抜き、抜き取るこ
とによって得られる。このようにして半導体ウヱハ1か
ら分割された半導体べレット2には、次に電極金属が取
り付けられて半導体装置が製造される。第5図はこの半
導体装置の側面図である。半導体べレツト2の下面には
モリブデン、タングステンなどからなる電極金属4がア
ルミニウム、アルミニウムシリコンなどからなるろう材
5を介してろう付けされている。このような、従釆の半
導体装置の製造方法においては、半導体ウェハから打ち
抜き、抜き取った半導体べレットに1個づつ電極金属を
ろう付けするために製造工数が長くかかり、また打ち抜
き時やろう付け時に半導体べレツトが割れ易いために製
造歩留が低下して生産性が悪くなるという欠点があった
。FIG. 1 is a plan view of a semiconductor wafer 1, which is made by selectively diffusing a semiconductor substrate by photo-etching or the like, and has one or more PN junctions. FIG. 2 is also a plan view of the semiconductor wafer 1, but shows the pellet portion 2a on the surface of the semiconductor wafer 1 to be extracted. Figure 3 shows semiconductor pellet 2
Fig. 4 is a plan view thereof, and Fig. 4 is a side view thereof. This semiconductor pellet 2 is made by applying ultrasonic waves to the pellet portion 2a of the semiconductor wafer 1.
It is obtained by punching or extracting with a scriber, a scriber, etc. Electrode metal is then attached to the semiconductor pellets 2 separated from the semiconductor wafer 1 in this manner to manufacture semiconductor devices. FIG. 5 is a side view of this semiconductor device. An electrode metal 4 made of molybdenum, tungsten, or the like is brazed to the lower surface of the semiconductor pellet 2 via a brazing material 5 made of aluminum, aluminum silicon, or the like. In such conventional semiconductor device manufacturing methods, the number of manufacturing steps is long because the semiconductor wafer is punched out and electrode metal is brazed one by one to the extracted semiconductor pellets. There is a drawback that the semiconductor pellet is easily cracked, resulting in a lower manufacturing yield and poor productivity.
さらに、半導体べレットが割れ易くなると半導体装置に
紙立ててから特性が劣化するという問題もあった。この
発明はこのような従来の欠点を除去するためになされた
もので、その目的とするところは、生産性が良く、特性
劣化もなくなるような半導体装置の製造方法を提供する
ことにある。Furthermore, if the semiconductor pellet becomes easily breakable, there is a problem in that its properties deteriorate after it is mounted on a semiconductor device. The present invention was made to eliminate these conventional drawbacks, and its purpose is to provide a method for manufacturing a semiconductor device that has good productivity and eliminates characteristic deterioration.
このような目的を達成するために、この発明は、半導体
ウェハにろう材を介して電極金属を取付け、しかる後半
導体ゥェハから半導体べレットを打ち抜き、抜き取るよ
うにしたものである。In order to achieve such an object, the present invention is such that an electrode metal is attached to a semiconductor wafer via a brazing material, and then a semiconductor pellet is punched out from the semiconductor wafer.
以下、この発明を実施例にもとづいて第6図〜第10図
にて詳細に説明する。なお、各図におし、て、第1図〜
第5図と同一または相当部分には同一符号を付してある
。第6図はこの発明に係る半導体装置の製造方法の一実
施例に用いる半導体ウヱハ1の平面図を示す。Hereinafter, this invention will be explained in detail based on examples with reference to FIGS. 6 to 10. In addition, in each figure, Figure 1~
The same or corresponding parts as in FIG. 5 are given the same reference numerals. FIG. 6 shows a plan view of a semiconductor wafer 1 used in an embodiment of the method for manufacturing a semiconductor device according to the present invention.
この半導体ゥェハ1は、位置決め用の溝3を形成した半
導体基板にフオトェッチング法により選択拡散を行ない
1個以上のPN接合を形成して作られたものである。次
に、第7図の側面図に示すように、モリブデン、タング
ステンなどの材料を円柱形に形成した複数個(本実施例
では4個)の電極金属4を円板のろう材5を介して半導
体ウェハ1の下面に設けてろう付け前の組立てを行ない
、しかる後、温度を上げてろう材5を溶解し半導体ゥェ
ハーと電極金属4とのろう付け接合を行なう。次に、半
導体ゥェハ1の打ち抜き作業を行なう。第8図は打ち抜
き時の半導体ゥェハ1の平面図、第9図はその側面図で
ある。半導体ウェハ1のべレット部分2aは電極金属4
と同一円形に形成されている。したがって、超音波、ス
クラィプ、レーザなどを用いた打ち抜き方法によってべ
レット部分2aを打ち抜くと、半導体ウェハ1から分離
されて半導体べレット2と電極金属4がろう材5でろう
付けされた状態で取りり出せる。第10図は、このよう
にして取り出された半導体装置の側面図である。この実
施例では、1個の半導体ウハから4個の半導体装置が取
り出せる。この数は半導体ゥェハの大きさおよび取り出
す半導体装置の大きさなどによって任意に設定される。
以上の実施例では、半導体べレットの径は電極金属の径
と同一にして打ち抜いたが、これより大きくてもまた小
さくてもよい。また、以上の実施例では、半導体ウェハ
の径よりかなり小さい径の電極金属を複数個用いたが、
半導体ウェハとほぼ同一径の電極金属をろう材で接合し
、その後、任意の大きさに半導体ウェハと電極金属を同
時に打ち抜いて複数個の半導体装置を取り出すこともで
きる。This semiconductor wafer 1 is made by selectively diffusing a semiconductor substrate in which positioning grooves 3 have been formed using a photo-etching method to form one or more PN junctions. Next, as shown in the side view of FIG. 7, a plurality of (four in this example) electrode metals 4 made of materials such as molybdenum or tungsten are connected through a disc brazing material 5. It is provided on the lower surface of the semiconductor wafer 1 and assembled before brazing, and then the temperature is raised to melt the brazing material 5 and the semiconductor wafer and the electrode metal 4 are joined by brazing. Next, the semiconductor wafer 1 is punched out. FIG. 8 is a plan view of the semiconductor wafer 1 during punching, and FIG. 9 is a side view thereof. The pellet portion 2a of the semiconductor wafer 1 is an electrode metal 4
It is formed in the same circular shape. Therefore, when the pellet portion 2a is punched out by a punching method using ultrasonic waves, a scraper, a laser, etc., it is separated from the semiconductor wafer 1 and taken out with the semiconductor pellet 2 and the electrode metal 4 brazed with the brazing material 5. can be released. FIG. 10 is a side view of the semiconductor device taken out in this manner. In this embodiment, four semiconductor devices can be taken out from one semiconductor wafer. This number is arbitrarily set depending on the size of the semiconductor wafer and the size of the semiconductor device to be taken out.
In the above embodiments, the diameter of the semiconductor pellet was punched out to be the same as the diameter of the electrode metal, but it may be larger or smaller than this. Furthermore, in the above embodiments, a plurality of electrode metals having a diameter considerably smaller than the diameter of the semiconductor wafer were used;
It is also possible to bond electrode metals with approximately the same diameter as the semiconductor wafer using a brazing material, and then simultaneously punch out the semiconductor wafer and the electrode metal to a desired size to take out a plurality of semiconductor devices.
さらに、半導体べレットの抜き取り形状は円形のほか、
楕円、多角形など任意の形状にすることができる。Furthermore, the shape of the semiconductor pellet when cut out is circular, as well as
It can be any shape such as an ellipse or polygon.
以上のように、この発明に係る半導体装置の製造方法に
よると、電極金属をろう材を介して半導体ゥェハにろう
付けした後に半導体べレットを抜き取るようにしたため
、製造工数が短縮され、また工程中に半導体べレットが
割れたりして製造歩留が低下することがなくなり、さら
に半導体装置に縦立ててからの歩蟹低下もなくなり、生
産性が向上してコスト低減がはかれ、かつ品質が安定し
て信頼性も増すなどの効果がある。As described above, according to the method for manufacturing a semiconductor device according to the present invention, the semiconductor pellet is removed after the electrode metal is brazed to the semiconductor wafer via the brazing material, which reduces the number of manufacturing steps and This eliminates the problem of semiconductor pellets cracking and lower manufacturing yields, and also eliminates the problem of lower manufacturing yields when vertically mounted on semiconductor devices, improving productivity, reducing costs, and stabilizing quality. This has the effect of increasing reliability.
第1図、第2図は従来の製造方法に用いる半導体ゥェハ
の平面図、第3図は半導体べレットの平面図、第4図は
その側面図、第5図は半導体装置の側面図、第6図はこ
の発明に係る半導体装置の製造方法の一実施例に用いる
半導体ウェハの平面図、第7図はろう付け時の半導体ゥ
ェハの側面図、第8図は抜き取き時の半導体ウェハの平
面図、第9図はその側面図、第10図は半導体装置の側
面図である。
各図において、同一または相当部分には同一符号を付し
てある。1・・・・・・半導体ゥェハ、2・・・・・・
半導体べレット、2a・・・・・・ベレツト部分、3・
・…・溝、4・・・・・・電極金属、5……ろう材。
氷1欧
沙2図
オ3図
才4図
オ5図
才6図
オ?図
オ8図
才9図
第10図1 and 2 are a plan view of a semiconductor wafer used in a conventional manufacturing method, FIG. 3 is a plan view of a semiconductor pellet, FIG. 4 is a side view thereof, and FIG. 5 is a side view of a semiconductor device. FIG. 6 is a plan view of a semiconductor wafer used in an embodiment of the semiconductor device manufacturing method according to the present invention, FIG. 7 is a side view of the semiconductor wafer during brazing, and FIG. 8 is a side view of the semiconductor wafer during extraction. FIG. 9 is a plan view, FIG. 9 is a side view thereof, and FIG. 10 is a side view of the semiconductor device. In each figure, the same or corresponding parts are given the same reference numerals. 1... Semiconductor wafer, 2...
Semiconductor pellet, 2a... Beret part, 3.
... Groove, 4... Electrode metal, 5... Brazing metal. Ice 1 Ousa 2 Figures O 3 Figures 4 Figures 5 Figures 6 Figures O? Figure 8 Figure 9 Figure 10
Claims (1)
ペレツトを打ち抜き、抜き取る半導体装置の製造方法に
おいて、上記半導体ウエハにろう材を介して電極金属を
ろう付けし、しかる後前記半導体ウエハから半導体ペレ
ツトを打ち抜き、抜き取るようにしたことを特徴とする
半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a plurality of semiconductor pellets are punched and extracted from a semiconductor wafer having a PN junction, wherein an electrode metal is brazed to the semiconductor wafer through a brazing material, and then semiconductor pellets are punched from the semiconductor wafer. , a method for manufacturing a semiconductor device, characterized in that the semiconductor device is extracted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54085686A JPS609661B2 (en) | 1979-07-03 | 1979-07-03 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54085686A JPS609661B2 (en) | 1979-07-03 | 1979-07-03 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS568845A JPS568845A (en) | 1981-01-29 |
JPS609661B2 true JPS609661B2 (en) | 1985-03-12 |
Family
ID=13865723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54085686A Expired JPS609661B2 (en) | 1979-07-03 | 1979-07-03 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS609661B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61152460U (en) * | 1985-03-13 | 1986-09-20 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5969151A (en) * | 1982-10-13 | 1984-04-19 | Unitika Ltd | Spherical ion exchange resin and its production and adsorptive treatment |
JPH0610234B2 (en) * | 1985-07-05 | 1994-02-09 | ユニチカ株式会社 | Microspherical cured melamine resin particles and method for producing the same |
-
1979
- 1979-07-03 JP JP54085686A patent/JPS609661B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61152460U (en) * | 1985-03-13 | 1986-09-20 |
Also Published As
Publication number | Publication date |
---|---|
JPS568845A (en) | 1981-01-29 |
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