Nothing Special   »   [go: up one dir, main page]

JPS6089951A - フリツプチツプｉｃの製造方法 - Google Patents

フリツプチツプｉｃの製造方法

Info

Publication number
JPS6089951A
JPS6089951A JP58198599A JP19859983A JPS6089951A JP S6089951 A JPS6089951 A JP S6089951A JP 58198599 A JP58198599 A JP 58198599A JP 19859983 A JP19859983 A JP 19859983A JP S6089951 A JPS6089951 A JP S6089951A
Authority
JP
Japan
Prior art keywords
bump
flip chip
electrode pad
forming
semiconductor pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58198599A
Other languages
English (en)
Inventor
Masahide Murakami
村上　正秀
Toshio Komiyama
込山　利男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58198599A priority Critical patent/JPS6089951A/ja
Publication of JPS6089951A publication Critical patent/JPS6089951A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、フリップチップＩＣのノ（ンプの形成方法に
関するものでおる。
従来、フリップチップＩＣのバンブは、）・ンダ。
ＡＪ、Ａｇ−８ｎによって、次の方法により形成される
、まず半導体ペレットの電極パッドにＣｒ又はＴｉを接
着用金属として薄く蒸着し、その後バング金属をメッキ
により付着して７７１部分を残してエツチング除去して
作られる。上記のバンプ形成方法は、通常のワイヤディ
ングが行われる半導体ペレットと比較して製造工程が長
くなシ。
コスト高となる為、多品種少量生産には不向きであると
いう欠点がおった。
本発明の目的は、多品種少量生産に適した上記バンブを
容易に形成できる方法を提供することにある。
本発明の特徴は、半導体ペレットの電極パッド上に形成
されるバンプをワイヤボンディング法により形成するこ
とにある。
本発明によれば、ワイヤボンディング法により容易にバ
ンブが形成できるので、従来のバンプ形成と比較して工
程が短くなυコストも安くなる。
さらに、上記方法で形成したフリップチップＩＣを多品
種少量生産の混成集積回路に使用すれば、従来のように
半導体ペレットをワイヤボンディング法により実装した
混成集積回路と比較して実装密度が大きくなり小形化が
計られる。
次に本発明の一実施例について説明する。
第１図のように半導体ペレット１の電極パッド２上にネ
ールへラドボンディングを２回行うことによってＡｕま
たはＡＩボール３でＡｕまたはＡｌバンプ４を形成する
。以上方法で製造したフリップチップＩＣ５を薄膜６で
形成された回路パターン上に超音波ボンディング法によ
り接合させる。
上記方法で７リツプチツプＩＣのバンプを形成すること
によシ、多品種少量生産に逸したフリップチップＩＣが
低コストで容易に製造することができる。
以上本発明について一実施例をあげて説明したがこの発
明についての技術的範囲は上記実施例に限定されるもの
ではなく、本発明についての特許権は特許請求の範囲に
記す全ての方法に及ぶ。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図である。第２図は本
発明で製造されたフリップチップＩＣの実施例の断面図
である。 １・・・・・・半導体ペレット、２・・・・・・電極パ
ッド、３・・・・・・ＡｕまたはＡ７ボール、４・・・
・・・ＡｕまたはＭバンプ、５・・・・・・フリップチ
ップＩＣ１６・・・・・・薄膜。 ７・・・・・・キャピラリ、８・・・・・・セラミック
基板。

Claims (1)

    【特許請求の範囲】
  1. 半導体ペレツウの電極パッド上に形成されるノくンブを
    ワイヤボンディング法によυ形成することを特徴とする
    フリップチップＩＣの製造方法。
JP58198599A 1983-10-24 1983-10-24 フリツプチツプｉｃの製造方法 Pending JPS6089951A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58198599A JPS6089951A (ja) 1983-10-24 1983-10-24 フリツプチツプｉｃの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58198599A JPS6089951A (ja) 1983-10-24 1983-10-24 フリツプチツプｉｃの製造方法

Publications (1)

Publication Number Publication Date
JPS6089951A true JPS6089951A (ja) 1985-05-20

Family

ID=16393871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58198599A Pending JPS6089951A (ja) 1983-10-24 1983-10-24 フリツプチツプｉｃの製造方法

Country Status (1)

Country Link
JP (1) JPS6089951A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955523A (en) * 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
US5189507A (en) * 1986-12-17 1993-02-23 Raychem Corporation Interconnection of electronic components
US5478007A (en) * 1993-04-14 1995-12-26 Amkor Electronics, Inc. Method for interconnection of integrated circuit chip and substrate
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
DE4334715B4 (de) * 1993-10-12 2007-04-19 Robert Bosch Gmbh Verfahren zur Montage von mit elektrischen Anschlüssen versehenen Bauteilen

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955523A (en) * 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
US5189507A (en) * 1986-12-17 1993-02-23 Raychem Corporation Interconnection of electronic components
US5478007A (en) * 1993-04-14 1995-12-26 Amkor Electronics, Inc. Method for interconnection of integrated circuit chip and substrate
DE4334715B4 (de) * 1993-10-12 2007-04-19 Robert Bosch Gmbh Verfahren zur Montage von mit elektrischen Anschlüssen versehenen Bauteilen
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6163463A (en) * 1996-12-06 2000-12-19 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection

Similar Documents

Publication Publication Date Title
JP3526731B2 (ja) 半導体装置およびその製造方法
JP2828021B2 (ja) ベアチップ実装構造及び製造方法
US7598121B2 (en) Method of manufacturing a semiconductor device
JP2005072587A (ja) Ｂｇａパッケージ、パッケージ積層構造及びその製造方法
JPS6089951A (ja) フリツプチツプｉｃの製造方法
US6984877B2 (en) Bumped chip carrier package using lead frame and method for manufacturing the same
JP2000164617A (ja) チップサイズパッケージおよびその製造方法
JP4360873B2 (ja) ウエハレベルｃｓｐの製造方法
JPS61214444A (ja) 半導体装置
JPH01161850A (ja) 半導体装置の製造方法
JP2992460B2 (ja) 半導体パッケージ及びその製造方法
JPS62147735A (ja) フリツプチツプの製法
JPS62150837A (ja) 半導体装置
KR100871371B1 (ko) 센터 패드 칩의 스택 패키지 및 그 제조방법
JP2006041224A (ja) 電子装置および電子装置の実装構造
JPS6041728Y2 (ja) 半導体装置
JP4002220B2 (ja) 半導体装置の製造方法
KR100192759B1 (ko) 범프 칩 스케일 패키지의 범프 형성방법
JP2000307032A (ja) チップスケールパッケージ及びその製造方法
JPH1167838A (ja) バンプ付電子部品の製造方法
JPH10107075A (ja) 半導体装置及びその製造方法
JP2549278Y2 (ja) 混成集積回路基板
JPH11224888A (ja) 半導体装置およびその製造方法
JPH0338847A (ja) 混成集積回路装置の製造方法
JP3615368B2 (ja) チップサイズパッケージ及びその製造方法