JPS60242681A - Field-feeect transistor - Google Patents
Field-feeect transistorInfo
- Publication number
- JPS60242681A JPS60242681A JP9930184A JP9930184A JPS60242681A JP S60242681 A JPS60242681 A JP S60242681A JP 9930184 A JP9930184 A JP 9930184A JP 9930184 A JP9930184 A JP 9930184A JP S60242681 A JPS60242681 A JP S60242681A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- epitaxial layer
- region
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は接合型電界効果トランジスタに関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a junction field effect transistor.
従来、電界効果トランジスタ（以下本明細書においては
Ｆ Ｅ Ｔ （Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓ
ｉｓｔｏｒ ）と略記する。）には、第７図に示ｊ Ｍ
ＯＳ （ＭｅｔａｌＯｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕ
ｃｔｏｒ ） ｍと第８図に示す接合型がある。図中、
ｌはｐ型シリコン基板、２および３はそれぞれソースお
よびドレインの役χするｎ型領域、４は５ｉＱ２層、５
はｎ型拡散領域、６はｐ型拡散領域、Ｓ、Ｇ、およびＤ
はＡ７！で形成されたそれぞれソース電極、ゲート電極
、およびドレイン寛＆ン示す。Conventionally, a field effect transistor (hereinafter referred to as FET (Field Effect Transistor) in this specification) has been used.
istor). ) is shown in Figure 7.
OS (MetalOxide Sem1condu
There are two types of junctions: ctor) m and the junction type shown in Fig. 8. In the figure,
1 is a p-type silicon substrate, 2 and 3 are n-type regions serving as a source and a drain, respectively, 4 is a 5iQ2 layer, and 5
is an n-type diffusion region, 6 is a p-type diffusion region, S, G, and D
is A7! The source electrode, gate electrode, and drain electrode formed respectively are shown.
ＭＯＳ−ＦＥＴでは担体のチャネルがＳ １０２−８ｊ
界面に形成されるから、５ｉ０２−８ｉ界面の結晶の乱
れに伴う界面散乱が生じ、それが担体の速度ン小さくし
ている。また、接合型ＦＥＴでは、チャネルが拡散層中
に形成されるから、高濃度のイオン化した不純物による
散乱が生じ、担体の速度ン小す（シている。したがって
、いずれの型のＦＥＴにおいても高速化に限界があった
。In MOS-FET, the carrier channel is S102-8j
Since it is formed at the interface, interface scattering occurs due to crystal disorder at the 5i02-8i interface, which reduces the velocity of the carrier. Also, in junction FETs, since the channel is formed in a diffusion layer, scattering due to high concentrations of ionized impurities occurs, reducing the carrier velocity. There were limits to the
したがって、本発明の目的は高速動作のＦＥＴン提供す
ることである。Accordingly, it is an object of the present invention to provide a fast operating FET.
上記目的ン達成するために、本発明によるＦＥＴは牛４
＃一基板の表面の所定の領域に設けられた第１導ｔｈ型
の埋込み層と、上記基板および上記埋込み層の上に設け
られた、上記第１埠亀型とは反対の第２導電型のエピタ
キシャル層と、該エピタキシャル１１の表面領域の上記
埋込み層を挾む位置に設けられた第２専軍型の高不純物
濃度領域とン含み、上記高不純物濃度領域がソースおよ
びドレインの役ンし、上記埋込み１−がゲートの役ンす
ることン要旨とする。In order to achieve the above object, the FET according to the present invention
#1 A buried layer of a first conductivity type provided in a predetermined region on the surface of the substrate; and a second conductivity type opposite to the first Noguchi type provided on the substrate and the buried layer. and a second exclusive type high impurity concentration region provided at a position sandwiching the buried layer in the surface region of the epitaxial layer 11, and the high impurity concentration region serves as a source and a drain. , the gist is that the embedding 1- serves as a gate.
以下に、図面馨参照しながら、実施例〉用いて本発明を
一層詳細に説明するが、それらは例示に過き゛ず、本発
明の枠を越えることなしにいろいろな変形や改良があり
得ることは勿鵬である。The present invention will be described in more detail below using examples with reference to the drawings, but these are merely illustrative and it is understood that various modifications and improvements may be made without going beyond the scope of the present invention. It's Mu Peng.
第１脂は本発明にょるＦ Ｅ Ｔ （７）構造を示す断
面図で、図中第７図と共通する引用番号は対応する部分
ン表わす。ｐ型シリコン基板工の表面の所定の領域にｐ
ｍ埋込み層７馨設ける。ついで、ｐ＋ｍ埋込み層７ン含
むｐ型シリコン基叛１の全表面にｎ−５エピタキシヤル
鳩８ン形成する。その後、所定の領域にｎ１工ピタキシ
ヤル層８’ｔＸｍしてｐ型不純物ン孤散し、ゲートｔ！
Ｌ極取出しロリン設ける。ｎ″″ｍエピタキシャル層８
０層面０表面ｐ型埋込み層７ｇ挾む二つの位置にｎ型不
純物ン拡散し、＋
ｎ型領域２および３を作る。全体をＳ ｉｏｚ層４で被
榎した後、ゲート奄＆Ｇ、ソースＩＩ他Ｓ、およびドレ
イン′＃Ｌ極Ｄｉ形成する。１ｏはｐ−ｎ接合空乏層ン
表わし、１１は５ｉ０２− Ｓｉ界面及転層馨意味し、
１２カ埋込ｈａ ７ 、！： ＳｉＯ２／ｉｉ ４ ノ
ｌ’ｊｌＫ形ｇ ８ ｔＬるチャネルである。Figure 1 is a cross-sectional view showing the FET (7) structure according to the present invention, and reference numbers common to those in Figure 7 represent corresponding parts. P is applied to a predetermined area on the surface of the p-type silicon substrate.
7 m buried layers are provided. Next, an N-5 epitaxial layer 8 is formed on the entire surface of the p-type silicon substrate 1, including the p+m buried layer 7. Thereafter, an n1 pitaxial layer 8'tXm is formed in a predetermined region to scatter p-type impurities, and the gate t!
Provide L-pole extraction roller. n″″m epitaxial layer 8
An n-type impurity is diffused into two positions sandwiching the p-type buried layer 7g on the 0-layer surface 0-surface to form +n-type regions 2 and 3. After covering the entire structure with Sioz layer 4, gate layer &G, source II and S, and drain '#L pole Di are formed. 1o represents the p-n junction depletion layer, 11 represents the 5i02-Si interface and inversion layer,
12 cards embedded ha 7,! : SiO2/ii 4 nol'jlK type g 8 tL channel.
第１図にＦＥＴはっき゛のように動作する。ゲート電極
Ｇに印加されるバイアスル圧によってゲート電極Ｇと等
電位の埋込み層７とエピタキシャル層８のｐ −ｎ接合
に生じるを乏層１ｏの淳さｔ制御し、ソース−ドレイン
間に流れるドレイン電流を制御する。The FET operates as shown in FIG. The bias voltage applied to the gate electrode G controls the drain current flowing between the source and the drain by controlling the drain current generated at the p-n junction between the buried layer 7 and the epitaxial layer 8, which are at the same potential as the gate electrode G, in the depletion layer 1o. control.
ｒ ｏ）Ｆ Ｅ Ｔの動作を図解すると第２図（ａｌお
よび（ｂｌのようになる。ゲート電圧Ｖａ ＝ ０で第
２図（ａ）のようにチャネルが形成されるテグレッショ
ン型であり、Ｖａ ｋ負にバイアス馨かけてぃ（と、チ
ャネルは狭くなり、あるバイアスでチャネルは消失し、
ドレイン電流は流れな（なる。本発明にょるＦＥＴでは
、チャネルがエピタキシャル層に形成されるから、高い
担体速度が得られる。The operation of r o) FET is illustrated in Figure 2 (al and (bl). It is a regression type in which a channel is formed as shown in Figure 2 (a) when the gate voltage Va = 0, If you apply a negative bias, the channel will become narrower, and at a certain bias the channel will disappear,
No drain current flows. In the FET according to the present invention, a high carrier velocity can be obtained because the channel is formed in the epitaxial layer.
本発明によるＦＥＴは、第３囚に示すゲート端子取出し
乞行なえは、ｎ型半導体基板の上にも形成することかで
きる。第４図は第３図のＩＶ−Ｎ腺に沿って切った断面
図馨示す。図中１′はｎ型シリコン基８！ン表わす。The FET according to the present invention can also be formed on an n-type semiconductor substrate, except for the gate terminal shown in the third example. FIG. 4 shows a cross-sectional view taken along the IV-N gland in FIG. In the figure, 1' is an n-type silicon group 8! to represent.
本発明によるＦＥＴは第５図およびあ６図に示すように
いろいろの汲形ン考えることができる。The FET according to the present invention can be designed in various shapes as shown in FIGS. 5 and 6.
第５図は、ｎ−型エピタキシャルｆＷ１８のチャネル領
域１２にＳｉＯ２層４に接して薄いｐ型層１３を設けた
構造χ示し、この構造では５ｉ０２ Ｓｉ界面Ｑ結晶の
乱れに伴う不都合が避けられる。第６−は従来のＭ Ｏ
Ｓ −ＦＢ Ｔと本発明によるＦＥＴの組み合わせたＳ
造ン示し、この構造では大きな電流音制御することがで
さるという利点が得られる。第５図および第６図に示″
ｆｔａ造においても、前と同様に、シリコン基数ｌはｎ
型であることもｐ型であることもできる。FIG. 5 shows a structure χ in which a thin p-type layer 13 is provided in the channel region 12 of the n-type epitaxial fW 18 in contact with the SiO2 layer 4, and this structure avoids the disadvantages associated with disorder of the 5i02 Si interface Q crystal. No. 6- is the conventional M.O.
S-FBT combined with FET according to the present invention
This structure has the advantage of being able to control large current noises. As shown in Figures 5 and 6.
In the fta structure, as before, the silicon base number l is n
It can be either type or p-type.
以上説明した通り、本発明によれば、高速動作のＦＥＴ
Ｙ得ることができる。As explained above, according to the present invention, a high-speed operation FET
You can get Y.
第１図は本発明によるＦＥＴの断面図、第２図（ａｌお
よび（ｂｌは本発明によるＦＥＴの動作ン説明するため
のチャネル部のエネルギ・バンド図、第３図は本発明の
他の一つの態様にｌるＦＥＴの上面図、第４図は第３図
のＦＥＴンバー１ｖ線に沿って切った断面図、第５図お
よび第６図は本発明のさらに他の二つの異った実施の態
様によるＦＥＴの断面図、第７図はＭ ＯＳ −Ｆ Ｅ
Ｔの断面図、第８図は従来の接合型ＦＥＴの断面図で
ある。
１．１′・・・シリコン基板、２・・・ソース、３・−
・ドレイン、４・・・ＳｉＯ２層、５・・・ｎ型−散層
、６・・・ｐ型拡散層、７・・・ｐ型埋込み層、８・・
・ｎ型エピタキシャル層、９・・・ケート′ｆＭ極取出
し口、１ｏ・・・ｐ−ｎ接合空乏層、１ｊ・・・５ｉ０
２ Ｓｉ界面及転層、］２・・・チャネル、１３・・・
薄り・ｐ型層、Ｓ・・・ソース電極、Ｄ・・・ドレイン
ＩＩＩ極、Ｇ・・・ゲート電極。
特許出願人 タラリオン株式会宅
代理人 升埋士 水 １）武 三 Ｒ
第１図
（ａ） （ｂ）
第３図
第５図
第４図FIG. 1 is a sectional view of the FET according to the present invention, FIG. 2 (al and (bl) are energy band diagrams of the channel portion for explaining the operation of the FET according to the present invention, and FIG. FIG. 4 is a cross-sectional view taken along line 1v of the FET shown in FIG. 3, and FIGS. FIG. 7 is a cross-sectional view of the FET according to the embodiment of
8 is a cross-sectional view of a conventional junction FET. 1.1'...Silicon substrate, 2...Source, 3.-
- Drain, 4... SiO2 layer, 5... n-type diffused layer, 6... p-type diffused layer, 7... p-type buried layer, 8...
・N-type epitaxial layer, 9...Kate'fM pole outlet, 1o...pn junction depletion layer, 1j...5i0
2 Si interface and transfer layer,] 2...channel, 13...
Thin p-type layer, S...source electrode, D...drain III pole, G...gate electrode. Patent Applicant Tararion Co., Ltd. Real Estate Agent Masuji Mizu 1) Takezo R Figure 1 (a) (b) Figure 3 Figure 5 Figure 4
Claims (1)
の埋込み層と、上記基板および上記埋込み層の上に設け
られた、上記第１導電、型とは反対の第２４亀型のエピ
タキシャル層と、該エピタキシャル層の表面領域の上記
埋込み層ン挾む位置に設けられた第２４霜、型の高不純
物濃度領域と馨含み、上記高不純物濃度領域がソースお
よびドレインの役ンし、上記埋込み層がゲートの役ンす
ることン特徴とする電界効果トランジスタ。a 14th tortoise-shaped buried layer provided in a predetermined region on a surface of a semiconductor substrate; and a 24th tortoise-shaped epitaxial layer opposite to the first conductive type and provided on the substrate and the buried layer. the epitaxial layer, and a high impurity concentration region of a 24th type provided at a position sandwiching the buried layer in the surface region of the epitaxial layer, the high impurity concentration region serving as a source and a drain; A field effect transistor characterized by a buried layer serving as a gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9930184A JPS60242681A (en) | 1984-05-16 | 1984-05-16 | Field-feeect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9930184A JPS60242681A (en) | 1984-05-16 | 1984-05-16 | Field-feeect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60242681A true JPS60242681A (en) | 1985-12-02 |
Family
ID=14243801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9930184A Pending JPS60242681A (en) | 1984-05-16 | 1984-05-16 | Field-feeect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60242681A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008137309A1 (en) * | 2007-05-03 | 2008-11-13 | Dsm Solutions, Inc. | Inverted junction field effect transistor and method of forming thereof |
-
1984
- 1984-05-16 JP JP9930184A patent/JPS60242681A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008137309A1 (en) * | 2007-05-03 | 2008-11-13 | Dsm Solutions, Inc. | Inverted junction field effect transistor and method of forming thereof |
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