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JPS6469046A - Manufacture of bi-mos integrated circuit device - Google Patents

Manufacture of bi-mos integrated circuit device

Info

Publication number
JPS6469046A
JPS6469046A JP22711087A JP22711087A JPS6469046A JP S6469046 A JPS6469046 A JP S6469046A JP 22711087 A JP22711087 A JP 22711087A JP 22711087 A JP22711087 A JP 22711087A JP S6469046 A JPS6469046 A JP S6469046A
Authority
JP
Japan
Prior art keywords
emitter
polycrystalline silicon
silicon layers
film
temperature fluid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22711087A
Other languages
Japanese (ja)
Inventor
Yasuo Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22711087A priority Critical patent/JPS6469046A/en
Publication of JPS6469046A publication Critical patent/JPS6469046A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To inhibit the generation of a short circuit between an emitter and a base by executing the reflow heat treatment of a high temperature fluid insulating film such as a BPSG film under a nitrogen gas atmosphere. CONSTITUTION:When a silicon gate MOS transistor and a bipolar transistor are formed onto the same substrate 1, polycrystalline silicon layers 8 are shaped in gate-electrode forming regions in the silicon gate MOS transistor. Polycrystalline silicon layers 11 are formed in emitter forming regions in the bipolar transistor. A high-temperature fluid insulating film (BPSG film) 15 is shaped onto these polycrystalline silicon layers 8, 11, and the high-temperature fluid insulating film (BPSG film) 15 is thermally treated under an inert gas atmosphere such as nitrogen gas. Accordingly, the decrease of the film thickness and the dispersion of film thickness of the polycrystalline silicon layers 11 as emitter diffusion sources can be inhibited, thus preventing the generation of defectives such as a short circuit between an emitter and a base. Yield can be improved.
JP22711087A 1987-09-10 1987-09-10 Manufacture of bi-mos integrated circuit device Pending JPS6469046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22711087A JPS6469046A (en) 1987-09-10 1987-09-10 Manufacture of bi-mos integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22711087A JPS6469046A (en) 1987-09-10 1987-09-10 Manufacture of bi-mos integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6469046A true JPS6469046A (en) 1989-03-15

Family

ID=16855633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22711087A Pending JPS6469046A (en) 1987-09-10 1987-09-10 Manufacture of bi-mos integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6469046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172100A (en) * 1995-12-18 1997-06-30 Nec Corp Method for manufacturing semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172100A (en) * 1995-12-18 1997-06-30 Nec Corp Method for manufacturing semiconductor integrated circuit device

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