JPS643065B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a method for manufacturing a MOS integrated circuit,
In particular, it relates to a manufacturing method that allows other types of active elements such as bipolar transistors ( _Bip -T) and junction FETs (JFET) to coexist in so-called silicon gate MOS integrated circuits that use polycrystalline silicon for the gate electrode. It is something.

For integrated circuits using such mixed devices, it is necessary to simplify the manufacturing process. The gist of the present invention is primarily placed on this point. The second point is that the electrical characteristics of the various elements must not be so inferior that they impair their practicality compared to those constructed as individual elements. Thirdly, M.O.S.
Not to mention the transistor (MOST), B _ip −
The T and JFET are each electrically isolated and can be easily implemented as conventional analog integrated circuits or digital circuits such as TTL and CML.

Conventionally, many attempts have been made to incorporate _Bip -T into a MOS integrated circuit and to achieve higher functionality and characteristics with a single chip. However, this complicates the manufacturing method, lowering yield and increasing chip price _.
-No advantage was obtained compared to the case where the T was constructed with a separate chip. Incidentally, recent integrated circuits are moving toward higher integration and higher speed due to advances in technology for miniaturizing element dimensions. As a result, it has become possible to implement functions that were conventionally configured with multiple chips on a single chip. In this case, it becomes necessary to perform various types of signal processing within one chip. For example, analog signal processing, A-D conversion, or D
-A conversion, digital signal processing, input/output circuits necessary for connection with peripheral circuits, etc. must be constructed on a single chip.

One way to solve this problem is to establish circuit technology for performing analog signal processing, AD or AA conversion in MOST. but,
Low-frequency noise and long-term stability problems, which are inherent disadvantages of MOST due to being a surface device, will still remain, and in order to provide a large driving force, the device area will increase and the speed will decrease. If you do that, the deficiencies you develop will seem difficult to overcome.

Other methods MOST involve complicated internal processing.
In this way, the input/output signals, analog circuits, conversion circuits, and large drive circuits can be handled by _Bip -T or JFET, and the characteristics of each device can be fully utilized to create a streamlined circuit configuration. be.
Although the advantages of this method are obvious, MOST and B _ip
The key is to establish a practical manufacturing method for the coexistence of -T or JFET.

The present invention provides one method for this purpose.

According to the present invention, MOST and B Coexistence of _ip -T becomes possible.

The manufacturing method of the MOST according to the present invention is exactly the same as that of a conventional polycrystalline silicon gate n-channel MOST. Also, the manufacturing method of _Bip -T or JFET is
A method conventionally known as the triple diffusion method is used. The advantage of the triple diffusion method is that it does not require epitaxial growth, resulting in low cost and high yield. However, the drawbacks are that the collector series resistance is several times larger than that of the epitaxial type, and that parasitic pnpn effects are more likely to occur, which puts some restrictions on the circuits that can be realized. However, this is not a fatal drawback for most circuits unless large currents are required.
In order to reduce the number of processes even by one, MOST and
Only the source, drain, and emitter can share the same diffusion layer of B _ip -T. The most important thing here is that the current amplification factor of _Bip -T and the characteristics of MOST must be optimized with high reproducibility.

In the present invention, as a method to simultaneously reduce the number of steps and achieve good characteristics, we have developed a polycrystalline silicon gate.
The _Bip -T emitter region is simultaneously formed in the MOST direct contact (method of directly connecting the source or drain diffusion layer and the polycrystalline silicon layer) process. Therefore, the emitter diffusion layer is formed by impurity diffusion from polycrystalline silicon. With this method, the emitter of _Bip -T is always connected to the polycrystalline silicon layer as an electrode, so checking the current amplification factor or withstand voltage can be done by checking the diffusion layer for the tiny transistor that makes up the gate. This can be done during formation. The fact that the current amplification factor can be precisely controlled in this way is highly effective for mass production of _Bip -T. Furthermore, according to this method, a low resistance ratio of the polycrystalline silicon layer can be easily realized by high-density phosphorus or arsenic doping, which not only helps improve the speed of MOS circuits, but also makes it possible to use polycrystalline silicon layers for wiring in bipolar circuits. It becomes possible to use it. This has a great effect of reducing the area of the wiring region of the bipolar circuit and improving the integration density.

In order to describe the present invention in more detail, a first embodiment will be described. FIG. 1 shows a first embodiment. In FIG. 1a, 1 is a P-type silicon substrate. First, an n-type diffusion region 2 (referred to as an n-well) is selectively formed in a portion of the silicon substrate where B _ip -T is to be formed using a combination of normal ion implantation and thermal diffusion. The layer resistance of n-well 2 is B _ip
In order to lower the collector series resistance of -T, the lower the better, but since a P-type base region is formed in this region, a surface impurity concentration of about 10 ¹⁷ cm ^-3 is appropriate.
Further, the depth of the n-well 2 is determined based on the required degree of integration since it extends in the lateral direction. Usually 5~
The thickness is selected to be about 10 μm. Therefore, the layer resistance of the n-well is about 100 to 300 Ω/□, and the value of the collector series resistance can be lowered to a point where there is no problem in practical use. Next, selective oxidation is performed using the silicon nitride film 4 as a mask to form a thick oxide film 3 of about 1 μm except for the region where a transistor is to be formed (FIG. 1b). Then, only the silicon nitride film at the B _ip -T portion is removed by etching. next,
Boron is deposited into the n-well 2 by ion implantation or thermal diffusion to form the base region 5 of B _ip -T.
is formed (Fig. 1c). Then, a silicon oxide film 6 having a thickness of 0.3 to 0.5 μm is formed on the n-well by thermal oxidation. Subsequently, the silicon nitride film 4 covering the surface of the region where the MOST is to be formed is removed, and the gate oxide film 7 of the MOST is formed.
Next is the direct contact process (Fig. 1d). In this step, the direct contact 8 of the MOST, the emitter 9 of the _Bip -T, and the collector outlet 10 are opened. Polycrystalline silicon is then deposited by vapor phase growth and conventional patterning forms gate 11 and source (drain) 1.
2, an emitter 13 and a collector 14 are formed. The phosphorus is then thermally diffused (Figure 1e). At this time, since the gate oxide film 7 is usually thin, around 0.1 μm or less, it completely changes to phosphorus glass during phosphorus diffusion, and from there, phosphorus diffuses into the silicon, forming the source 15 and drain 16. It is formed.
In addition, in the B _ip -T part, phosphorus diffuses into the silicon through the polycrystalline silicon, and the emitter 17
and a collector outlet 18 are formed. Since the diffusion coefficient of phosphorus in polycrystalline silicon is large,
It becomes possible to simultaneously form the source and drain of the MOST and the emitter and collector of the _Bip -T. The diffusion time can be controlled so that the current amplification factor of _Bip -T reaches an optimum value since the junction depth conditions for the source and drain of the MOST are not so strict. Here, arsenic ion implantation may be used instead of phosphorus diffusion for forming the source, drain, and emitter. It is also possible to perform phosphorus diffusion or arsenic ion implantation after etching the gate oxide film of the MOST in the step shown in FIG. 1e. Next, after depositing CVDSiO ₂ film or PSG film 19, contact window 2
0, 21, 22 (Fig. 1 f). Here,
20 is to the source or drain of MOST, 21
is a contact window to the base of B _ip -T, and 22 is a contact window to the polycrystalline silicon layer. Subsequently, aluminum evaporation is performed, and a wiring layer 23 is formed by selective etching. In this way, the part of B _ip −T is
Like MOST, it has a two-layer wiring structure made of polycrystalline silicon and aluminum, which is extremely advantageous for high integration.

As is clear from the above description, this method only adds two steps, one for forming the n-well component and the other for forming the base diffusion layer, to the standard method for manufacturing a polycrystalline silicon gate MOS integrated circuit. this is,
It can be said that the number of steps is about the same as CMOS.
This means that a MOS bipolar integrated circuit with an excellent price/performance ratio can be realized compared to conventional MOSLSI.

By using the manufacturing method according to the present invention, a JFET can be manufactured without adding any new steps. JFET has high input impedance and
Since there is no 1/f noise, it is excellent as a first-stage amplification element in analog circuits.

A method for manufacturing a JFET will be described as a second example. FIG. 2a shows a cross section along the channel of the JFET, and FIG. 2b shows a cross section in the channel width direction.
The manufacturing method is exactly the same as the first implementation, so it is omitted.
Only the final structure is shown. In FIG. 2a, n-wells 102 and 117 constitute a gate, and 113 serves as a gate electrode. 24 is the channel area, 25
and 26 are source and drain electrodes. In FIG. 2b, gate 117 is connected to n-well 102 at the end of channel 24. In FIG. A feature of the JFET that can be manufactured according to the present invention is that the gate length can be shortened to the minimum dimension in direct contact. Therefore, it often becomes a problem when making _Bip -T and JFET at the same time. It is possible to prevent a decrease in the channel conductance of the JFET by shortening the channel. Typical B _ip −T
The layer resistance of the active base region (pinch resistance) of is approximately
It is 5KΩ/□. According to the present invention, it is easy to make the channel length 5 μm, so for example, as a practical value, in order to make the forward transfer admittance in the saturation region 5 mV at zero source-gate voltage, the channel length should be 125 μm. It's going to be a good thing. In a MOST with a gate film thickness of 0.1 μm, the channel width to obtain gm = 1 mV at a drain current of 0.5 mA is approximately 25 times the channel length, so if the channel length is 5 μm, the channel width will be 125 μm. . Therefore, it can be said that there is no big difference in the planar dimensions required to obtain the same level of DC characteristics between JFET and MOST.

Next, as a third embodiment, a manufacturing method advantageous for lowering the collector series resistance will be described. Third
In the figure, the direct contact process, that is, the process up to the opening 9 for forming the emitter region and the opening 10 for the collector outlet, is the same as in the first embodiment shown in FIG. Polycrystalline silicon is then grown and patterned to form the MOST
Only the gate electrode of Bip _- T and the emitter electrode 13 of Bip-T are left, and the collector electrode 14 shown in FIG. 1d is etched. After doing this, when impurity diffusion is performed to form the source and drain or emitter regions, since silicon is exposed in the collector opening 10, the impurity is diffused deep into the deep n ⁺ region 118. is formed. In this case, the collector electrode is formed by aluminum wiring. Therefore, since the aluminum wiring is directly connected to the deep n ⁺ region, it is effective in lowering the collector resistance.

As is clear from the above description, by implementing the present invention, _Bip -T and JFET can be integrated into a MOS integrated circuit with the same number of steps as the conventional CMOS process.
can coexist. B _ip −T and JFET are n
Because of the isolation provided by the wells, it is possible to include conventional bipolar integrated circuits within MOS integrated circuits. Therefore, extremely versatile circuits can be constructed on a single chip. Also, until now
When considering the application to MOSLSI, there are great advantages in replacing the input/output part with _Bip -T. As device dimensions become smaller, the signal current and signal amplitude of internal gates become smaller and smaller, and the interface with external circuits becomes a major problem. This problem is also solved by the fact that low voltage operation is possible and
GM, B _ip -T with high driving ability and high speed
This can be easily solved by using .

[Brief explanation of the drawing]

FIGS. 1a to 1f are cross-sectional views showing a first embodiment of the present invention in the order of steps, and FIGS. 2a and 2b are sectional views showing the second embodiment of the present invention in the order of steps. FIG. 3 is a cross-sectional view showing a third embodiment of the present invention. In the figure, 1 is a P-type silicon substrate, 2 is an n-well, 3 is a thick field oxide film, 4 is a silicon nitride film, 5 is a P-type base region, and 6 is a B _ip -T.
A thick oxide film covering the region, 7 is a MOST gate oxide film, 8 is a direct contact, 9 is an emitter hole, 10 is a collector extraction hole, 11 is a polycrystalline silicon gate, 12 is a MOST silicon electrode, 1
3 is an emitter electrode, 14 is a collector electrode, 15,
16 is the source or drain, 17 is the emitter, 1
8 is collector extraction, 19 is CVD oxide film or
PSG film, 20 is a MOST contact, 21 is a base contact, 22 is a polycrystalline silicon aluminum connection, 23 is a base aluminum electrode, 24 is a JFET channel, 25 and 26 are source or drain electrodes,
102 is the JFET back gate, 105 is a P-type source or drain region, 113 is a gate electrode, 117
is an n ⁺ type gate region, and 118 is a deep n ⁺ region.

Claims (1)

[Claims] 1. Forming a first impurity diffusion region of another conductivity type on one main surface of a semiconductor substrate of one conductivity type, and forming a second impurity diffusion region of one conductivity type in the first impurity diffusion region. a step of forming a gate insulating film on the front rail main surface apart from the first impurity diffusion region; and forming an insulating film on the surfaces of the first and second impurity diffusion regions. a step of forming a first opening in a predetermined region of the insulating film over the first impurity region, and a step of forming a second opening in a predetermined region of the insulating film over the second impurity region. and selectively forming a polycrystalline silicon layer on the gate insulating film and in the second opening to form a gate electrode and an extraction electrode, respectively, and introducing impurities of the other conductivity type, The impurity of the other conductivity type is introduced into the gate electrode and the extraction electrode, and source and drain regions are formed in a portion of the one main surface of the semiconductor substrate adjacent to the gate electrode, directly below the second opening. and forming a third impurity diffusion region of the other conductivity type.
Method of manufacturing MOS integrated circuits.