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JPS642483A - Video signal processor - Google Patents

Video signal processor

Info

Publication number
JPS642483A
JPS642483A JP62158054A JP15805487A JPS642483A JP S642483 A JPS642483 A JP S642483A JP 62158054 A JP62158054 A JP 62158054A JP 15805487 A JP15805487 A JP 15805487A JP S642483 A JPS642483 A JP S642483A
Authority
JP
Japan
Prior art keywords
memory
addresses
horizontal scanning
video signal
periods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62158054A
Other languages
Japanese (ja)
Other versions
JPH012483A (en
Inventor
Tsutomu Fukatsu
Yoshihiro Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62158054A priority Critical patent/JPS642483A/en
Publication of JPH012483A publication Critical patent/JPH012483A/en
Publication of JPS642483A publication Critical patent/JPS642483A/en
Priority to US07/715,873 priority patent/US5204754A/en
Priority to US07/982,225 priority patent/US5355256A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE: To obtain a still picture which is scanned excellently by interlacing by writing a video signal of (n+1) horizontal scanning lines successively from a 1st horizontal scanning period of a vertical synchronizing period in a memory and resetting addresses alternately at (n) horizontal scanning period intervals and (n+1) horizontal scanning period intervals.
CONSTITUTION: When the video signal of 263H periods is stored in addresses of the memory 42 which are specified by an address counter 46, the addresses are reset and the memory 42 enters a read ready state. The data are read out of the addresses of the memory 42 specified by the address counter 46. When the video signals of the 262H periods is read out, the address counter 46 is reset. Thus, a 262H detecting circuit 41 and a 263H detecting circuit 39 operate alternately. Thus, the video signals of the 262H and 263H periods are read out of the memory 42 alternately and an interlaced still picture signal having no skew is obtained.
COPYRIGHT: (C)1989,JPO&Japio
JP62158054A 1987-06-24 1987-06-24 Video signal processor Pending JPS642483A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62158054A JPS642483A (en) 1987-06-24 1987-06-24 Video signal processor
US07/715,873 US5204754A (en) 1987-06-24 1991-06-14 Video signal processing apparatus for restoring an interlaced video signal stored in a memory
US07/982,225 US5355256A (en) 1987-06-24 1992-11-25 Video signal reproducing apparatus having diverse still picture reproduction modes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158054A JPS642483A (en) 1987-06-24 1987-06-24 Video signal processor

Publications (2)

Publication Number Publication Date
JPH012483A JPH012483A (en) 1989-01-06
JPS642483A true JPS642483A (en) 1989-01-06

Family

ID=15663284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158054A Pending JPS642483A (en) 1987-06-24 1987-06-24 Video signal processor

Country Status (1)

Country Link
JP (1) JPS642483A (en)

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