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JPS5235581A - Manufacturing process of semiconductor device - Google Patents

Manufacturing process of semiconductor device

Info

Publication number
JPS5235581A
JPS5235581A JP50111420A JP11142075A JPS5235581A JP S5235581 A JPS5235581 A JP S5235581A JP 50111420 A JP50111420 A JP 50111420A JP 11142075 A JP11142075 A JP 11142075A JP S5235581 A JPS5235581 A JP S5235581A
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacturing process
chips
insulation
prevented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50111420A
Other languages
Japanese (ja)
Inventor
Masahiro Hara
Takao Yuri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50111420A priority Critical patent/JPS5235581A/en
Publication of JPS5235581A publication Critical patent/JPS5235581A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: The insulation oxidized film is formed on the lead frame except for necessary area. Thus, the short circuit taking place at the time of connection with chips can be prevented.
COPYRIGHT: (C)1977,JPO&Japio
JP50111420A 1975-09-12 1975-09-12 Manufacturing process of semiconductor device Pending JPS5235581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50111420A JPS5235581A (en) 1975-09-12 1975-09-12 Manufacturing process of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50111420A JPS5235581A (en) 1975-09-12 1975-09-12 Manufacturing process of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5235581A true JPS5235581A (en) 1977-03-18

Family

ID=14560712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50111420A Pending JPS5235581A (en) 1975-09-12 1975-09-12 Manufacturing process of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5235581A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5686352A (en) * 1993-07-26 1997-11-11 Motorola Inc. Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5686352A (en) * 1993-07-26 1997-11-11 Motorola Inc. Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff

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