JPS596574A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS596574A JPS596574A JP57115777A JP11577782A JPS596574A JP S596574 A JPS596574 A JP S596574A JP 57115777 A JP57115777 A JP 57115777A JP 11577782 A JP11577782 A JP 11577782A JP S596574 A JPS596574 A JP S596574A
- Authority
- JP
- Japan
- Prior art keywords
- base region
- insulating film
- semiconductor device
- forming
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、低不純物濃度のベース領域をもつトランジス
タの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a transistor having a base region with a low impurity concentration.
Ｉ Ｃｆハ、ｎ ｐ ｎ ）ランシスタとして、一般に
第１図に示す断面構造のトランジスタが用いられている
。第１図において、１はｐ型半導体基板、２はＮ＋型埋
込コレクタ領域、３はＮ−型エピタキシャル層、４はｐ
＋型分離層、６はｎ＋型コレクタコンタクト領域、６は
ｐ型ベース領域、７はｎ＋ 型エミッタ領域、８は保護
被膜、９は電極である。I Cf, n p n ) A transistor having the cross-sectional structure shown in FIG. 1 is generally used as a transistor. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is an N+ type buried collector region, 3 is an N- type epitaxial layer, and 4 is a p-type semiconductor substrate.
6 is an n+ type collector contact region, 6 is a p type base region, 7 is an n+ type emitter region, 8 is a protective film, and 9 is an electrode.
一般に、トランジスタの低雑音化を図るためには、外部
ベース抵抗を低くすることが必要である。Generally, in order to reduce the noise of a transistor, it is necessary to reduce the external base resistance.
しかし、第１図のようなｎｐｎ ）ランシスタにおいて
は、外部ベース抵抗を低くするために、ベース領域の不
純物濃度を上げると、エミ・ツク注入効率が悪くなり、
ｈ、、が低下する。この特性を改善したものとして、グ
ラフト・ベース構造があるが、グラフト・ベース構造に
すると、通常の方法では、マスク数および工程数が増加
し、チップコストの高騰、特性のバラツキが大きくなる
等の問題がある。However, in an npn (npn) transistor as shown in FIG. 1, when the impurity concentration in the base region is increased in order to lower the external base resistance, the emitter implantation efficiency deteriorates.
h, decreases. There is a graft-based structure that improves this characteristic, but when using a graft-based structure, the number of masks and steps increases, resulting in a sharp increase in chip cost and large variations in characteristics. There's a problem.
本発明は、かかる問題点に鑑み、マスク数を増やさずし
て、グラフト・ベーストランジスタと同様の構造を実現
し、素子の低雑音化を図る、半導体装置の製造方法を提
供せんとするものである。In view of these problems, the present invention aims to provide a method for manufacturing a semiconductor device that achieves a structure similar to that of a graft-based transistor without increasing the number of masks, and reduces device noise. be.
すなわち、本発明の方法は、コレクタ領域上の第１の絶
縁膜に、ベース領域開口のだめの開口部を設けた後、こ
の開口部に一導電型不純物を蒸着し、その後、前記ベー
ス領域開口部上に第２の絶縁膜を形成し、活性ベース領
域上の前記絶縁膜を選択的にエッチ除去した後、酸化雰
囲気中で拡散処理することを特徴とする。That is, in the method of the present invention, an opening for the base region opening is provided in the first insulating film on the collector region, an impurity of one conductivity type is vapor-deposited in this opening, and then the base region opening is A second insulating film is formed thereon, the insulating film on the active base region is selectively etched away, and then a diffusion treatment is performed in an oxidizing atmosphere.
以下、本発明の実施例について、図面を用いて詳述する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明により製作されるｎｐｎ ？ランシスタ
の一実施例を示す断面図である。第２図において、第１
図と同一部分または相当部分には、同一符号をけしてお
り、１０は拡散によるＰ＋型べ第３図は、本発明の一実
施例の製造工程を説明するものである。まず、ｎ型エピ
タキシャ）し層３上に、通常の熱酸化法により、酸化膜
８を形成した後、上記酸化膜８を選択的にエッチ除去し
、ｎｐｎ Ｉ−ランシスタのベース領域を開口スル。そ
の後、Ｐ型不純物源、例えばボロン層６′を上記ベース
領域開口部に蒸着する（第３図ａ）。FIG. 2 shows an NPN? manufactured according to the present invention. FIG. 2 is a sectional view showing an example of a run sister. In Figure 2, the first
Components that are the same as or corresponding to those in the figures are designated by the same reference numerals, and 10 is a P+ type formed by diffusion. FIG. 3 illustrates the manufacturing process of an embodiment of the present invention. First, an oxide film 8 is formed on the n-type epitaxial layer 3 by a normal thermal oxidation method, and then the oxide film 8 is selectively removed by etching to open the base region of the npn I-transistor. Thereafter, a P-type impurity source, for example a boron layer 6', is deposited in the base region opening (FIG. 3a).
次に、第２絶縁膜１１、たとえばｃｖｎ法による５ｉｏ
ｚ膜３０００人を上記ベース領域上に形成した後、活性
ベース領域を形成すべき部分上の上記Ｓｉ０２ 膜をエ
ミッタ形成用マスクを用い選択的にエッチ除去する（第
３図ｂ）。この第２絶縁膜１１は、窒化硅素（５ｉｓＮ
ａ ） 、多結晶シリコン。Next, the second insulating film 11 is formed by, for example, a 5io film by the CVN method.
After forming 3,000 layers of the Z film on the base region, the Si02 film on the portion where the active base region is to be formed is selectively etched away using an emitter forming mask (FIG. 3b). This second insulating film 11 is made of silicon nitride (5isN
a) Polycrystalline silicon.
あるいは基板シリコンの熱酸化膜も実用できる。Alternatively, a thermally oxidized film on the silicon substrate can also be used.
この後、酸化雰囲気中で、上記ボロンを拡散する。この
時、活性ベース領域６のシート抵抗は、不純物のボロン
が拡散中に形成される熱酸化膜に吸収され、外部ベース
領域１００シー１抵抗より高くなる。たとえば、ｒ型外
部ベース領域１０のシート抵抗１００Ω、活性ベース領
域６のシート抵抗２００Ωである（第３図Ｃ）。Thereafter, the boron is diffused in an oxidizing atmosphere. At this time, the sheet resistance of the active base region 6 becomes higher than the sheet resistance of the external base region 100 because impurity boron is absorbed by the thermal oxide film formed during the diffusion. For example, the sheet resistance of the r-type extrinsic base region 10 is 100Ω, and the sheet resistance of the active base region 6 is 200Ω (FIG. 3C).
再ひ、エミッタ形成用マスクを用いて、Ｃ工程で生成さ
れだ熱酸化膜を写真食刻技術により、エミッタ領域を開
口し、通常の拡散法により、リンを蒸着、拡散しエミッ
タ領域７の形成を行う。このエミッタ領域７の不純物濃
度は、たとえば、シート抵抗１０Ω程度を管理基準とし
て行なわれるものである。最後に、写真食刻技術を用い
て、エミッタ、ベース、コレクタの各コンタクト部を開
口し、周知の方法で電極９を形成する（第３図ｄ）ここ
で、９Ｌ、９ｂ、９０はトランジスタのエミッタ電極、
ベース電極およびコレクタ型部である。Once again, using the emitter formation mask, the emitter region is opened by photolithography in the thermal oxide film generated in step C, and phosphorus is evaporated and diffused by the usual diffusion method to form the emitter region 7. I do. The impurity concentration of the emitter region 7 is controlled using, for example, a sheet resistance of about 10Ω. Finally, each contact portion of the emitter, base, and collector is opened using photolithography, and the electrode 9 is formed by a well-known method (Fig. 3d).Here, 9L, 9b, and 90 are transistors. emitter electrode,
These are the base electrode and the collector mold part.
以上述べた、本発明の方法によれば、マスク数を増加す
ることなく、グラフト・ベース構造が実現出来、トラン
ジスタの低雑音化を図れる。またチップコストの低減、
特性のバラツキの減少等の利点ヲ持ち、トランジスタの
高性能化に大きく寄与するものである。According to the method of the present invention described above, a graft-based structure can be realized without increasing the number of masks, and the noise of the transistor can be reduced. In addition, chip cost reduction,
It has advantages such as reduced variation in characteristics, and greatly contributes to improving the performance of transistors.
第１図は従来のｎｐｎ）ランシスタの一例を示す断面図
、第２図は本発明の一実施例を示す断面図、第３図ａ
−ｄは本発明の一実施例による製造工程を示す断面図で
ある。
１・・・・・・Ｐ型半導体基板、３・・・・・・ｎ−型
エピクキシャル層、２・・・・・・埋込コレクク領域、
６・・・・・・カレクタコンタクト層、６．１０・・・
・・・ベース領域、７・・・・・・エミッタ領域、８・
・・・・・酸化膜、９・・・・・・電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
１
第３図Fig. 1 is a sectional view showing an example of a conventional npn) run transistor, Fig. 2 is a sectional view showing an embodiment of the present invention, and Fig. 3 a.
-d is a sectional view showing a manufacturing process according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 3... N-type epitaxial layer, 2... Buried collector region,
6... Calector contact layer, 6.10...
... base region, 7 ... emitter region, 8.
... Oxide film, 9 ... Electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 1 Figure 3
Claims (3)
領域上の第１の絶縁膜に、ベース領域開口部を設ける工
程と、前記ベース領域開口部に反対導電型不純物層を形
成した後、前記ベース領域開口部上に、第２の絶縁膜を
形成する工程と、前記第２の絶縁膜を選択的に除去した
後、酸化雰囲気中で拡散処理してベース領域を形成する
工程とをそなえだことを特徴とする半導体装置の製造方
法。(1) After forming a base region opening in a first insulating film on a − conductivity type collector region provided on the main surface of a semiconductor substrate, and forming an opposite conductivity type impurity layer in the base region opening; , a step of forming a second insulating film over the base region opening; and a step of selectively removing the second insulating film and then performing a diffusion treatment in an oxidizing atmosphere to form a base region. A method for manufacturing a semiconductor device characterized by the following features:
晶シリコン、熱酸化膜、ｃｖＤによる酸化膜等から選ば
れてなることを特徴とする特許請求の範囲第１項に記載
の半導体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the second insulating film is selected from silicon nitride (5isNa), polycrystalline silicon, a thermal oxide film, a CVD oxide film, etc. manufacturing method.
領域形成用のマスクパターンを用いることを特徴とする
特許請求の範囲第１項に記載の半導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein a mask pattern for forming an emitter region is used when selectively removing the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115777A JPS596574A (en) | 1982-07-02 | 1982-07-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115777A JPS596574A (en) | 1982-07-02 | 1982-07-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596574A true JPS596574A (en) | 1984-01-13 |
Family
ID=14670791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57115777A Pending JPS596574A (en) | 1982-07-02 | 1982-07-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596574A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01194824A (en) * | 1988-01-27 | 1989-08-04 | Sanyo Denki Co Ltd | Ac power source equipment |
| WO2001006551A1 (en) * | 1999-07-20 | 2001-01-25 | Infineon Technologies Ag | Method for producing two differently doped adjacent regions in an integrated semiconductor |
-
1982
- 1982-07-02 JP JP57115777A patent/JPS596574A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01194824A (en) * | 1988-01-27 | 1989-08-04 | Sanyo Denki Co Ltd | Ac power source equipment |
| WO2001006551A1 (en) * | 1999-07-20 | 2001-01-25 | Infineon Technologies Ag | Method for producing two differently doped adjacent regions in an integrated semiconductor |
| US6716712B2 (en) | 1999-07-20 | 2004-04-06 | Infineon Technologies Ag | Process for producing two differently doped adjacent regions in an integrated semiconductor |
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