JPS5897171A - Editing point detection circuit for electronic edition - Google Patents

Abstract

PURPOSE:To detect the editing point and to simplify the circuit, by converting an address of an RAM for PCM signals at reproduction into a code. CONSTITUTION:In the process reading out and reproducing a PCM signal written in an RAM4, an RAM wire start address and editing point address formed based on a designated reproduction speed for the detection of an editing point are converted at address information obtained from a recording medium by using a circuit 18. This conversion circuit 18 calculates an address code at the designated editing point at reproduction and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an edit point detection circuit, and more particularly to an edit point detection circuit when electronically editing a recording medium recorded using a PCM signal.

2. Description of the Related Art As information recording and reproducing devices such as VTRs become widespread, it often becomes necessary to edit information recorded on a recording medium. For such requests,
2. Description of the Related Art Devices have been developed that have an electronic editing function that performs editing processing based on a time code recorded in advance on a recording medium.

FIG. 1 shows a conventionally developed electronic editing device.

In the figure, a PCM signal input terminal 1 is supplied with a PCM signal read from a recording medium, such as a VTR tape. The input PCM signal is provided to a compression circuit 3 via an input buffer 2.

This compression circuit 3 is designed to compress the amount of data, because if the PCM signal applied to the input terminal 1 is stored as it is in a random access memory (RAM), which will be described later, it would require a very large memory capacity, which is undesirable. It is set in. The compressed PGM data is written to the PCM signal storage RAM 4. Regarding the continuous generation side of RAM4,
The contents of the RAM 4 are read out based on commands from the address control circuit 8 at a speed commensurate with the playback speed designation input, which will be described later.The read PCM signal passes through the expansion circuit 5, and is expanded in accordance with the compression. applied, selector 6
The signal is then output from the PCM output terminal 7. The selector 6 receives the PCM signal from the recording medium applied to the input terminal 1 as it is to one terminal, and outputs the PCM signal to the RAM 4.
One of the PCM signals read out is selected and output to the output terminal.

On the other hand, the address code recorded on the recording medium together with the PCM signal is input from the address code input terminal 12 via the input buffer 7 to 13 to the address code RAM 14 provided separately from the RAM 4. .

The PCM signals and address signals stored in the PCM signal RAM 4 and the address code RAM 14 as described above are read from the RAM 4 at a specified playback speed.
In order to read and reproduce the signal, the following fi control circuit is provided. That is, a playback speed designation signal designated by the rotary dial or operation switch is inputted from the playback speed designation terminal 11, and a clock signal corresponding to the playback speed is generated by the clock generation circuit 1o.

The formed clock signal is input to the address generation circuit 9, which generates address information based on the clock signal and outputs it to the address control circuit 8.

Here, since the PCM signal stored in the RAM 4 and the address code have different recorded frequencies, the address control circuit 8 performs address conversion processing. The converted address signal is applied to the PCM signal RAM 4 and the address code RAM 14, and reading of the PCM signal is executed. The read PCM signal is processed by the expansion circuit 5 as described above, and then outputted from the output terminal 7.
This becomes a signal for driving speakers, etc. At this time,
By determining the edit point while listening to the reproduced sound that is successively output from the PCM signal RAM 4, the edit point designation time converted via the address control circuit 8 is determined based on the signal input to the edit point designation terminal 16. The edit point is detected by reading the address code from the address code RAM 14 and reporting it as edit point address information by a suitable display means.

The conventional edit point detection circuit performs the above-mentioned <PCM signal
When writing to AM, the address code recorded on the recording medium together with the PCM signal is also written in the address code RAM 14 in association with the PCM signal. Therefore, when reproducing the contents of the PCM signal RAM 4 and determining an edit point, it is possible to immediately associate the PCM signal with the address code, but on the other hand, a large capacity memory is required to store the address code. Also, a memory IIJI! like the address control circuit 8! The disadvantage is that the single circuit becomes complicated.

Therefore, the main object of the present invention is to be able to detect edit points by using a conversion circuit with a simple circuit configuration, without providing a memory for storing address codes as required by conventional circuits. An object of the present invention is to provide such an editing point detection circuit.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

To summarize the invention, in the process of reading and reproducing a PCM signal written in the RAM, a RAM is formed based on a specified reproduction speed in order to detect an editing point.
1! A circuit is provided to convert the input start address and edit point address using address information obtained from the recording medium, and this conversion circuit calculates and outputs the address code at the specified edit point during playback operation. be.

FIG. 2 is a book diagram of one embodiment of the present invention. In the figure, the PCM signal applied to input terminal 1 is input to the input buffer? 2 and compression circuit 3 to RAM 4,
Furthermore, the system of the PCM signal read out from the RAM 4 and led out to the output terminal 7 via the PCMM signal expansion circuit 5 and the selector 6 is constructed in the same manner as in the conventional system shown in the first leap.

In this embodiment, in response to a playback speed designation input given to the playback speed designation terminal 1°1, a clock of a frequency commensurate with the playback speed designation input is generated by the clock generation circuit 10, and is given to the address generation circuit 9. to form an address signal,
Controls the read operation of RAM4. The address generation circuit 9 is inputted with signals given to the PCM signal RAM write start designation terminal 15 and the m dye point designation terminal 16, and the RAM write start signal or edit signal is input to each designation terminal 15 and 16. When the point designation signal is applied, the address at that time is transferred to the address reading circuit 17.

The address reading circuit 17 latches the input address information and transfers it to the edit point correction circuit 18.

On the other hand, the address code recorded on the recording medium together with the PCM signal is applied to the input terminal 12, and is applied to the address code reading circuit 19 through the input buffer 13 to form an address code signal. This address code reading circuit 19 includes the RAM write start designation terminal 1.
5 is applied, the address code of the recording medium at the start of RAM writing is detected, and the edit point correction circuit 1
8 as the address code. Therefore, the edit point correction circuit 18 is given RAM write start address information and edit point designation address information based on the above-described specified playback speed from the address reading circuit 17, and the address code reading circuit 19 provides the address information on the recording medium. A RAM write start address code read from is given. The edit point correction circuit 18 calculates the memory address difference from these input address information, converts it into an address code, calculates the address code at the edit point, and calculates the corrected address of the edit point corresponding to the playback speed. Output the code. The outputted edit point address code is appropriately given to a display means or the like and notified as the detection of an edit point.

In the above-mentioned embodiment, a case has been described in which the edit point correction is calculated based on the playback speed by calculation from the input address information, but the correction is not limited to this, and the correction can also be calculated by program processing using the CPU. .

As described above, according to the present invention, in a device for electronically editing a PCM signal, by providing a circuit that converts the address of a PCM signal RAM during playback into an address code, editing can be performed using a simple calculation circuit. RA for address code can be detected like the conventional device.
There is no need to provide M. Accordingly, the memory control circuit for the address code RAM becomes unnecessary, and the circuit of the electronic editing device can be simplified, making it highly economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional electronic editing device. FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 1 is a PCM signal input terminal, 4 is a PCM signal RAM, 7 is a PCM signal output terminal, 9 is an address generation circuit, 11 is a playback speed specification terminal, 12 is an address code input terminal, and 15 is a PCM signal RAM Write start designation terminal, 16 is edit point designation terminal, 17 is address reading circuit, 1
Reference numeral 8 indicates an editing point correction circuit, and reference numeral 19 indicates an address code reading circuit. Agent Shin Kuzuno - (1 other person)

Claims (1)

[Scope of Claims] Storage means for storing PCM signals, writing means for reading PCM signals from a recording medium and writing them into the storage means, and writing the PCM signals stored in the storage means at an arbitrary speed. a reading means for reading and reproducing the PCM signal, and converting the addresses of the start and stop of writing of the PCM signal to the storage means and the edit point into an address signal corresponding to the playback speed to form an edit point detection signal. An edit point detection circuit for electronic editing, comprising address control means.