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JPS5887829A - Polishing of si wafer - Google Patents

Polishing of si wafer

Info

Publication number
JPS5887829A
JPS5887829A JP18639581A JP18639581A JPS5887829A JP S5887829 A JPS5887829 A JP S5887829A JP 18639581 A JP18639581 A JP 18639581A JP 18639581 A JP18639581 A JP 18639581A JP S5887829 A JPS5887829 A JP S5887829A
Authority
JP
Japan
Prior art keywords
wafer
polishing
choline
pulverized powder
fine powder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18639581A
Other languages
Japanese (ja)
Inventor
Shinichiro Takasu
高須 新一郎
Hachiro Hiratsuka
平塚 八郎
Hisashi Muraoka
久志 村岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP18639581A priority Critical patent/JPS5887829A/en
Publication of JPS5887829A publication Critical patent/JPS5887829A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To prevent contamination of the Si wafer to be generated by metals of Na, Cu, etc., by a method wherein the Si wafer is polished using a polishing agent such as choline aqueous solution added with pulverized powder of amorphous SiO2, etc. CONSTITUTION:The chemical agent containing no metal element of Na, Cu, etc., having the faculty to etch the proper quantity of Si, having the property not to etch a polishing device constituting structural material, and moreover not to dissolve pulverized powder of amorphous SiO2, etc., to be added, is used as the polishing material for mirror polish finishing of the Si wafer. Namely, when the Si wafer is to be mirror polish finished, the polishing agent such as choline aqueous solution added with pulverized powder consisting of amorphous SiO2 is used. Concentration of choline of the polishing agent mentioned above is set to 0.2-10[%], and the adding quantity of pulverized powder is set to 200[g/ l]or less.

Description

【発明の詳細な説明】 本発明は、Slウェーハ製造プロセスにおけるSiウェ
ーハの研摩方法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for polishing a Si wafer in a process for producing a Si wafer.

従来、Slウェーハは第1図に示すようなプロセスで製
造されている。すなわち、チヨクラスキー法(cz法)
や70−ティングゾーン法(FZ法)で形成されたSl
のインゴットの外径を研削によシ愁え(工程1)、さら
にインゴット側面に決められた方位と幅を持つr’li
+ (オリエンテーションフラット)が現われるようイ
ンゴット側面を研削(工程2)する。次いで、インコゞ
ットを蝕刻(工程3)したのち、適当な厚さにスライシ
ング(工程4)してウェーハ素材を得る。
Conventionally, Sl wafers have been manufactured by a process as shown in FIG. That is, the Czyoklasky method (cz method)
Sl formed by the 70-ting zone method (FZ method)
The outer diameter of the ingot is ground by grinding (process 1), and the r'li with a predetermined orientation and width is further added to the side surface of the ingot.
Grind the side surface of the ingot so that + (orientation flat) appears (Step 2). Next, the ingot is etched (step 3) and then sliced to an appropriate thickness (step 4) to obtain a wafer material.

このウェーハ累月の表面を洗浄(工程5)したのち、そ
の両面をラッピング(工程6)する。
After cleaning the surface of this wafer (step 5), both surfaces thereof are lapped (step 6).

次に、ウェーハ素材のエツジを丸く削り(工程7)、続
いてウェーハ素拐を蝕刻(工程8)する。次に、ウェー
ハ累月の表rh*をボ゛リジング(工程9,10)した
のち、該表面を洗浄(工程11)してSlウェーハが製
造される。かくして製造されたSiウェーハは所定の検
査がなされたのち出荷(工程12)されることになる。
Next, the edges of the wafer material are rounded (step 7), and then the wafer material is etched (step 8). Next, after boring the surface rh* of the wafer (steps 9 and 10), the surface is cleaned (step 11) to produce an Sl wafer. The Si wafer thus manufactured is subjected to a predetermined inspection and then shipped (step 12).

ところが、このようなSlウェーハの製造プロセスにあ
っては、上記工程9.]0において次のような問題があ
った。すなわち、工程9゜10においては、通常Naを
含有する無機アルカリと非晶質SiO2微粉末との混合
物をボリシング材として用い、ウェハ素材表面のポリシ
ングが行われる。その際、工程9および工程10では異
った量比で無機アルカリと非晶質S iO2が混合され
る。丑だ、工程9では無機アルカリと非晶質5IO2と
を用いてボリンングし、工程IOではCuイオン全使用
した蝕刻を主とする仕上げを行う場合もある。いずれの
場合にあっても、半導体素子製作プロセスで最も低レベ
ルに抑えるべきNa 、Cu ’ie含有するボリシン
グ剤を用いているので、工程11での洗浄は高度の技術
管理のもとに実行されなければならない。そして、この
洗浄が完全に行われない場合には、ウェーハ表面に残留
するNa 、 Cuによって製作された素子の特性が損
なわれることになる。特に、ウェーハ裏面に微細な機械
加工損傷を与えるような場合には、この機械加工損傷に
Na 、 Cu等が多量に残存し、工程11での洗浄で
もその除去が極めて困難であることが判明した。
However, in the manufacturing process of such a Sl wafer, the above step 9. ]0 had the following problem. That is, in steps 9 and 10, the surface of the wafer material is polished using a mixture of an inorganic alkali containing Na and amorphous SiO2 fine powder as a polishing material. At this time, in step 9 and step 10, inorganic alkali and amorphous SiO2 are mixed in different quantitative ratios. In some cases, in step 9, boring is performed using an inorganic alkali and amorphous 5IO2, and in step IO, finishing is performed mainly by etching using all Cu ions. In either case, the cleaning in step 11 is carried out under a high level of technical control, since a borishing agent containing Na and Cu'ie, which should be kept at the lowest level in the semiconductor device manufacturing process, is used. There must be. If this cleaning is not performed completely, the characteristics of the fabricated device will be impaired due to Na and Cu remaining on the wafer surface. In particular, when fine machining damage is caused to the backside of the wafer, it has been found that large amounts of Na, Cu, etc. remain in the machining damage, and it is extremely difficult to remove it even with cleaning in step 11. .

本発明は上記事情を考慮してなされたもので、その目的
とするところは、Slウェーハの製造プロセスにおいて
Siウェーハを研摩するに際し、NaやCu等による汚
染を未然に防lIユすることができ、Slデバイスの製
造歩留シ向上に寄与し得るSlウェーハの研摩方法を提
供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to prevent contamination by Na, Cu, etc. when polishing a Si wafer in the process of manufacturing an Sl wafer. An object of the present invention is to provide a method for polishing an Sl wafer that can contribute to improving the manufacturing yield of Sl devices.

ます、本発明の詳細な説明する。本発明の骨子は、Si
ウェーハを鏡面研厚仕」二げするためのポリシンダ材と
して、NaやCu叫の金h2元素を含有せず、Siを適
当量蝕刻する能力を持ち、ポリシング装置構成構造材を
腐蝕せず、かつ添加する非晶質S io 2等の微粉末
を俗解しない薬品を用いるようにしたことである。
Now, the present invention will be explained in detail. The gist of the present invention is that Si
As a polycinder material for mirror-polishing and polishing wafers, it does not contain any gold elements such as Na or Cu, has the ability to etch an appropriate amount of Si, does not corrode the structural materials of the polishing equipment, and The purpose is to use a chemical that is not commonly understood as a fine powder such as amorphous S io 2 to be added.

Stを蝕刻する浴液として汀、例えばHF +HNO,
混酸があるが、この混酸は金践構造材料を著しく浸す。
As a bath solution for etching St, for example, HF + HNO,
There is a mixed acid, but this mixed acid significantly soaks the metal structure materials.

このtcめ、混酸全使用する場合、ポリシング装置構成
構造材料として有機物材料、或いはアルミナ等の耐酸性
セラミクス材料を選ぶ必要がある。しかし汗から、現在
要求されるような極端に精密なウェーハ精度を確保する
ためには、上記構造材料として機械加工および精密加工
が容易な金属材料、例えばステンレススチールを用いな
ければならず、上記耐酸性の点で矛盾を生じた。
For this reason, when all mixed acids are used, it is necessary to select an organic material or an acid-resistant ceramic material such as alumina as the structural material for the polishing device. However, in order to ensure the extremely precise wafer precision currently required, metal materials that are easy to machine and precisely process, such as stainless steel, must be used as the structural material, and the acid-resistant There was a contradiction in terms of gender.

そこで本発明者等は有機強アルカリについて鋭意研究を
重ねた結果、コリン(Tri Methyl−2−Hy
droxyethyl Ammonium Hydro
xide :〔(CH3)6NCH2CH20H〕+0
H−)が優れた特性を示すことを見出した。すなわち、
コリンはボリシング装置構造材料として用いられるステ
ンレススチール、ガラスセラミクス、有機材料等を浸す
ことなく、安定して使用し得る。さらに、研摩に必要な
特性も極めて良好なものであった。
As a result of extensive research into strong organic alkalis, the present inventors discovered choline (Tri Methyl-2-Hy
Droxyethyl Ammonium Hydro
xide: [(CH3)6NCH2CH20H]+0
It has been found that H-) exhibits excellent properties. That is,
Choline can be used stably without soaking stainless steel, glass ceramics, organic materials, etc. used as structural materials of the borising device. Furthermore, the properties necessary for polishing were also extremely good.

本発明はこのような点に着目し、コリン水溶液に非晶質
S iO2等の微粉末を加えたポリシング剤を用いて、
St、ウェーハをポリシングするようにした方法である
。したがって、SiウェーハがNaやCu等の金属によ
って汚染されることを未納に防止でき、前記した目的全
達成することができる。
The present invention focuses on these points, and uses a polishing agent in which fine powder such as amorphous SiO2 is added to an aqueous choline solution.
St. This is a method for polishing a wafer. Therefore, undue contamination of the Si wafer with metals such as Na and Cu can be prevented, and all of the above objectives can be achieved.

以下、本発明の詳細を図面を参照して説明する。Hereinafter, details of the present invention will be explained with reference to the drawings.

第2図は有機強アルカリとしてのコリン、TMAH(T
etra Methyl Ammonium Hydr
oxide :〔(CH6)4N′3+OH〕およびT
MA (Trl Methyl Am1ne:[CH3
]5N )の水浴液濃度と1111との関係を示す特性
図である。ここで、図中実線Aはコリン、BはTMA 
、 Cは’IMAHの特性を示している。この図から同
じPHヲ得るためには、コリンの濃度はTMAの約l/
10の濃度でよく、TMA■■の約25倍の濃度で十分
であることが判る。
Figure 2 shows choline and TMAH (T) as strong organic alkalis.
etra Methyl Ammonium Hydro
oxide: [(CH6)4N'3+OH] and T
MA (Trl Methyl Am1ne:[CH3
]5N) is a characteristic diagram showing the relationship between the water bath solution concentration and 1111. Here, the solid line A in the figure is choline, and the solid line B is TMA.
, C indicates the characteristics of 'IMAH. From this figure, to obtain the same pH, the concentration of choline should be approximately 1/1 of TMA.
It can be seen that a concentration of about 25 times that of TMA is sufficient.

Siウェーハをポリシングするに際しては、使用ポリシ
ング材料中の不純物に起因するウェーハ表面汚染の問題
がある。このため、TMAH。
When polishing Si wafers, there is a problem of wafer surface contamination due to impurities in the polishing material used. For this reason, TMAH.

TMAおよびコリンの純度レベルを低価格で高度化し得
ることか必要条件となる。本発明者等は、現在入手し得
る上記3者の5〔%〕水浴液の純度レベルについて、現
在最も信頼し得るフレームレス原子吸光分析法を用い、
松数回にわたって分析を行った。その結果、TMAI−
(およびTMAでは重金属例えばNa 、 Fe 、 
Zn 、 Agが20〜50[ppb〕検出されたのに
対し、コリンはいずれも1〜5 [ppb)以下であっ
た。すなわち、コリンはその使用に際し純度的に極めて
安定に使用し得ることが判明した。また、NaOHy 
KOHPNa CO3或いはC2N205Ct2Na 
f含有する薬剤よりもNaの汚染が少ないことは明らか
である。さらに、Cu(NO3)2を使用するエツチン
グに比較し、Cuの汚染が起こらないと云う特長がある
のも明らかである。
It is a prerequisite that the purity level of TMA and choline can be improved at low cost. The present inventors used flameless atomic absorption spectrometry, which is currently the most reliable method, to determine the purity level of the currently available 5% water bath liquids of the above three types.
Matsu was analyzed several times. As a result, TMAI-
(and in TMA heavy metals such as Na, Fe,
Zn and Ag were detected at 20 to 50 [ppb], whereas choline was detected at 1 to 5 [ppb] or less. That is, it has been found that choline can be used with extremely stable purity. Also, NaOHy
KOHPNa CO3 or C2N205Ct2Na
It is clear that Na contamination is less than f-containing drugs. Furthermore, compared to etching using Cu(NO3)2, it is clear that it has the advantage of not causing Cu contamination.

次に、コリンのSLに対する蝕刻速度について説明する
。コリンおよびNaOH(1) Siに対する各蝕刻速
度は次の第1表に示す通υである。
Next, the etching speed of choline with respect to SL will be explained. The etching speeds for choline and NaOH(1)Si are shown in Table 1 below.

第   1   表 コリンのStに対する蝕刻速度は、NaOHに比較しN
型、P型いずれとも大きく、かつその差は少ない。した
がって、現在MOS型LSIに使用される(100)S
iウェハに対しコリンが極めて有用である。−ま/ζ、
ポリシング中にはStラウェ−表面温度が上昇するため
、蝕刻速度の温度に対する安定性が必要である。第3図
はコリン浴液に表面活性剤(商品名NCW(iolA 
) l [%〕を添加した液に対し、蝕刻速度の温度依
存性を示す特性図である。ここで、図中曲ffMCは1
.5[wt%]。
Table 1 The etching rate of choline for St is compared to NaOH.
Both type and P type are large, and the difference between them is small. Therefore, the (100) S
Choline is extremely useful for i-wafers. -Ma/ζ,
During polishing, the temperature of the St substrate surface increases, so the etching rate must be stable with respect to temperature. Figure 3 shows a surfactant (trade name: NCW (iolA) added to the choline bath solution.
FIG. 2 is a characteristic diagram showing the temperature dependence of the etching rate for a solution to which 1% of the etching rate is added. Here, the song ffMC in the figure is 1
.. 5 [wt%].

Dは0.3[wt%〕のコリン浴液を示している。この
図から明らかなように55〜60〔℃〕以上の温度にお
いて、15〔wt%〕のコリン浴液を用いたものは略一
定の蝕刻法1屁をイ」することが判明した。−まだ、各
種1度のコリン溶液に対する蝕刻速度は第4図に示す如
くなり、蝕刻速度に温度依存性があることが明らかとな
った。このため、温度および溶液濃度を変更することに
より、蝕刻速度を容易に)ilAJ整+−、イaると云
う特長がある。lた、コリンは極めて水に浴解し易いた
めに、純水にて洗浄することにより容易に取り除くこと
ができる。
D indicates a 0.3 [wt%] choline bath solution. As is clear from this figure, it was found that at a temperature of 55 to 60 [°C] or higher, the etching process using a 15 [wt%] choline bath solution was approximately constant. -The etching rates for each type of 1 degree choline solution were as shown in FIG. 4, and it became clear that the etching rates were temperature dependent. Therefore, by changing the temperature and solution concentration, the etching speed can be easily adjusted. Furthermore, since choline is extremely easily dissolved in water, it can be easily removed by washing with pure water.

さて、実際のウェーハ鏡面研摩に際しては、コリンと微
粉末とを次のように混合してスラリーとなし使用する。
Now, in actual wafer mirror polishing, choline and fine powder are mixed as follows to form a slurry and used.

すなわち、第1段階鏡面研摩工程用スラリーとしては下
記第2表に示す成分例1のものを、第2段階鏡面研摩工
程用スラリーとしては成分例2,3のものを用いる。
That is, as the slurry for the first stage mirror polishing process, the composition of Example 1 shown in Table 2 below is used, and as the slurry for the second stage mirror polishing process, composition examples 2 and 3 are used.

第    2   表 上記した配合は、鏡面研摩にあたって使用する装置、研
摩・母ツド、圧力、温度、研摩パッド・ウェーハ相対速
度およびスラリー供給速度等によって最適値に選定保持
される必要がある。したがって、上記配合例はこれに限
定されるものではない。しかしながら、一般的には第1
段階において非晶質5IO2微粉末の童Fiやや多く、
第2段階である仕上げ工程においては非晶質8102微
粉末の量は少なく、或いは全く使用しなくてもよい。
Table 2 The above formulations need to be selected and maintained at optimal values depending on the equipment used for mirror polishing, the polishing base, pressure, temperature, relative speed of the polishing pad and wafer, slurry supply speed, etc. Therefore, the above formulation example is not limited to this. However, generally the first
At the stage, there is a little more amorphous 5IO2 fine powder,
In the finishing step, which is the second stage, the amount of amorphous 8102 fine powder may be small or may not be used at all.

成分例1および成分例2のスラリーヲ用いて両面鏡面研
摩装置により鏡面仕上はを行った。
Using the slurries of Component Example 1 and Component Example 2, mirror finishing was performed using a double-sided mirror polishing device.

26枚の100[mφ]Siウェーハラッピング後30
〔後爪0エツチングしたウェーハに対し、第1段階鏡面
研摩工程で約20分、第2段階鏡面研摩工程で約5分の
研摩を行った。このとき、第1段階での除去量は約25
〔μm〕、第2段階での除去ii: IJ二約3〔μm
〕であった。さらに、ウェーハの反りは3〔μm〕、平
f11度はEPDで13〔μm〕の平均値を得た。
30 after wrapping 26 100 [mφ] Si wafers
[The wafer that had been etched with no post-nails was polished for about 20 minutes in the first stage mirror polishing process and for about 5 minutes in the second stage mirror polishing process. At this time, the amount removed in the first stage is approximately 25
[μm], second stage removal ii: IJ2 approximately 3 [μm]
〕Met. Further, the average value of the wafer warpage was 3 [μm], and the flat f11 degree was 13 [μm] by EPD.

一方、片面鏡面研摩装置全使用した例では、第1段階で
の除去量は約15〔μm〕、第2段階での除去量は約2
〔μm〕であった。除去量(片面についての除去量)が
両面鏡面研摩装置を使用した例より多いのは、研摩圧が
前者に対し約5倍と高かったためと考えらねる。ウェハ
の反りは45〔μm〕、平坦度はEPDで20〔μm〕
の平均値金示した。
On the other hand, in an example in which the entire single-sided mirror polishing device is used, the amount removed in the first stage is approximately 15 [μm], and the amount removed in the second stage is approximately 2 μm.
[μm]. The reason why the amount removed (the amount removed for one side) was greater than in the example using a double-sided mirror polishing device is probably because the polishing pressure was about 5 times higher than in the former case. Wafer warpage is 45 [μm], flatness is 20 [μm] by EPD
The average value of gold indicated.

上記2つの例で得たStウエーノ・を洗浄処理したとこ
ろ、いずれの場合にあってもイオンビームマスクアナラ
イザを用いてもウェー71表面のNa残存を検出するこ
とはできなかった。すなわち、81ウエー・・研摩工程
におけるNa等の汚染を防止することができた。
When the St wafers obtained in the two examples above were cleaned, it was not possible to detect Na remaining on the surface of the wafer 71 in either case even using an ion beam mask analyzer. That is, 81-way...contamination with Na, etc. during the polishing process could be prevented.

なお、上述した説明ではコリン水溶液に混合するものと
して非晶質S i O2微粉末を用いたが、この代υに
はNaやCu等の金属元素を含まず、コリン水溶液に溶
解しない微粉末であれば用いてもよい。壕だ、コリン濃
度、微粉末添加量および温度等の条件は、仕様に応じて
適宜定めれはよい。さらに、前記表面活性剤は必すしも
使用しなくてもよい。1だ、研摩工程は必ずしも2段階
に分けて行う必要はなく、1回の工程で行うようにして
もよい。その他、本発明はその要旨を逸脱しない範囲で
、種々変形して実施することができる。
In the above explanation, amorphous SiO2 fine powder was used as the material to be mixed with the choline aqueous solution, but this substitute υ may be a fine powder that does not contain metal elements such as Na or Cu and does not dissolve in the choline aqueous solution. You may use it if you have it. Conditions such as temperature, choline concentration, amount of fine powder added, temperature, etc. may be determined as appropriate according to specifications. Furthermore, the surfactants may not necessarily be used. 1. The polishing process does not necessarily need to be performed in two stages, and may be performed in one process. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は一般的なS1ウエーノ・製造ノロセスを示す作
業工程図、第2図乃至第4図はそれぞれ本発明の詳細な
説明するためのもので第2図はコリン、TMAHオ、1
:ひTMA (7)水m液濃rm−とPtlとの関係を
示す特性図、第3図C:コリン水溶液の温度に対するS
tの蝕刻速度を示す特性図、第4図は温度をパラメータ
としたコリン水溶液の重量%に対するStの蝕刻速j此
を示す’l’!を作図である。 出願入代]j11人  弁理士 鈴 江 武 彦□上
Fig. 1 is a work process diagram showing a general S1 Ueno manufacturing process, and Figs. 2 to 4 are for explaining the present invention in detail, respectively.
: HTMA (7) Characteristic diagram showing the relationship between water concentration rm- and Ptl, Figure 3C: S vs. temperature of choline aqueous solution
A characteristic diagram showing the etching rate of t. Figure 4 shows the etching rate of St with respect to the weight percent of the choline aqueous solution with temperature as a parameter. is a drawing. Application fee] 11 patent attorneys Suzue Takehiko□Top

Claims (3)

【特許請求の範囲】[Claims] (1)  Siウェーハを鏡面研摩仕上げするに際し、
コリン水溶液に微粉末を加えたボリシング剤を用いるこ
とを特徴とするStウエーノ・の研摩方法。
(1) When mirror polishing a Si wafer,
A method for polishing St. ueno, which is characterized by using a borishing agent prepared by adding fine powder to an aqueous choline solution.
(2)  前記微粉末は、非晶質SiO2からなるもの
であること全特徴とする特許請求の範囲第1項記載のS
tラウェ−の研摩方法。
(2) The S according to claim 1, characterized in that the fine powder is made of amorphous SiO2.
How to polish t-lawe.
(3)前記ポリシング剤のコリン濃ii0.2〜10〔
%〕、微粉末添加量を2oo(g/、1以下に設定した
ことを特徴とする特許請求の範囲第1項記載のSiウェ
ーハの研摩方法。
(3) Choline concentration ii of the polishing agent 0.2 to 10 [
%], and the amount of fine powder added is set to 2oo (g/, 1 or less).
JP18639581A 1981-11-20 1981-11-20 Polishing of si wafer Pending JPS5887829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18639581A JPS5887829A (en) 1981-11-20 1981-11-20 Polishing of si wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18639581A JPS5887829A (en) 1981-11-20 1981-11-20 Polishing of si wafer

Publications (1)

Publication Number Publication Date
JPS5887829A true JPS5887829A (en) 1983-05-25

Family

ID=16187643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18639581A Pending JPS5887829A (en) 1981-11-20 1981-11-20 Polishing of si wafer

Country Status (1)

Country Link
JP (1) JPS5887829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10247202A1 (en) * 2002-10-10 2003-10-30 Wacker Siltronic Halbleitermat Production of a boron-doped silicon wafer comprises cutting a boron-doped silicon crystal into wafers, mechanically shaping, wet chemical etching, and polishing by continuously introducing a silicic acid-containing aqueous polishing agent

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10247202A1 (en) * 2002-10-10 2003-10-30 Wacker Siltronic Halbleitermat Production of a boron-doped silicon wafer comprises cutting a boron-doped silicon crystal into wafers, mechanically shaping, wet chemical etching, and polishing by continuously introducing a silicic acid-containing aqueous polishing agent

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