JPS5857778B2 - Random number initial value setting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a random number initial value setting method in an electronic device having a random number generation function.

In general, methods for generating random numbers are broadly classified into methods using calculations and methods using physical phenomena.

Among these methods, generally known methods for generating random numbers by calculation include the square taking method, the multiplication type congruential method, and the mixed congruential method.

In any of these methods using calculations, it is necessary to provide an initial value of a random number (numerical data other than "O") to an electronic device (for example, an electronic computer) that executes the calculation according to each of the above methods.

However, it is not preferable to always give the same initial value when calculating random numbers because random numbers with the same content will always be generated only in the same order.

For this reason, in the past, for example, a counter with a predetermined number of digits was specially provided, and when the random number calculation was started, the counter was allowed to perform a counting operation for an arbitrary period of time, and then the counted value of this counter was taken out to obtain the initial value of the random number. There is something I did.

However, this method requires a dedicated counter for setting the initial value of the random number, which has the disadvantage of complicating the circuit.

This invention was made in consideration of the above circumstances, and it is possible to obtain highly accurate random numbers with a simple circuit without providing a dedicated circuit for setting the initial value of the counter etc. as described above. This provides an initial value setting method for random numbers.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

This embodiment uses a refresh RAM (MO8 type dynamic RAM) for storing display data provided in the CRT display device of an electronic computer equipped with the CRT display device.
) and the address counter that addresses this refresh RAM take random values when the computer is powered on, so that the initial value of the random number is set.

FIG. 1 shows the overall configuration of the electronic computer.

In FIG. 1, a main memory 1 is provided with areas such as a system program area, a system working area, and a user's area.

Fixed programs for controlling the operations of the hardware of the computer, such as arithmetic processing, command reference tables, interrupt processing routines, and error processing routines, are incorporated in the system program area.

A program for controlling the initial value setting operation of random numbers according to this embodiment is also stored in this fixed program according to the flowchart of FIG. 2, which will be described later.

Further, the system working area is provided with a large number of general-purpose registers for storing data generated when the CPU 2 performs arithmetic processing according to the fixed program, and among them, the initial value of the random number is stored in the register WA. It will be remembered.

Furthermore, the user's area is an area for storing program data input by the user from a key input device (not shown) or the like.

The main memory 1 having each of the areas is address-controlled by address data and control signals sent from the CPU 2 via pass lines 9 and 10, and data writing and reading operations in each of the areas are executed. .

The data read from the main memory 1 is sent to the CPU 2 via the pass line 11, or
The data sent from U2 is written to the main memory 1 via the pass line 11.

CPU2 is an arithmetic processing circuit and an arithmetic control circuit.

It is made up of a group of registers including the time storage register TA, and executes arithmetic processing according to the program in the main memory 1.

The address data is outputted from the arithmetic processing circuit and outputted to the pass line 9, thereby addressing the main memory 1 or the pass line 12,
The signal is sent to the address counter 4 via the I10 port 3 and the pass line 14, and the contents of the address counter 4 are incremented.

Furthermore, the data etc. output from the arithmetic processing circuit are also
The data is sent to the refresh RAM 5 via the pass line 13, the I10 port 3, and the pass line 15, and the display data is stored in the refresh RAM 5.

Furthermore, an enable signal E is output from the arithmetic control circuit to the I10 port 3, and the operation of the I10 port is controlled by the output state of the enable signal E.

The refresh RAM 5 is addressed by the address counter 4 and stores display data sent from the I10 port 3, and this display data is sent to the character generator 7 via the pass line 16.
As a result, the corresponding data is displayed on the CRT display device 8.

The CRT display device 8 is of a raster scan type, and is therefore provided with a CRT counter 6° character generator 7.

The CRT counter 6 includes a dot counter, a character counter, a last column rank, and a line counter, and the contents of these counters are sent to the character generator 7 via a pass line 17.

Therefore, the character generator 7 generates a character corresponding to the display data sent from the refresh RAM 5 on the pass line 1 in accordance with the dots and rasters.
8 and sent to the CRT display device 8.

Further, from the CRT counter 6, a horizontal synchronizing signal H-8
A vertical synchronizing signal V-8 is output and sent to the CRT display device 8.

Further, a control signal output from the CRT counter 6 is sent to the address counter 4 via a pass line 19 to control the address data output operation.

Next, the flowchart shown in FIG. 2, and the address counter 4. shown in FIGS. 3 and 4. Refresh RAM5
The operation will be explained with reference to the storage state diagrams of registers TA and WA.

When the computer is powered on, the address counter 4
The contents of the refresh RAM 5 become random values, and the operation of step S1 shown in FIG. 2 is first executed.

That is, in step S1, an enable signal E for setting the I10 port 3 to read mode is output from the arithmetic control circuit in the CPU 2.

Note that when the power is turned on, the contents of the address counter 4 and the refresh RAM 5 are both random contents as described above, but to simplify the explanation, as shown in FIG. The content of is 1122J, and refresh RAM5
data r13'' at addresses 122 to 135, respectively.
It is assumed that rA5J, ---, r6Bj (in hexadecimal) are stored.

Following the operation in step S, the process proceeds to step S2, in which data for one character is read from the storage area of the refresh RAM 5 addressed by the contents of the address counter 4, and this data is stored in a temporary storage register in the CPU 2. An operation of forwarding to TA is performed.

When the power is turned on, the contents of address counter 4 are "
122J, data "13" at address 122 of the refresh RAM 5 is read out from the refresh RAM 5, as shown in FIG.

This data "13" is transmitted to pass line 16, I10 port 3. It is sent to the register TA in the CPU 2 via the pass line 13 and stored therein.

Next, the process proceeds to step S3, where the CPU 2 increments the content of the address counter 4, that is, increments it by "+1".

In this operation, the current value of address counter 4 is “122
J is sent to the arithmetic processing circuit in the CPU 2 and incremented by 1, and the resulting value 1'-123J is sent to the pass line 12.
, I10 port 3. It is sent again to the address counter 4 via the pass line 14 and stored therein.

Next, the process advances to step S4, where the refresh RAM 5 is first refreshed.
The CPU 2 performs a detection operation to determine whether the content of the data read from the temporary storage register TA and written to the temporary storage register TA is "0".

In this step S4, the content of the initial value of the random number to be obtained is "0".
This is to prevent this from happening.

In this step S4, since the data l-13J stored in the register TA is not rOJ, the process advances to the next step S5, and the operation of step S5 is started.

Note that when "O" is detected in step S4, the process advances to step S2, new data is read from the refresh RAM 5 according to the incremented contents of the address counter 4, and the process proceeds to step S3. S is executed.

In step S5, the first digit of the data read from the refresh RAM 5 is selected and transferred to the register WA in the main memory 1.

That is, 1 of the data "13" in register TA
The data “3” in the digit is stored in the register W for the initial value of the random number.
Transferred to A.

In this way, the data ``3'' is placed in the first digit of register WA.
is stored as shown in FIG. 4a.

Next, the process proceeds to step S6, where the CPU 2 performs a detection operation to determine whether data other than "0" has been stored up to a predetermined number of digits (in this example, 12 digits) in the register WA.

Since data up to the first digit is now stored, the process returns to step S2.

Then, in step S2, according to the current value "123J" of the address counter 4, 123J of the refresh RAM 5 is stored.
Data "A5" in address 3 is read out, sent to register TA, and stored.

In the next step S3, the current value r123J of the address counter 4 is incremented by 1 to become r124j, which is sent to the address counter 4 and stored.

Furthermore, step S4. S5. The operation in S6 is similarly executed and the process returns to step S2, whereupon the data reading operation of the refresh RAM 5 for the next data at address 124 is started.

Figure 4 shows the register TA after the second operation is completed.
, indicates the storage state of WA.

By the way, the data in the next 124th address of the refresh RAM 5 is "FO" as shown in FIG. 3, and particularly contains data "0" in the first digit.

In such a case, since this state is detected in step S4, the process immediately returns to step S2 from step S4, and as a result, data "0" is stored in the register WA.
Therefore, the initial value of the random number is prohibited from including data "0".

FIG. 4C shows the storage state of register WA in such a case.

The same operation as described above is continued while incrementing the contents of the address counter 4, and when 12 digits of data are stored in the register WA as shown in FIG. Since it is detected, the series of initial value setting operations described above are completed.

In this way, the initial value of the random number consisting of 12 digits is obtained,
Further, using this initial value, it becomes possible to perform arithmetic operations to obtain subsequent random numbers.

Further, in the case of this embodiment, the random contents of the refresh RAM used for storing display data of the CRT display device and the address counter that addresses this refresh RAM at power-on are used to generate the initial value of the random number described above. Although the setting operation is performed, the calculation time required for this setting operation is extremely short, and of course the C
CR
It does not prevent the display operation of the T display device.

In the above embodiment, it is detected in step S4 whether the value of the register TA is "O" or not, and one digit of the register TA is selected in step S5 to set the initial value.
The method is not limited to this, and any method can be used as long as the initial value does not become "0".

Further, in the above embodiment, the present invention was applied to an electronic computer, but it goes without saying that the present invention can also be applied to other electronic devices having a random number generation function and a refresh RAM. It is sufficient that it does not deviate from the range, and various applications and modifications are possible.

As described in detail above, according to the present invention, the contents of the refresh RAM used for data storage of the electronic device and the address counter that addresses this refresh RAM are both set to initial values when the power of the electronic device is turned on. By obtaining the initial value of the random number by taking advantage of the fact that it becomes a random value in the past, the desired initial value of the random number can be obtained immediately when the power is turned on, and it is also possible to provide a special circuit for this purpose. Since there is no such thing, the hardware configuration is simple.

Furthermore, by calling random contents according to random contents, extremely random values can be obtained, and therefore, there is an advantage that highly accurate initial values of random numbers can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is an overall circuit configuration diagram of an embodiment of the present invention, and FIG.
The figure is a flowchart for explaining the operation of the ipsilateral side.
The figure shows the address counter and refresh RA when the power is turned on.
The state diagram of M, FIG. 4, shows the address counter, refresh RAM, register TA, according to the flowchart of FIG.
It is a memory state diagram of WA.

Claims (1)

[Claims] 1. When an electronic device is powered on, a refresh RAM used for data storage of this electronic device is addressed by the address counter before initialization, and random data is sequentially read from the refresh RAM to obtain a numerical value of a predetermined number of digits. A random number initial value setting method characterized in that data is obtained and this numerical data can be used as an initial value for random number calculation.