JPS58222556A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an element structure with the CMOS process connected without sacrificing characteristic of bipolar element by commonly executing impurity doping for the emitter and forming polysilicon emitter on the emitter simultaneously with forming the polysilicon gate. CONSTITUTION:After forming a gate oxide film 13 for MOS element, an emitter window 14 is formed by photo etching and then a polysilicon layer 12 to be used for gate of MOS element is formed. Thereafter, the arsenic ion is implanted to the entire part and thermal processing is executed. Thereby resistance of polysilicon which will become a gate is lowered and simultaneously an emitter 9 is formed through the emitter window 14. With the photo resist used as the mask, the polysilicon layer 12 is etched and thereby a gate 12 and emitter polysilicon layer 19 of MOS element are formed. With SiO2 film used as the mask, boron ion is implanted for doping of the source/drain 8 of PMOS, while arsenic ion for doping of the source/drain 7 of NMOS. A semiconductor device can be formed through heat processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an element structure that increases the speed of a bipolar element and simplifies the manufacturing process in a composite LSI in which a biborder transistor and a MOS transistor are formed on the same substrate.

Bipolar transistor and complementary MO8) transistor (
LSIs (hereinafter referred to as BiCMO8LS, I) in which both P-channel and N-channel transistors (called CMOS transistors) were fabricated on the same substrate have already been attempted since 1969. One BicM reported so far
os LSI's MOS devices are manufactured using an AI gate process and have large processing dimensions (more than 5 μm), and are inferior in terms of integration and high-speed performance compared to LSIs using recent microfabrication technology (for example, minimum size 2 μm). ntcMos
The bipolar element included in LS i was similarly large in size, and could not be expected to have high integration or high-speed performance.

In recent years, due to advancements in self-core 2-in technology using silicon gates, microfabrication technology, etc., the gate length of MOSLSI has become mainstream from 3 μm to 2 μm. M like this
It has become necessary to simultaneously form fine bipolar elements in line with OS elements.

By analogy with the previously reported process for forming BiCMO8LSI, FIG. 1 shows a process for forming a bipolar element at the same time as a silicon gate MOS element. Each part of the 816MO8 element shown here will be explained in order of process.

On the surface of the P-type silicon substrate 1, N+ (high concentration N-type,
Buried layer 2 and P3 buried layer 4 for isolation
After forming, an N-type epitaxial layer 3 is formed. ,
After forming the P well region 5 in the region where NMO8 is to be formed, S
A selective oxide film 10 for isolation is formed using the i3N film as an oxidation mask.

Next, the entire base 6 of the bipolar element is formed, the gate oxide film 13 and the polysilicon core 12 for the gate are formed, and the polysilicon is photoetched and the 2M08 portion is photoetched, and the source and drain 8 of the PMO 8 are formed by self-line. Next, the sio film 11 as a diffusion mask is formed, and in order to simplify the printing process, an emitter diffusion window 14 and a source/drain diffusion window of NMO8 are simultaneously formed, and then an N-type impurity is doped. emitter 9,
A source/drain 7 is formed. After this, Figure 1(b)
As shown in FIG. 3, a passivation film 15 is formed, and contact windows for connecting electrodes to all elements are formed. The contact windows are emitter 16, base 16', and NM, respectively.
O8I 6", PMO816"'.

Above, we have shown a general method that connects the silicon gate CMOS process and the bipolar process. This method is used to simultaneously create the source/drain of U and NMO8 and the emitter of the bipolar element, and to take out the electrode of NMO8. After this, it is necessary to form the contact window after forming the passivation film 15. In other words, the emitter diffusion window 14 should be made sufficiently larger than the emitter contact 16 to account for mask misalignment.

However, no improvement in the performance of bipolar devices can be expected.

This problem will be further explained using FIGS. 2(a) and 2(b). FIGS. 2(a) and 2(b) show the parts of the two pibo elements shown in FIGS. 1(a) and 1(b). FIG. 2(a) shows a state in which the emitter 9 is formed through the emitter diffusion window 14. As mentioned above, after this, NMO
A passivation film is formed to cover the surface of the emitter, but it is also formed on the emitter, as shown in Figure 2(b).
It is necessary to form a contact window 16 in this film as shown in FIG. For example, when using a process with a minimum processing size of 2 μm, it is necessary to allow a mask alignment deviation of 2 μm (β in the figure) for the width of the contact window 16 of 2 μm (α in the figure), so the first emitter window 16 has a width of 6 μm. Therefore, it is not possible to reduce the emitter width to the minimum processing dimension of 2 μm.

On the other hand, in the process of manufacturing only bipolar elements, the washed emitter structure shown in FIG. 3 is used to miniaturize the emitter (which leads to higher performance of the bipolar element). In this method, as shown in FIG. 3(d), an emitter diffusion window 14 is added to the passivation xi 5.
After forming the emitter 9 through the emitter 9, as shown in FIG. 3(b), the emitter diffusion window 14 is left as it is (therefore, no passivation film is formed after this) and photoetching for contact is performed. The photoresist 17 does not have a window on the emitter, but has a window 16' on the base.

FIG. 3(C) shows the electrode 18, 18' after removing the resist film.
This shows the state in which it has been formed.

According to the method shown in FIG.
The device performance is also greatly improved compared to the width of the emitter 9 shown in the figure (6 μm). That is, the base resistance on the lower side of the emitter 9 is reduced to 1/3, and the junction capacitance of the emitter 9 is also reduced to 1/3.

A conventional method of using polysilicon for the emitter 9 will be explained with reference to FIG. In order to improve the performance of the device, when the junction depth of the emitter 9 is made shallow (for example, 0.2 to 0.3 μm), it is still necessary to prevent the electrode from reacting with the underlying silicon layer and deteriorating the junction characteristics. In order to improve the injection efficiency of the emitter 9,
This is a method of adding a polysilicon layer on top of the emitter 9. FIG. 4(a) shows that after forming an emitter diffusion window, a polysilicon layer is formed on the entire surface, and an impurity for the emitter 9 is doped from above the polysilicon to form an emitter 9. A polysilicon layer 19 is patterned on top. Next, as in FIG. 3(b), leave the emitter 9 as it is and open the base contact window 16'.
Electrodes 18, 18' are formed as shown in FIG. 4(b).

Figure 5 shows the wash emitter structure in Figure 3 simply as B.
This figure shows the case where it is applied to a 10MO8 structure. , P.M.O.
8. After forming the NMO8 element and the passivation film 15, open the emitter window 14 and form the emitter 9,
Next, open the contact windows in other parts as shown in FIG. 3(C).

If this method is used, an emitter corresponding to the minimum processing size can be formed in terms of structure, but it causes large characteristic fluctuations in the MO8 element. For example, when doping arsenic as an impurity to a depth of 0.3 μm to improve the performance of a bipolar device,
As the thermal diffusion conditions for arsenic or the annealing conditions after ion implantation, heat treatment, for example, at 1000 C for 60 minutes or more is usually required.

By this heat treatment, the depth of the source/drain junction of the previously formed PMO8 and NMO8 becomes deep, and therefore the lateral spread of the junction becomes large, and the effective channel length becomes short. For example, in the case of a channel length with a design dimension of 2 μm, an effective channel length of 1.4 μm is obtained for a normal source/drain junction depth of 0.3 μm, but due to the heat treatment of the emitter, the junction depth becomes deeper ( For example, 0.5μm
), the effective channel length becomes 1 μm, which causes a decrease in breakdown voltage due to punch-through and a large change in the threshold 1 direct voltage due to the short channel effect.

In this way, if one attempts to create a B i 0 MO8 process by simply combining a highly integrated CMOS process and a high-speed bipolar process, the characteristics of one of the elements must be sacrificed.

The purpose of the present invention is to combine a highly integrated CMOS process with a high-speed bipolar process to create a high-performance B i 0M
The object of the present invention is to provide an element structure that combines the CMo5 process without sacrificing the characteristics of bipolar elements when producing the O8 process.

The present invention is a method of forming fine emitters by making the most of the steps used in the CMOS process. That is, after forming the gate oxide film, a fine emitter window is opened, and then polysilicon used for the gate of the MO8 element is formed.
The impurity doping performed to lower the resistance of polysilicon also serves as emitter doping, and
This is a method in which a polysilicon emitter is processed on the emitter at the same time as the polysilicon gate is processed.

The present invention will be explained below using the embodiment shown in FIG.

FIG. 6(a) shows a gate oxide film 13 for an MO8 element.
After forming the emitter window 14 to a thickness of 0.00 mm, the dimension is 2 μm.
The width is shown formed by photoetching. An outline of the steps leading to this structure will be explained below. First, N”, P+
After forming the buried layers (each 2°4), an epitaxial growth layer 3 is formed to a thickness of 4 μm. Next, the Pijl well 5 was formed to a depth of 38 m1 by ion implantation and heat treatment.
It is formed to have a density of 5 x 10 "7 cm".

Next, by selective oxidation using St, N, and films as masks,
An oxide film 10 for isolation is formed to a thickness of 1 μm. Next, the paste layer 6 of the bipolar element is formed by a thermal diffusion method or an ion implantation method to a depth of 0.6 μm and a single layer resistance of 300 Ω/hole. Thereafter, a gate oxide film 13 is formed to a thickness of 500 nm.

Since the thin gate oxide and film are photo-etched, a fine emitter pattern can be created with high precision.

FIG. 6(b) shows that, subsequent to FIG. 6(a), a polysilicon layer 12 of 0.3 μm was formed by CVD to be used for the gate of the MO8 element.
m thickness, and then arsenic ions were added to lX1016/
- After implanting the entire surface, heat treatment is performed for 100 minutes at 1ooot:', and the resistance of the poly7 silicon that will become the gate is reduced to 200.
At the same time, the emitter 9 is formed to a depth of 0.4 μm through the entire emitter window 14.

FIG. 6 (Q shows polysilicon +112 etched by dry etching using photoresist as a mask,
Gate 12 and emitter polysilicon layer 191r of MO8 element: The state in which they are formed is shown. Note that the width of the polysilicon emitter 19 needs to be larger than the emitter window 14 by an allowance for mask alignment (for example, 2 μm on one side).

By this stage, a bipolar element has been formed, and the current amplification factor is also adjusted to about 100 by heat treatment after arsenic ion implantation. In addition, the heat treatment of the noquipolar element is 100OC.
However, the subsequent MOB element formation temperature is 9500℃.
It is carried out at a low temperature below (2000) to reduce the influence on the characteristic fluctuations of the Ibora element.

FIG. 6(d) shows that after FIG. 6(c), the source/drain 8 of 2MO8 is doped by boron ion implantation and the source/drain 7 of NMO8 is doped by arsenic ion implantation using the 5i02 film as a mask. 0.3μ by heat treatment
Form to a depth of m. Thereafter, phosphor glass 15 is formed as a passivation film to a thickness of 0.5 μm by CVD, and then contact windows for each element are simultaneously formed. Emitter 16, base 16', NMO respectively
8 source/drain 16'', 2MO8 source/drain 16'''.

The emitter structure t of the completed bipolar element differs from the conventional emitter structure shown in FIG. 4(b) in that a passivation film is provided on the polysilicon and a contact window is opened in the polysilicon.

Note that FIG. 6 shows one embodiment of the present invention, and various changes can be considered in the intermediate steps. For example, phosphorus may be used instead of arsenic as the impurity doped into the polysilicon layer in FIG. 6(b). In addition, some of the steps in FIGS. 6(b) and 6(C) are replaced, and after forming the polysilicon layer, the gate 12 and emitter polysilicon 19 are first formed, and then the impurity doping step is performed. Very good. Furthermore, it is also possible to form an emitter by forming polysilicon doped with arsenic, for example, and heat-treating it.

In the figure, 17 is a photoresist film, 18 is an emitter electrode, 18' is a base electrode, and 19 is an emitter polysilicon.

According to the present invention, the following effects can be obtained.

(1) Since the emitter is photo-etched on a thin gate oxide film, dimensional accuracy can be improved compared to the conventional method of opening a window on a thick (for example, 0.5 μm) passivation film.

(2) Since the emitter window formed on the gate oxide film is fixed with polysilicon, a fine emitter width corresponding to the minimum processing size can be achieved regardless of the subsequent process, which improves the high performance of bipolar devices. becomes possible.

(3) Since the emitter is formed using the process of forming the MO8 element, the only additional process for forming the emitter is the process of opening the emitter window.
The process can be simplified as an iCMUS process.

(4) After forming the bipolar element which requires a lot of heat treatment first, M
Since an O8 element is formed, it is easy to control the depth of a shallow source/drain junction, and a fine MO8 element can be formed. In other words, highly integrated MO8 in BiCMUS process
LSLIO8 can be applied as is.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are cross-sectional views of the conventional B1CMo5 process, and Figures 2 (a) and (b) are cross-sectional views of the conventional BiCMUS process.
Cross-sectional view of the bipolar element part of the process, Figure 3 (a)
, (b) and (c) are 1-dimensional views showing a conventional emitter formation method for a bipolar device, and FIGS. 4(a) and (b) are cross-sectional views of a bipolar device using a conventional polysilicon emitter. , Figure 6 (a), (b), (
c) and (d) are cross-sectional views showing examples of the present invention. l...P type substrate, 2...N1 embedded j-13...N
Epitaxial layer, 4...P4' isolation layer, 5...P well, 6...Pace, 7...NMO
8 source train, 8...2 MO8 source/drain, 9...emitter, 10...field oxide film, 11...mask oxide film, 12...polysilicon gate, 13...・Gate oxide film, 14... Emitter diffusion window, 15... Pat/pation film, 16...
Emitter contact window, 16'... Base contact window 16 //... NMO8 source/drain contact window, 16'''... PMOS source/drain contact window, 17... Photoresist film, 18...・
Emitsuda 1 pole, 18'...Base pole, 19...Emitter polysilicon. Bamboo 2 Sen No. 30 No. 4 - Figure No. 5 Prison procedure amendment (method) % formula % Display of the case 1982 Patent Application No. 105411 Name of the invention Semiconductor device amendment person hat 1 and groan! Patent applicant fl Address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo Name: T! 1lo1 Hitachi Co., Ltd. (1st place Representative 3 1) Osamu Katsu Shigeyo Residence 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo Drawing (Figure 6(d)) -2

Claims (1)

[Claims] 1. A MOS transistor (MOS having a silicon gate) formed on an emitter diffusion window formed in an insulating film with a thickness of 0.1 μm or less on the transistor and emitter, and the area thereof is larger than the emitter diffusion window. A semiconductor device characterized in that bipolar transistors having a polysilicon layer are arranged on the same substrate. 2. Claim 1 states that an insulating film is further provided on the polysilicon layer, and a contact window for taking out the emitter electrode is provided in the polysilicon region of the insulating film. Characteristic semiconductor devices.